./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:50:02,895 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:50:02,972 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:50:02,975 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:50:02,975 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:50:02,975 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:50:03,002 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:50:03,002 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:50:03,003 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:50:03,003 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:50:03,003 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:50:03,003 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:50:03,003 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:50:03,004 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:50:03,004 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:50:03,004 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:50:03,004 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2025-02-06 19:50:03,228 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:50:03,233 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:50:03,235 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:50:03,236 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:50:03,236 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:50:03,237 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2025-02-06 19:50:04,384 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a7f59c9c1/c3da86d0415e4bd397f3f1a78bc3b0d0/FLAG8d097608f [2025-02-06 19:50:04,691 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:50:04,692 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2025-02-06 19:50:04,700 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a7f59c9c1/c3da86d0415e4bd397f3f1a78bc3b0d0/FLAG8d097608f [2025-02-06 19:50:04,982 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a7f59c9c1/c3da86d0415e4bd397f3f1a78bc3b0d0 [2025-02-06 19:50:04,985 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:50:04,986 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:50:04,987 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:04,987 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:50:04,990 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:50:04,991 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:04" (1/1) ... [2025-02-06 19:50:04,992 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@77777ed1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:04, skipping insertion in model container [2025-02-06 19:50:04,992 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:04" (1/1) ... [2025-02-06 19:50:05,007 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:50:05,120 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:05,135 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:50:05,159 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:05,174 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:50:05,175 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05 WrapperNode [2025-02-06 19:50:05,175 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:05,176 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:05,176 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:50:05,176 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:50:05,180 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,188 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,208 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 339 [2025-02-06 19:50:05,209 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:05,209 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:50:05,209 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:50:05,210 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:50:05,215 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,216 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,217 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,224 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:50:05,225 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,225 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,228 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,232 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,233 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,233 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,235 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:50:05,235 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:50:05,235 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:50:05,235 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:50:05,236 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (1/1) ... [2025-02-06 19:50:05,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:05,248 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:05,261 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:05,265 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:50:05,281 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:50:05,281 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:50:05,281 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:50:05,281 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:50:05,331 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:50:05,332 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:50:05,606 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2025-02-06 19:50:05,606 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:50:05,614 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:50:05,614 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:50:05,615 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:05 BoogieIcfgContainer [2025-02-06 19:50:05,615 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:50:05,616 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:50:05,616 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:50:05,620 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:50:05,621 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:05,621 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:04" (1/3) ... [2025-02-06 19:50:05,622 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e10f600 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:05, skipping insertion in model container [2025-02-06 19:50:05,622 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:05,622 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:05" (2/3) ... [2025-02-06 19:50:05,622 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2e10f600 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:05, skipping insertion in model container [2025-02-06 19:50:05,622 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:05,623 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:05" (3/3) ... [2025-02-06 19:50:05,623 INFO L363 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2025-02-06 19:50:05,659 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:50:05,659 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:50:05,659 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:50:05,659 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:50:05,659 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:50:05,659 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:50:05,659 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:50:05,659 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:50:05,663 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:05,675 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:05,676 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:05,676 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:05,681 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,681 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,681 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:50:05,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:05,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:05,685 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:05,685 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:05,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,691 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:05,692 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:05,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:05,696 INFO L85 PathProgramCache]: Analyzing trace with hash -2014143597, now seen corresponding path program 1 times [2025-02-06 19:50:05,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:05,701 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363727720] [2025-02-06 19:50:05,701 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:05,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:05,751 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:05,763 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:05,763 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:05,763 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:05,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:05,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:05,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1363727720] [2025-02-06 19:50:05,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1363727720] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:05,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:05,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:05,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042858863] [2025-02-06 19:50:05,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:05,830 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:05,831 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:05,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1308095898, now seen corresponding path program 1 times [2025-02-06 19:50:05,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:05,831 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1417817003] [2025-02-06 19:50:05,831 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:05,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:05,836 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-02-06 19:50:05,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-02-06 19:50:05,837 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:05,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:05,846 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:05,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:05,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1417817003] [2025-02-06 19:50:05,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1417817003] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:05,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:05,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:05,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755726952] [2025-02-06 19:50:05,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:05,848 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:05,849 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:05,864 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:05,865 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:05,866 INFO L87 Difference]: Start difference. First operand has 126 states, 125 states have (on average 1.568) internal successors, (196), 125 states have internal predecessors, (196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:05,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:05,890 INFO L93 Difference]: Finished difference Result 124 states and 190 transitions. [2025-02-06 19:50:05,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 124 states and 190 transitions. [2025-02-06 19:50:05,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:05,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 124 states to 117 states and 183 transitions. [2025-02-06 19:50:05,903 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:05,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:05,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 183 transitions. [2025-02-06 19:50:05,906 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:05,907 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-02-06 19:50:05,916 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 183 transitions. [2025-02-06 19:50:05,927 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:05,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.564102564102564) internal successors, (183), 116 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:05,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 183 transitions. [2025-02-06 19:50:05,932 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-02-06 19:50:05,934 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:05,936 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 183 transitions. [2025-02-06 19:50:05,937 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:50:05,937 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 183 transitions. [2025-02-06 19:50:05,939 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:05,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:05,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:05,942 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,942 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:05,942 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume !(~b0_val~0 != ~b0_val_t~0);" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:05,942 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:05,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:05,942 INFO L85 PathProgramCache]: Analyzing trace with hash 611581221, now seen corresponding path program 1 times [2025-02-06 19:50:05,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:05,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1465776176] [2025-02-06 19:50:05,944 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:05,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:05,952 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-02-06 19:50:05,964 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-02-06 19:50:05,964 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:05,964 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,075 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,075 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,075 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1465776176] [2025-02-06 19:50:06,075 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1465776176] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:06,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1536884036] [2025-02-06 19:50:06,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,076 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,076 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 1 times [2025-02-06 19:50:06,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1321235918] [2025-02-06 19:50:06,076 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,091 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,096 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,097 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,097 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,169 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1321235918] [2025-02-06 19:50:06,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1321235918] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,170 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,170 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [927740638] [2025-02-06 19:50:06,170 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,170 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,170 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,170 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:06,170 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:06,171 INFO L87 Difference]: Start difference. First operand 117 states and 183 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,191 INFO L93 Difference]: Finished difference Result 117 states and 182 transitions. [2025-02-06 19:50:06,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 182 transitions. [2025-02-06 19:50:06,195 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 182 transitions. [2025-02-06 19:50:06,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 182 transitions. [2025-02-06 19:50:06,197 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,197 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-02-06 19:50:06,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 182 transitions. [2025-02-06 19:50:06,206 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5555555555555556) internal successors, (182), 116 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 182 transitions. [2025-02-06 19:50:06,207 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-02-06 19:50:06,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:06,210 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 182 transitions. [2025-02-06 19:50:06,210 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:50:06,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 182 transitions. [2025-02-06 19:50:06,211 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,212 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,212 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,212 INFO L85 PathProgramCache]: Analyzing trace with hash -350032796, now seen corresponding path program 1 times [2025-02-06 19:50:06,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469408065] [2025-02-06 19:50:06,212 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-02-06 19:50:06,231 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-02-06 19:50:06,231 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,231 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469408065] [2025-02-06 19:50:06,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469408065] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:06,250 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1686144392] [2025-02-06 19:50:06,250 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,251 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,251 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,251 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 2 times [2025-02-06 19:50:06,251 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,251 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1610742001] [2025-02-06 19:50:06,251 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:06,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,257 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,262 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,262 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:06,262 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1610742001] [2025-02-06 19:50:06,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1610742001] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1641843498] [2025-02-06 19:50:06,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,318 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,318 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:06,318 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:06,319 INFO L87 Difference]: Start difference. First operand 117 states and 182 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,334 INFO L93 Difference]: Finished difference Result 117 states and 181 transitions. [2025-02-06 19:50:06,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 181 transitions. [2025-02-06 19:50:06,336 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 181 transitions. [2025-02-06 19:50:06,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,338 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,340 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 181 transitions. [2025-02-06 19:50:06,340 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,340 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-02-06 19:50:06,340 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 181 transitions. [2025-02-06 19:50:06,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.547008547008547) internal successors, (181), 116 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 181 transitions. [2025-02-06 19:50:06,346 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-02-06 19:50:06,347 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:06,347 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 181 transitions. [2025-02-06 19:50:06,348 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:50:06,348 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 181 transitions. [2025-02-06 19:50:06,349 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,349 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,349 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,350 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,350 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,350 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume !(~b1_val~0 != ~b1_val_t~0);" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,350 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,351 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,351 INFO L85 PathProgramCache]: Analyzing trace with hash -357443661, now seen corresponding path program 1 times [2025-02-06 19:50:06,351 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,351 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1883141181] [2025-02-06 19:50:06,351 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,351 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,358 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-02-06 19:50:06,361 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-02-06 19:50:06,361 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1883141181] [2025-02-06 19:50:06,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1883141181] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:06,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1823690166] [2025-02-06 19:50:06,407 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,408 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,408 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,408 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 3 times [2025-02-06 19:50:06,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119977914] [2025-02-06 19:50:06,408 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:06,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,416 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,421 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,423 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:06,423 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119977914] [2025-02-06 19:50:06,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119977914] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,454 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,454 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2140312518] [2025-02-06 19:50:06,454 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,454 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,454 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,454 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:06,454 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:06,455 INFO L87 Difference]: Start difference. First operand 117 states and 181 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,491 INFO L93 Difference]: Finished difference Result 117 states and 180 transitions. [2025-02-06 19:50:06,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 180 transitions. [2025-02-06 19:50:06,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 180 transitions. [2025-02-06 19:50:06,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 180 transitions. [2025-02-06 19:50:06,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,496 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-02-06 19:50:06,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 180 transitions. [2025-02-06 19:50:06,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5384615384615385) internal successors, (180), 116 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 180 transitions. [2025-02-06 19:50:06,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-02-06 19:50:06,501 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:06,502 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 180 transitions. [2025-02-06 19:50:06,502 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:50:06,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 180 transitions. [2025-02-06 19:50:06,502 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,506 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,507 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,507 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,507 INFO L85 PathProgramCache]: Analyzing trace with hash -388463468, now seen corresponding path program 1 times [2025-02-06 19:50:06,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [173446762] [2025-02-06 19:50:06,507 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,513 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-02-06 19:50:06,516 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-02-06 19:50:06,516 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,516 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,530 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [173446762] [2025-02-06 19:50:06,530 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [173446762] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,530 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,530 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:06,530 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [987525041] [2025-02-06 19:50:06,530 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,530 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,530 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,530 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 4 times [2025-02-06 19:50:06,530 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,530 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576346602] [2025-02-06 19:50:06,531 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:50:06,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,535 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 39 statements into 2 equivalence classes. [2025-02-06 19:50:06,537 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,538 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-02-06 19:50:06,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,566 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1576346602] [2025-02-06 19:50:06,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1576346602] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,568 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,568 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,568 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311161950] [2025-02-06 19:50:06,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,568 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,569 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:06,569 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:06,569 INFO L87 Difference]: Start difference. First operand 117 states and 180 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,580 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,580 INFO L93 Difference]: Finished difference Result 117 states and 179 transitions. [2025-02-06 19:50:06,580 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 179 transitions. [2025-02-06 19:50:06,581 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 179 transitions. [2025-02-06 19:50:06,581 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 179 transitions. [2025-02-06 19:50:06,582 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,582 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-02-06 19:50:06,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 179 transitions. [2025-02-06 19:50:06,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5299145299145298) internal successors, (179), 116 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 179 transitions. [2025-02-06 19:50:06,612 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-02-06 19:50:06,613 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:06,613 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 179 transitions. [2025-02-06 19:50:06,613 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:50:06,613 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 179 transitions. [2025-02-06 19:50:06,614 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,614 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,614 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,615 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume !(~d0_val~0 != ~d0_val_t~0);" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,615 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,617 INFO L85 PathProgramCache]: Analyzing trace with hash 1243696292, now seen corresponding path program 1 times [2025-02-06 19:50:06,618 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,618 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826936913] [2025-02-06 19:50:06,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,627 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:50:06,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:50:06,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826936913] [2025-02-06 19:50:06,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826936913] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:06,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281847837] [2025-02-06 19:50:06,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,692 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,693 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 5 times [2025-02-06 19:50:06,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1932289465] [2025-02-06 19:50:06,695 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:50:06,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,700 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,703 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,705 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:06,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1932289465] [2025-02-06 19:50:06,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1932289465] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [227894776] [2025-02-06 19:50:06,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,734 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,734 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,735 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:06,735 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:06,735 INFO L87 Difference]: Start difference. First operand 117 states and 179 transitions. cyclomatic complexity: 63 Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,758 INFO L93 Difference]: Finished difference Result 117 states and 178 transitions. [2025-02-06 19:50:06,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 178 transitions. [2025-02-06 19:50:06,759 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,760 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 178 transitions. [2025-02-06 19:50:06,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,760 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,760 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 178 transitions. [2025-02-06 19:50:06,760 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,760 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-02-06 19:50:06,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 178 transitions. [2025-02-06 19:50:06,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5213675213675213) internal successors, (178), 116 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 178 transitions. [2025-02-06 19:50:06,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-02-06 19:50:06,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:06,763 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 178 transitions. [2025-02-06 19:50:06,764 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:50:06,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 178 transitions. [2025-02-06 19:50:06,764 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,765 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,765 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,765 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,766 INFO L85 PathProgramCache]: Analyzing trace with hash -974061661, now seen corresponding path program 1 times [2025-02-06 19:50:06,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457897656] [2025-02-06 19:50:06,766 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,769 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:50:06,771 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:50:06,771 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,772 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,784 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,785 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,785 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1457897656] [2025-02-06 19:50:06,785 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1457897656] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,785 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,785 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:06,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350109327] [2025-02-06 19:50:06,785 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,785 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,786 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,786 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 6 times [2025-02-06 19:50:06,786 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,786 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158040105] [2025-02-06 19:50:06,786 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:50:06,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,790 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,792 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,792 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:50:06,792 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,821 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,821 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [158040105] [2025-02-06 19:50:06,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [158040105] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,821 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694116406] [2025-02-06 19:50:06,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,821 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,821 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:06,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:06,822 INFO L87 Difference]: Start difference. First operand 117 states and 178 transitions. cyclomatic complexity: 62 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:06,832 INFO L93 Difference]: Finished difference Result 117 states and 177 transitions. [2025-02-06 19:50:06,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117 states and 177 transitions. [2025-02-06 19:50:06,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,834 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117 states to 117 states and 177 transitions. [2025-02-06 19:50:06,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117 [2025-02-06 19:50:06,835 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117 [2025-02-06 19:50:06,835 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117 states and 177 transitions. [2025-02-06 19:50:06,835 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:06,835 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-02-06 19:50:06,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states and 177 transitions. [2025-02-06 19:50:06,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2025-02-06 19:50:06,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117 states, 117 states have (on average 1.5128205128205128) internal successors, (177), 116 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:06,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 177 transitions. [2025-02-06 19:50:06,837 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-02-06 19:50:06,841 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:06,842 INFO L432 stractBuchiCegarLoop]: Abstraction has 117 states and 177 transitions. [2025-02-06 19:50:06,842 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:50:06,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117 states and 177 transitions. [2025-02-06 19:50:06,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:06,842 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:06,842 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:06,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:06,843 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:06,843 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:06,843 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,843 INFO L85 PathProgramCache]: Analyzing trace with hash -795926540, now seen corresponding path program 1 times [2025-02-06 19:50:06,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [831580785] [2025-02-06 19:50:06,844 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:06,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:06,858 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:06,858 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,858 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,916 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,916 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [831580785] [2025-02-06 19:50:06,916 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [831580785] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,916 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,916 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:06,916 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1348080503] [2025-02-06 19:50:06,916 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,916 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:06,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:06,917 INFO L85 PathProgramCache]: Analyzing trace with hash 122796901, now seen corresponding path program 7 times [2025-02-06 19:50:06,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:06,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864676869] [2025-02-06 19:50:06,917 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:50:06,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:06,924 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:06,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:06,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:06,930 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:06,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:06,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:06,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864676869] [2025-02-06 19:50:06,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864676869] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:06,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:06,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:06,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1517814345] [2025-02-06 19:50:06,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:06,963 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:06,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:06,964 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:06,964 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:06,965 INFO L87 Difference]: Start difference. First operand 117 states and 177 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 7.8) internal successors, (39), 5 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:07,000 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:07,001 INFO L93 Difference]: Finished difference Result 122 states and 182 transitions. [2025-02-06 19:50:07,001 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 182 transitions. [2025-02-06 19:50:07,002 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2025-02-06 19:50:07,002 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 122 states and 182 transitions. [2025-02-06 19:50:07,003 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2025-02-06 19:50:07,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2025-02-06 19:50:07,004 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 182 transitions. [2025-02-06 19:50:07,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:07,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122 states and 182 transitions. [2025-02-06 19:50:07,004 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 182 transitions. [2025-02-06 19:50:07,006 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 120. [2025-02-06 19:50:07,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 120 states, 120 states have (on average 1.5) internal successors, (180), 119 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:07,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 180 transitions. [2025-02-06 19:50:07,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 120 states and 180 transitions. [2025-02-06 19:50:07,007 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:07,008 INFO L432 stractBuchiCegarLoop]: Abstraction has 120 states and 180 transitions. [2025-02-06 19:50:07,008 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:50:07,008 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 120 states and 180 transitions. [2025-02-06 19:50:07,008 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2025-02-06 19:50:07,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:07,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:07,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:07,009 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:07,009 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:07,009 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:07,009 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:07,009 INFO L85 PathProgramCache]: Analyzing trace with hash -795926540, now seen corresponding path program 2 times [2025-02-06 19:50:07,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:07,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1018731352] [2025-02-06 19:50:07,010 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:07,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:07,013 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:07,015 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:07,015 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:07,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:07,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:07,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:07,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1018731352] [2025-02-06 19:50:07,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1018731352] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:07,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:07,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:07,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421556181] [2025-02-06 19:50:07,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:07,045 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:07,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:07,045 INFO L85 PathProgramCache]: Analyzing trace with hash -721208601, now seen corresponding path program 1 times [2025-02-06 19:50:07,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:07,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848462738] [2025-02-06 19:50:07,046 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:07,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:07,049 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:07,058 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:07,058 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:07,058 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:07,058 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:07,076 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:07,079 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:07,079 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:07,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:07,091 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:07,357 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:07,358 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:07,358 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:07,358 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:07,358 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-02-06 19:50:07,358 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,358 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:07,358 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:07,358 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2025-02-06 19:50:07,358 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:07,359 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:07,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,382 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,401 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,406 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,414 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,426 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,432 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,434 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,436 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,438 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,581 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:07,581 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-02-06 19:50:07,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,587 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,590 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-02-06 19:50:07,591 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:07,591 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:07,605 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-02-06 19:50:07,605 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-02-06 19:50:07,612 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-02-06 19:50:07,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,612 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,614 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,616 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-02-06 19:50:07,617 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:07,617 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:07,638 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:07,638 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,639 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,640 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,642 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-02-06 19:50:07,642 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-02-06 19:50:07,642 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:07,661 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-02-06 19:50:07,672 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-02-06 19:50:07,672 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:07,672 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:07,672 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:07,672 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:07,672 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-02-06 19:50:07,672 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,672 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:07,672 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:07,672 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration9_Loop [2025-02-06 19:50:07,672 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:07,672 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:07,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:07,884 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:07,887 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-02-06 19:50:07,887 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,887 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,889 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,891 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-02-06 19:50:07,892 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:07,905 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:07,905 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:07,906 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:07,906 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:07,906 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:07,909 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:07,909 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:07,910 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:07,916 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:07,916 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,916 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,919 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,920 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-02-06 19:50:07,921 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:07,931 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:07,932 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:07,932 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:07,932 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:07,932 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:07,933 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:07,933 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:07,934 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:07,940 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-02-06 19:50:07,941 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,941 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,943 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,944 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-02-06 19:50:07,945 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:07,957 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:07,957 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:07,957 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:07,957 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:07,957 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:07,958 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:07,958 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:07,959 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:07,965 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:07,965 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:07,966 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:07,968 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:07,976 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-02-06 19:50:07,978 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:07,989 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:07,989 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:07,989 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:07,989 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:07,989 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:07,990 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:07,990 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:07,992 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-02-06 19:50:07,995 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-02-06 19:50:07,997 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-02-06 19:50:08,000 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:08,000 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:08,002 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:08,004 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-02-06 19:50:08,005 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-02-06 19:50:08,005 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-02-06 19:50:08,005 INFO L474 LassoAnalysis]: Proved termination. [2025-02-06 19:50:08,005 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2025-02-06 19:50:08,013 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-02-06 19:50:08,016 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-02-06 19:50:08,048 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:08,062 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:08,082 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:08,083 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:08,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:08,084 INFO L256 TraceCheckSpWp]: Trace formula consists of 173 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-02-06 19:50:08,086 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:08,154 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:08,164 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:08,164 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:08,164 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:08,165 INFO L256 TraceCheckSpWp]: Trace formula consists of 96 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-02-06 19:50:08,166 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:08,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:08,278 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-02-06 19:50:08,279 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61 Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:08,354 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 120 states and 180 transitions. cyclomatic complexity: 61. Second operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 274 states and 420 transitions. Complement of second has 5 states. [2025-02-06 19:50:08,355 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-02-06 19:50:08,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 15.8) internal successors, (79), 5 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:08,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2025-02-06 19:50:08,358 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 39 letters. [2025-02-06 19:50:08,362 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:08,362 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 79 letters. Loop has 39 letters. [2025-02-06 19:50:08,363 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:08,363 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 40 letters. Loop has 78 letters. [2025-02-06 19:50:08,364 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:08,364 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 274 states and 420 transitions. [2025-02-06 19:50:08,369 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-02-06 19:50:08,371 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 274 states to 274 states and 420 transitions. [2025-02-06 19:50:08,371 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-02-06 19:50:08,371 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 198 [2025-02-06 19:50:08,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 274 states and 420 transitions. [2025-02-06 19:50:08,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:08,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 274 states and 420 transitions. [2025-02-06 19:50:08,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states and 420 transitions. [2025-02-06 19:50:08,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 271. [2025-02-06 19:50:08,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5387453874538746) internal successors, (417), 270 states have internal predecessors, (417), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:08,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 417 transitions. [2025-02-06 19:50:08,378 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 417 transitions. [2025-02-06 19:50:08,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:08,384 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:08,384 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:08,384 INFO L87 Difference]: Start difference. First operand 271 states and 417 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:08,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:08,411 INFO L93 Difference]: Finished difference Result 271 states and 416 transitions. [2025-02-06 19:50:08,411 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 271 states and 416 transitions. [2025-02-06 19:50:08,412 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-02-06 19:50:08,416 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 271 states to 271 states and 416 transitions. [2025-02-06 19:50:08,416 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-02-06 19:50:08,416 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-02-06 19:50:08,416 INFO L73 IsDeterministic]: Start isDeterministic. Operand 271 states and 416 transitions. [2025-02-06 19:50:08,417 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:08,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-02-06 19:50:08,421 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states and 416 transitions. [2025-02-06 19:50:08,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 271. [2025-02-06 19:50:08,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 271 states, 271 states have (on average 1.5350553505535056) internal successors, (416), 270 states have internal predecessors, (416), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:08,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 271 states to 271 states and 416 transitions. [2025-02-06 19:50:08,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-02-06 19:50:08,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:08,431 INFO L432 stractBuchiCegarLoop]: Abstraction has 271 states and 416 transitions. [2025-02-06 19:50:08,433 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:50:08,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 271 states and 416 transitions. [2025-02-06 19:50:08,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 148 [2025-02-06 19:50:08,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:08,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:08,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:08,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:08,436 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" [2025-02-06 19:50:08,436 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume !(0 == ~d1_ev~0);" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume !(1 == ~d1_ev~0);" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" "assume true;" [2025-02-06 19:50:08,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:08,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1121676761, now seen corresponding path program 1 times [2025-02-06 19:50:08,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:08,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [342039371] [2025-02-06 19:50:08,438 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:08,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:08,448 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:08,451 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:08,451 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:08,451 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:08,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:08,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:08,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [342039371] [2025-02-06 19:50:08,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [342039371] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:08,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:08,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:08,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [489803056] [2025-02-06 19:50:08,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:08,472 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:08,472 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:08,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1693610513, now seen corresponding path program 1 times [2025-02-06 19:50:08,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:08,473 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [910582971] [2025-02-06 19:50:08,473 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:08,473 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:08,478 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:08,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:08,485 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:08,485 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:08,485 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:08,487 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:08,489 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:08,491 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:08,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:08,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:08,651 ERROR L418 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Exception during sending of exit command (exit): Broken pipe [2025-02-06 19:50:08,653 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-02-06 19:50:08,778 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:08,778 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:08,778 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:08,778 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:08,779 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-02-06 19:50:08,779 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:08,779 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:08,779 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:08,779 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-02-06 19:50:08,779 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:08,779 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:08,780 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,791 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,809 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:08,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,029 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:09,029 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-02-06 19:50:09,030 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,030 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:09,035 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:09,036 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-02-06 19:50:09,039 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:09,039 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:09,056 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-02-06 19:50:09,056 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,056 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:09,062 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:09,064 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-02-06 19:50:09,065 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-02-06 19:50:09,065 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:09,079 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-02-06 19:50:09,085 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2025-02-06 19:50:09,086 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:09,086 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:09,086 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:09,086 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:09,086 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-02-06 19:50:09,086 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,086 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:09,086 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:09,086 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration10_Loop [2025-02-06 19:50:09,086 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:09,086 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:09,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,101 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,115 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,123 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,129 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,131 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,138 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,140 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,151 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,157 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,167 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,178 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,186 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,195 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,210 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,216 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:09,420 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:09,421 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-02-06 19:50:09,421 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,421 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:09,424 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:09,425 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-02-06 19:50:09,427 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:09,437 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:09,437 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:09,437 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:09,437 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:09,437 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:09,438 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:09,438 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:09,441 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:09,449 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2025-02-06 19:50:09,450 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,450 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:09,452 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:09,453 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-02-06 19:50:09,455 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:09,465 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:09,465 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:09,465 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:09,465 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:09,465 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:09,467 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:09,467 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:09,470 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-02-06 19:50:09,473 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-02-06 19:50:09,473 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-02-06 19:50:09,473 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:09,473 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:09,475 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:09,479 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-02-06 19:50:09,480 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-02-06 19:50:09,480 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-02-06 19:50:09,480 INFO L474 LassoAnalysis]: Proved termination. [2025-02-06 19:50:09,480 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d0_ev~0) = -1*~d0_ev~0 + 1 Supporting invariants [] [2025-02-06 19:50:09,486 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:09,487 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-02-06 19:50:09,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:09,521 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:09,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:09,556 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:09,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:09,561 INFO L256 TraceCheckSpWp]: Trace formula consists of 177 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-02-06 19:50:09,562 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:09,664 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:09,682 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:09,682 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:09,682 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:09,687 INFO L256 TraceCheckSpWp]: Trace formula consists of 90 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-02-06 19:50:09,688 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:09,878 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:09,879 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-02-06 19:50:09,879 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148 Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:09,954 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 271 states and 416 transitions. cyclomatic complexity: 148. Second operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 734 states and 1142 transitions. Complement of second has 5 states. [2025-02-06 19:50:09,955 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-02-06 19:50:09,956 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.0) internal successors, (80), 5 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:09,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2025-02-06 19:50:09,961 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 39 letters. [2025-02-06 19:50:09,961 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:09,961 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 80 letters. Loop has 39 letters. [2025-02-06 19:50:09,961 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:09,961 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 41 letters. Loop has 78 letters. [2025-02-06 19:50:09,962 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:09,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 734 states and 1142 transitions. [2025-02-06 19:50:09,970 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 296 [2025-02-06 19:50:09,982 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 734 states to 734 states and 1142 transitions. [2025-02-06 19:50:09,982 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 346 [2025-02-06 19:50:09,983 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-02-06 19:50:09,983 INFO L73 IsDeterministic]: Start isDeterministic. Operand 734 states and 1142 transitions. [2025-02-06 19:50:09,983 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:09,983 INFO L218 hiAutomatonCegarLoop]: Abstraction has 734 states and 1142 transitions. [2025-02-06 19:50:09,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 734 states and 1142 transitions. [2025-02-06 19:50:10,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 734 to 729. [2025-02-06 19:50:10,012 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 729 states, 729 states have (on average 1.5541838134430728) internal successors, (1133), 728 states have internal predecessors, (1133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 729 states to 729 states and 1133 transitions. [2025-02-06 19:50:10,021 INFO L240 hiAutomatonCegarLoop]: Abstraction has 729 states and 1133 transitions. [2025-02-06 19:50:10,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,022 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,022 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,022 INFO L87 Difference]: Start difference. First operand 729 states and 1133 transitions. Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,062 INFO L93 Difference]: Finished difference Result 909 states and 1378 transitions. [2025-02-06 19:50:10,062 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 909 states and 1378 transitions. [2025-02-06 19:50:10,067 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-02-06 19:50:10,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 909 states to 909 states and 1378 transitions. [2025-02-06 19:50:10,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2025-02-06 19:50:10,072 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2025-02-06 19:50:10,072 INFO L73 IsDeterministic]: Start isDeterministic. Operand 909 states and 1378 transitions. [2025-02-06 19:50:10,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-02-06 19:50:10,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 909 states and 1378 transitions. [2025-02-06 19:50:10,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 909 to 909. [2025-02-06 19:50:10,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.515951595159516) internal successors, (1378), 908 states have internal predecessors, (1378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1378 transitions. [2025-02-06 19:50:10,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-02-06 19:50:10,096 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:10,098 INFO L432 stractBuchiCegarLoop]: Abstraction has 909 states and 1378 transitions. [2025-02-06 19:50:10,098 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:50:10,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1378 transitions. [2025-02-06 19:50:10,101 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-02-06 19:50:10,101 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,101 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,104 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,104 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,104 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,105 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume !(0 == ~comp_m1_st~0);" [2025-02-06 19:50:10,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,105 INFO L85 PathProgramCache]: Analyzing trace with hash 432230803, now seen corresponding path program 1 times [2025-02-06 19:50:10,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [620201539] [2025-02-06 19:50:10,105 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,105 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,114 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,114 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,114 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [620201539] [2025-02-06 19:50:10,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [620201539] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1703320043] [2025-02-06 19:50:10,150 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,150 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,150 INFO L85 PathProgramCache]: Analyzing trace with hash 292527795, now seen corresponding path program 1 times [2025-02-06 19:50:10,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [45650325] [2025-02-06 19:50:10,150 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,152 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-06 19:50:10,155 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-06 19:50:10,155 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,204 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,204 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [45650325] [2025-02-06 19:50:10,204 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [45650325] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,204 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,205 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:10,205 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1218709997] [2025-02-06 19:50:10,205 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,205 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:10,205 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,205 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:10,205 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:10,205 INFO L87 Difference]: Start difference. First operand 909 states and 1378 transitions. cyclomatic complexity: 478 Second operand has 5 states, 5 states have (on average 1.4) internal successors, (7), 5 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,252 INFO L93 Difference]: Finished difference Result 927 states and 1387 transitions. [2025-02-06 19:50:10,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 927 states and 1387 transitions. [2025-02-06 19:50:10,256 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 384 [2025-02-06 19:50:10,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 927 states to 927 states and 1387 transitions. [2025-02-06 19:50:10,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 434 [2025-02-06 19:50:10,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 434 [2025-02-06 19:50:10,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 927 states and 1387 transitions. [2025-02-06 19:50:10,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,263 INFO L218 hiAutomatonCegarLoop]: Abstraction has 927 states and 1387 transitions. [2025-02-06 19:50:10,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 927 states and 1387 transitions. [2025-02-06 19:50:10,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 927 to 909. [2025-02-06 19:50:10,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 909 states, 909 states have (on average 1.506050605060506) internal successors, (1369), 908 states have internal predecessors, (1369), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 909 states to 909 states and 1369 transitions. [2025-02-06 19:50:10,276 INFO L240 hiAutomatonCegarLoop]: Abstraction has 909 states and 1369 transitions. [2025-02-06 19:50:10,276 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:10,277 INFO L432 stractBuchiCegarLoop]: Abstraction has 909 states and 1369 transitions. [2025-02-06 19:50:10,277 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:50:10,277 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 909 states and 1369 transitions. [2025-02-06 19:50:10,281 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 376 [2025-02-06 19:50:10,281 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,281 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,281 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,281 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,281 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume !(0 == ~comp_m1_st~0);" [2025-02-06 19:50:10,281 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,281 INFO L85 PathProgramCache]: Analyzing trace with hash 432230803, now seen corresponding path program 2 times [2025-02-06 19:50:10,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [241287301] [2025-02-06 19:50:10,282 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:10,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,287 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,293 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,293 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:10,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,320 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [241287301] [2025-02-06 19:50:10,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [241287301] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,321 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [450190218] [2025-02-06 19:50:10,321 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,321 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,321 INFO L85 PathProgramCache]: Analyzing trace with hash 290680753, now seen corresponding path program 1 times [2025-02-06 19:50:10,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762396273] [2025-02-06 19:50:10,321 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,323 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-06 19:50:10,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-06 19:50:10,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,330 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,330 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762396273] [2025-02-06 19:50:10,330 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762396273] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,330 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,330 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:10,330 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872680940] [2025-02-06 19:50:10,330 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,330 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:10,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,330 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,330 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,330 INFO L87 Difference]: Start difference. First operand 909 states and 1369 transitions. cyclomatic complexity: 469 Second operand has 3 states, 2 states have (on average 3.5) internal successors, (7), 3 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,357 INFO L93 Difference]: Finished difference Result 1111 states and 1643 transitions. [2025-02-06 19:50:10,357 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1111 states and 1643 transitions. [2025-02-06 19:50:10,362 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-02-06 19:50:10,367 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1111 states to 1111 states and 1643 transitions. [2025-02-06 19:50:10,367 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 526 [2025-02-06 19:50:10,367 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 526 [2025-02-06 19:50:10,367 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1111 states and 1643 transitions. [2025-02-06 19:50:10,367 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-02-06 19:50:10,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1111 states and 1643 transitions. [2025-02-06 19:50:10,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1111 to 1111. [2025-02-06 19:50:10,381 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1111 states, 1111 states have (on average 1.478847884788479) internal successors, (1643), 1110 states have internal predecessors, (1643), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1111 states to 1111 states and 1643 transitions. [2025-02-06 19:50:10,385 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-02-06 19:50:10,385 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:10,386 INFO L432 stractBuchiCegarLoop]: Abstraction has 1111 states and 1643 transitions. [2025-02-06 19:50:10,386 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:50:10,386 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1111 states and 1643 transitions. [2025-02-06 19:50:10,390 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-02-06 19:50:10,390 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,390 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,391 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,391 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,391 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,392 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:10,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,392 INFO L85 PathProgramCache]: Analyzing trace with hash 220879890, now seen corresponding path program 1 times [2025-02-06 19:50:10,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1355264534] [2025-02-06 19:50:10,392 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,399 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,401 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,401 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,401 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,454 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,454 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,454 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1355264534] [2025-02-06 19:50:10,454 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1355264534] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,454 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:10,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [880402463] [2025-02-06 19:50:10,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,458 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,459 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,459 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 1 times [2025-02-06 19:50:10,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1206051042] [2025-02-06 19:50:10,459 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,461 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,461 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,461 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:10,462 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,464 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,464 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,464 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,465 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:10,503 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,504 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:10,504 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:10,504 INFO L87 Difference]: Start difference. First operand 1111 states and 1643 transitions. cyclomatic complexity: 541 Second operand has 4 states, 4 states have (on average 10.5) internal successors, (42), 4 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,555 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:10,563 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,567 INFO L93 Difference]: Finished difference Result 1097 states and 1619 transitions. [2025-02-06 19:50:10,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1097 states and 1619 transitions. [2025-02-06 19:50:10,572 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-02-06 19:50:10,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1097 states to 1097 states and 1619 transitions. [2025-02-06 19:50:10,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2025-02-06 19:50:10,583 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2025-02-06 19:50:10,583 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1097 states and 1619 transitions. [2025-02-06 19:50:10,583 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,583 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-02-06 19:50:10,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1097 states and 1619 transitions. [2025-02-06 19:50:10,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1097 to 1097. [2025-02-06 19:50:10,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1097 states, 1097 states have (on average 1.4758432087511395) internal successors, (1619), 1096 states have internal predecessors, (1619), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1097 states to 1097 states and 1619 transitions. [2025-02-06 19:50:10,606 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-02-06 19:50:10,606 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:10,606 INFO L432 stractBuchiCegarLoop]: Abstraction has 1097 states and 1619 transitions. [2025-02-06 19:50:10,606 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 19:50:10,607 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1097 states and 1619 transitions. [2025-02-06 19:50:10,613 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 452 [2025-02-06 19:50:10,613 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,613 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,613 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,613 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,613 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,613 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:10,614 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,617 INFO L85 PathProgramCache]: Analyzing trace with hash 628744308, now seen corresponding path program 1 times [2025-02-06 19:50:10,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941366000] [2025-02-06 19:50:10,618 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,618 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,621 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,622 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,625 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,625 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941366000] [2025-02-06 19:50:10,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941366000] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128408234] [2025-02-06 19:50:10,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,646 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,646 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,646 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 2 times [2025-02-06 19:50:10,646 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894402153] [2025-02-06 19:50:10,646 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:10,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,647 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,648 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,648 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:10,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,648 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:10,648 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,649 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,649 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,649 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:10,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,676 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,676 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,676 INFO L87 Difference]: Start difference. First operand 1097 states and 1619 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,700 INFO L93 Difference]: Finished difference Result 1394 states and 2020 transitions. [2025-02-06 19:50:10,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1394 states and 2020 transitions. [2025-02-06 19:50:10,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2025-02-06 19:50:10,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1394 states to 1394 states and 2020 transitions. [2025-02-06 19:50:10,711 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 644 [2025-02-06 19:50:10,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 644 [2025-02-06 19:50:10,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1394 states and 2020 transitions. [2025-02-06 19:50:10,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-02-06 19:50:10,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1394 states and 2020 transitions. [2025-02-06 19:50:10,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1394 to 1394. [2025-02-06 19:50:10,725 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1394 states, 1394 states have (on average 1.449067431850789) internal successors, (2020), 1393 states have internal predecessors, (2020), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1394 states to 1394 states and 2020 transitions. [2025-02-06 19:50:10,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-02-06 19:50:10,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:10,729 INFO L432 stractBuchiCegarLoop]: Abstraction has 1394 states and 2020 transitions. [2025-02-06 19:50:10,729 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 19:50:10,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1394 states and 2020 transitions. [2025-02-06 19:50:10,734 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 584 [2025-02-06 19:50:10,734 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,734 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,734 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,734 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,735 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume !(0 == ~d0_ev~0);" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,735 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:10,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,735 INFO L85 PathProgramCache]: Analyzing trace with hash 1625816661, now seen corresponding path program 1 times [2025-02-06 19:50:10,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589010105] [2025-02-06 19:50:10,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,739 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,740 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,740 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,757 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,757 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589010105] [2025-02-06 19:50:10,757 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589010105] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,757 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,757 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,757 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2093177520] [2025-02-06 19:50:10,757 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,757 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,757 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,757 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 3 times [2025-02-06 19:50:10,757 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,757 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [216519188] [2025-02-06 19:50:10,757 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:10,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,759 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,760 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,760 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:10,760 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,760 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:10,760 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,762 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,762 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,762 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:10,787 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,788 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,788 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,788 INFO L87 Difference]: Start difference. First operand 1394 states and 2020 transitions. cyclomatic complexity: 635 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,808 INFO L93 Difference]: Finished difference Result 1547 states and 2225 transitions. [2025-02-06 19:50:10,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1547 states and 2225 transitions. [2025-02-06 19:50:10,814 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2025-02-06 19:50:10,819 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1547 states to 1547 states and 2225 transitions. [2025-02-06 19:50:10,820 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 746 [2025-02-06 19:50:10,820 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 746 [2025-02-06 19:50:10,820 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1547 states and 2225 transitions. [2025-02-06 19:50:10,820 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,820 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-02-06 19:50:10,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1547 states and 2225 transitions. [2025-02-06 19:50:10,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1547 to 1547. [2025-02-06 19:50:10,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1547 states, 1547 states have (on average 1.438267614738203) internal successors, (2225), 1546 states have internal predecessors, (2225), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1547 states to 1547 states and 2225 transitions. [2025-02-06 19:50:10,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-02-06 19:50:10,838 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:10,838 INFO L432 stractBuchiCegarLoop]: Abstraction has 1547 states and 2225 transitions. [2025-02-06 19:50:10,838 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-06 19:50:10,838 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1547 states and 2225 transitions. [2025-02-06 19:50:10,843 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 686 [2025-02-06 19:50:10,843 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,843 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,843 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,843 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,843 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume !(0 == ~d1_ev~0);" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,844 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:10,844 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,844 INFO L85 PathProgramCache]: Analyzing trace with hash 272506964, now seen corresponding path program 1 times [2025-02-06 19:50:10,844 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,844 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [508101255] [2025-02-06 19:50:10,844 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,844 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,850 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,850 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,861 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [508101255] [2025-02-06 19:50:10,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [508101255] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9383137] [2025-02-06 19:50:10,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,861 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,862 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 4 times [2025-02-06 19:50:10,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [753243482] [2025-02-06 19:50:10,862 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:50:10,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,863 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 8 statements into 2 equivalence classes. [2025-02-06 19:50:10,864 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,864 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:50:10,864 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,864 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:10,864 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,865 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,865 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,865 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,866 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:10,884 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,885 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,885 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,885 INFO L87 Difference]: Start difference. First operand 1547 states and 2225 transitions. cyclomatic complexity: 687 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:10,907 INFO L93 Difference]: Finished difference Result 1691 states and 2415 transitions. [2025-02-06 19:50:10,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1691 states and 2415 transitions. [2025-02-06 19:50:10,915 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2025-02-06 19:50:10,921 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1691 states to 1691 states and 2415 transitions. [2025-02-06 19:50:10,921 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 853 [2025-02-06 19:50:10,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 853 [2025-02-06 19:50:10,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1691 states and 2415 transitions. [2025-02-06 19:50:10,922 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:10,922 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-02-06 19:50:10,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1691 states and 2415 transitions. [2025-02-06 19:50:10,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1691 to 1691. [2025-02-06 19:50:10,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1691 states, 1691 states have (on average 1.4281490242460082) internal successors, (2415), 1690 states have internal predecessors, (2415), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:10,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1691 states to 1691 states and 2415 transitions. [2025-02-06 19:50:10,940 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-02-06 19:50:10,940 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:10,941 INFO L432 stractBuchiCegarLoop]: Abstraction has 1691 states and 2415 transitions. [2025-02-06 19:50:10,941 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-06 19:50:10,941 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1691 states and 2415 transitions. [2025-02-06 19:50:10,945 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 793 [2025-02-06 19:50:10,945 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:10,945 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:10,945 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,945 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:10,946 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:10,946 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:10,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,947 INFO L85 PathProgramCache]: Analyzing trace with hash 783041141, now seen corresponding path program 1 times [2025-02-06 19:50:10,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [566111990] [2025-02-06 19:50:10,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:10,947 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,950 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:10,952 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:10,952 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,952 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:10,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:10,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:10,961 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [566111990] [2025-02-06 19:50:10,961 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [566111990] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:10,961 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:10,961 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:10,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113108681] [2025-02-06 19:50:10,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:10,961 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:10,962 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:10,962 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 5 times [2025-02-06 19:50:10,962 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:10,962 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501212939] [2025-02-06 19:50:10,962 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:50:10,962 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:10,963 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,964 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,964 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:10,964 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,964 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:10,964 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:10,967 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:10,967 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:10,967 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:10,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:10,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:10,992 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:10,992 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:10,993 INFO L87 Difference]: Start difference. First operand 1691 states and 2415 transitions. cyclomatic complexity: 733 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:11,015 INFO L93 Difference]: Finished difference Result 1846 states and 2629 transitions. [2025-02-06 19:50:11,015 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1846 states and 2629 transitions. [2025-02-06 19:50:11,021 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 866 [2025-02-06 19:50:11,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1846 states to 1846 states and 2629 transitions. [2025-02-06 19:50:11,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 924 [2025-02-06 19:50:11,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 924 [2025-02-06 19:50:11,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1846 states and 2629 transitions. [2025-02-06 19:50:11,028 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:11,028 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-02-06 19:50:11,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1846 states and 2629 transitions. [2025-02-06 19:50:11,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1846 to 1846. [2025-02-06 19:50:11,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1846 states, 1846 states have (on average 1.424160346695558) internal successors, (2629), 1845 states have internal predecessors, (2629), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1846 states to 1846 states and 2629 transitions. [2025-02-06 19:50:11,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-02-06 19:50:11,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:11,052 INFO L432 stractBuchiCegarLoop]: Abstraction has 1846 states and 2629 transitions. [2025-02-06 19:50:11,052 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-06 19:50:11,052 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1846 states and 2629 transitions. [2025-02-06 19:50:11,056 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 866 [2025-02-06 19:50:11,056 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:11,056 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:11,057 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,057 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,057 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:11,057 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:11,057 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,057 INFO L85 PathProgramCache]: Analyzing trace with hash -959769194, now seen corresponding path program 1 times [2025-02-06 19:50:11,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,057 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [122816177] [2025-02-06 19:50:11,057 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:11,057 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,061 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:11,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:11,062 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,062 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:11,071 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:11,072 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:11,072 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [122816177] [2025-02-06 19:50:11,072 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [122816177] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:11,072 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:11,072 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:11,072 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [562885515] [2025-02-06 19:50:11,072 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:11,072 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:11,072 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,072 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 6 times [2025-02-06 19:50:11,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819277813] [2025-02-06 19:50:11,072 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:50:11,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,074 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,074 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,074 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:50:11,074 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,074 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,075 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,075 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,075 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,075 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,076 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:11,098 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:11,098 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:11,098 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:11,098 INFO L87 Difference]: Start difference. First operand 1846 states and 2629 transitions. cyclomatic complexity: 792 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:11,120 INFO L93 Difference]: Finished difference Result 2125 states and 3031 transitions. [2025-02-06 19:50:11,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2125 states and 3031 transitions. [2025-02-06 19:50:11,126 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 988 [2025-02-06 19:50:11,133 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2125 states to 2125 states and 3031 transitions. [2025-02-06 19:50:11,133 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1048 [2025-02-06 19:50:11,134 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1048 [2025-02-06 19:50:11,134 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2125 states and 3031 transitions. [2025-02-06 19:50:11,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:11,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-02-06 19:50:11,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2125 states and 3031 transitions. [2025-02-06 19:50:11,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2125 to 2125. [2025-02-06 19:50:11,154 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2125 states, 2125 states have (on average 1.4263529411764706) internal successors, (3031), 2124 states have internal predecessors, (3031), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,158 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2125 states to 2125 states and 3031 transitions. [2025-02-06 19:50:11,158 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-02-06 19:50:11,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:11,158 INFO L432 stractBuchiCegarLoop]: Abstraction has 2125 states and 3031 transitions. [2025-02-06 19:50:11,158 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-06 19:50:11,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2125 states and 3031 transitions. [2025-02-06 19:50:11,162 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 988 [2025-02-06 19:50:11,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:11,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:11,162 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,162 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,163 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume !(1 == ~d0_ev~0);" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:11,163 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:11,163 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,163 INFO L85 PathProgramCache]: Analyzing trace with hash -1847272875, now seen corresponding path program 1 times [2025-02-06 19:50:11,163 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,163 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [538135822] [2025-02-06 19:50:11,163 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:11,163 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,166 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:11,167 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:11,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:11,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:11,186 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:11,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [538135822] [2025-02-06 19:50:11,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [538135822] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:11,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:11,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:11,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336220012] [2025-02-06 19:50:11,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:11,186 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:11,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,187 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 7 times [2025-02-06 19:50:11,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [101091693] [2025-02-06 19:50:11,187 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:50:11,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,188 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,189 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,189 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,189 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,189 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,189 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,190 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,190 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,191 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:11,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:11,203 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:11,203 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:11,203 INFO L87 Difference]: Start difference. First operand 2125 states and 3031 transitions. cyclomatic complexity: 915 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:11,229 INFO L93 Difference]: Finished difference Result 2598 states and 3693 transitions. [2025-02-06 19:50:11,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2598 states and 3693 transitions. [2025-02-06 19:50:11,252 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1098 [2025-02-06 19:50:11,259 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2598 states to 2447 states and 3458 transitions. [2025-02-06 19:50:11,259 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1162 [2025-02-06 19:50:11,260 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1162 [2025-02-06 19:50:11,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2447 states and 3458 transitions. [2025-02-06 19:50:11,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:11,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-02-06 19:50:11,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2447 states and 3458 transitions. [2025-02-06 19:50:11,279 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2447 to 2447. [2025-02-06 19:50:11,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2447 states, 2447 states have (on average 1.4131589701675522) internal successors, (3458), 2446 states have internal predecessors, (3458), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,285 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2447 states to 2447 states and 3458 transitions. [2025-02-06 19:50:11,285 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-02-06 19:50:11,285 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:11,286 INFO L432 stractBuchiCegarLoop]: Abstraction has 2447 states and 3458 transitions. [2025-02-06 19:50:11,286 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-06 19:50:11,286 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2447 states and 3458 transitions. [2025-02-06 19:50:11,290 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1098 [2025-02-06 19:50:11,290 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:11,290 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:11,291 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,291 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,291 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume !(1 == ~d1_ev~0);" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:11,291 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:11,291 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,291 INFO L85 PathProgramCache]: Analyzing trace with hash -1875902026, now seen corresponding path program 1 times [2025-02-06 19:50:11,291 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,291 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913996399] [2025-02-06 19:50:11,291 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:11,291 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,294 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:11,296 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:11,296 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:11,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:11,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:11,306 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913996399] [2025-02-06 19:50:11,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913996399] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:11,306 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:11,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:11,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1220585541] [2025-02-06 19:50:11,306 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:11,306 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:11,306 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,306 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 8 times [2025-02-06 19:50:11,306 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,306 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1294049471] [2025-02-06 19:50:11,306 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:11,306 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,308 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,308 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,308 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:11,308 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,308 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,309 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,309 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,309 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,309 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,310 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:11,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:11,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:11,329 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:11,329 INFO L87 Difference]: Start difference. First operand 2447 states and 3458 transitions. cyclomatic complexity: 1020 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,358 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:11,358 INFO L93 Difference]: Finished difference Result 3167 states and 4405 transitions. [2025-02-06 19:50:11,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3167 states and 4405 transitions. [2025-02-06 19:50:11,365 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1251 [2025-02-06 19:50:11,373 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3167 states to 2931 states and 4063 transitions. [2025-02-06 19:50:11,373 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1307 [2025-02-06 19:50:11,374 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1307 [2025-02-06 19:50:11,374 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2931 states and 4063 transitions. [2025-02-06 19:50:11,374 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:11,374 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-02-06 19:50:11,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2931 states and 4063 transitions. [2025-02-06 19:50:11,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2931 to 2931. [2025-02-06 19:50:11,399 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2931 states, 2931 states have (on average 1.386216308427158) internal successors, (4063), 2930 states have internal predecessors, (4063), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:11,404 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2931 states to 2931 states and 4063 transitions. [2025-02-06 19:50:11,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-02-06 19:50:11,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:11,405 INFO L432 stractBuchiCegarLoop]: Abstraction has 2931 states and 4063 transitions. [2025-02-06 19:50:11,405 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-06 19:50:11,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2931 states and 4063 transitions. [2025-02-06 19:50:11,410 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1251 [2025-02-06 19:50:11,410 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:11,410 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:11,410 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,410 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:11,410 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-02-06 19:50:11,410 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-02-06 19:50:11,412 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,412 INFO L85 PathProgramCache]: Analyzing trace with hash -1876825547, now seen corresponding path program 1 times [2025-02-06 19:50:11,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297216259] [2025-02-06 19:50:11,412 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:11,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,415 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:11,416 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:11,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,416 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:11,419 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:11,419 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,419 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,423 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:11,423 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,423 INFO L85 PathProgramCache]: Analyzing trace with hash 421168858, now seen corresponding path program 9 times [2025-02-06 19:50:11,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090159768] [2025-02-06 19:50:11,424 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:11,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,425 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,426 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,426 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:11,426 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,426 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,426 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:11,426 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:11,427 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,427 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,427 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:11,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:11,428 INFO L85 PathProgramCache]: Analyzing trace with hash -1550254834, now seen corresponding path program 1 times [2025-02-06 19:50:11,428 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:11,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071093326] [2025-02-06 19:50:11,428 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:11,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:11,431 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-02-06 19:50:11,432 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-02-06 19:50:11,432 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,432 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,432 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:11,433 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-02-06 19:50:11,435 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-02-06 19:50:11,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:11,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:11,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:12,215 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:12,219 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:12,220 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:12,220 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:12,220 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:12,227 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:12,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:12,234 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:12,234 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:12,327 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:50:12 BoogieIcfgContainer [2025-02-06 19:50:12,327 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:50:12,327 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:50:12,330 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:50:12,330 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:50:12,331 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:05" (3/4) ... [2025-02-06 19:50:12,332 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:50:12,393 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:50:12,393 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:50:12,394 INFO L158 Benchmark]: Toolchain (without parser) took 7408.22ms. Allocated memory was 142.6MB in the beginning and 293.6MB in the end (delta: 151.0MB). Free memory was 107.1MB in the beginning and 161.0MB in the end (delta: -54.0MB). Peak memory consumption was 95.9MB. Max. memory is 16.1GB. [2025-02-06 19:50:12,394 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 116.1MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:12,394 INFO L158 Benchmark]: CACSL2BoogieTranslator took 188.46ms. Allocated memory is still 142.6MB. Free memory was 107.1MB in the beginning and 94.4MB in the end (delta: 12.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-02-06 19:50:12,394 INFO L158 Benchmark]: Boogie Procedure Inliner took 33.38ms. Allocated memory is still 142.6MB. Free memory was 94.4MB in the beginning and 92.0MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:12,394 INFO L158 Benchmark]: Boogie Preprocessor took 25.28ms. Allocated memory is still 142.6MB. Free memory was 92.0MB in the beginning and 90.6MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:12,395 INFO L158 Benchmark]: IcfgBuilder took 379.70ms. Allocated memory is still 142.6MB. Free memory was 90.6MB in the beginning and 66.3MB in the end (delta: 24.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-02-06 19:50:12,395 INFO L158 Benchmark]: BuchiAutomizer took 6711.40ms. Allocated memory was 142.6MB in the beginning and 293.6MB in the end (delta: 151.0MB). Free memory was 66.3MB in the beginning and 169.4MB in the end (delta: -103.2MB). Peak memory consumption was 45.5MB. Max. memory is 16.1GB. [2025-02-06 19:50:12,395 INFO L158 Benchmark]: Witness Printer took 66.11ms. Allocated memory is still 293.6MB. Free memory was 169.4MB in the beginning and 161.0MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:12,396 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 116.1MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 188.46ms. Allocated memory is still 142.6MB. Free memory was 107.1MB in the beginning and 94.4MB in the end (delta: 12.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 33.38ms. Allocated memory is still 142.6MB. Free memory was 94.4MB in the beginning and 92.0MB in the end (delta: 2.3MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 25.28ms. Allocated memory is still 142.6MB. Free memory was 92.0MB in the beginning and 90.6MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 379.70ms. Allocated memory is still 142.6MB. Free memory was 90.6MB in the beginning and 66.3MB in the end (delta: 24.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 6711.40ms. Allocated memory was 142.6MB in the beginning and 293.6MB in the end (delta: 151.0MB). Free memory was 66.3MB in the beginning and 169.4MB in the end (delta: -103.2MB). Peak memory consumption was 45.5MB. Max. memory is 16.1GB. * Witness Printer took 66.11ms. Allocated memory is still 293.6MB. Free memory was 169.4MB in the beginning and 161.0MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 22 terminating modules (20 trivial, 2 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. One deterministic module has affine ranking function (((long long) -1 * d0_ev) + 1) and consists of 3 locations. 20 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 2931 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 6.6s and 21 iterations. TraceHistogramMax:1. Analysis of lassos took 4.4s. Construction of modules took 0.3s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 3. Minimization of det autom 8. Minimization of nondet autom 14. Automata minimization 0.4s AutomataMinimizationTime, 22 MinimizatonAttempts, 28 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 797 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 795 mSDsluCounter, 8503 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 4629 mSDsCounter, 57 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 303 IncrementalHoareTripleChecker+Invalid, 360 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 57 mSolverCounterUnsat, 3874 mSDtfsCounter, 303 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN8 SILU0 SILI10 SILT2 lasso0 LassoPreprocessingBenchmarks: Lassos: inital60 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq184 hnf97 smp100 dnf152 smp86 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 23ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 2 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.1s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 285]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 285]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L432] COND TRUE 1 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L285] COND TRUE 1 [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:50:12,419 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)