./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu1.cil.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version c00e63dc
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu1.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-c00e63d-m
[2025-02-06 19:50:11,105 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-02-06 19:50:11,181 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-02-06 19:50:11,187 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-02-06 19:50:11,188 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-02-06 19:50:11,188 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG
[2025-02-06 19:50:11,216 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-02-06 19:50:11,218 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-02-06 19:50:11,218 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-02-06 19:50:11,219 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-02-06 19:50:11,219 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-02-06 19:50:11,220 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-02-06 19:50:11,220 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-02-06 19:50:11,220 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-02-06 19:50:11,220 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-02-06 19:50:11,221 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-02-06 19:50:11,221 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-02-06 19:50:11,222 INFO  L151        SettingsManager]: Preferences of IcfgBuilder differ from their defaults:
[2025-02-06 19:50:11,222 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-02-06 19:50:11,223 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-02-06 19:50:11,223 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-02-06 19:50:11,223 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-02-06 19:50:11,223 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c114a15ea6b1c9b012290758a6a9559b9c02a944706c9768958a3bd9c86822a7
[2025-02-06 19:50:11,489 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-02-06 19:50:11,497 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-02-06 19:50:11,500 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-02-06 19:50:11,501 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-02-06 19:50:11,502 INFO  L274        PluginConnector]: CDTParser initialized
[2025-02-06 19:50:11,503 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu1.cil.c
[2025-02-06 19:50:12,791 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2ab0b2476/874106e2ebaf4037a2443a8a7e27bf84/FLAG0f979c705
[2025-02-06 19:50:13,024 INFO  L384              CDTParser]: Found 1 translation units.
[2025-02-06 19:50:13,025 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/kundu1.cil.c
[2025-02-06 19:50:13,053 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2ab0b2476/874106e2ebaf4037a2443a8a7e27bf84/FLAG0f979c705
[2025-02-06 19:50:13,071 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2ab0b2476/874106e2ebaf4037a2443a8a7e27bf84
[2025-02-06 19:50:13,074 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-02-06 19:50:13,075 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-02-06 19:50:13,076 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-02-06 19:50:13,077 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-02-06 19:50:13,080 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-02-06 19:50:13,081 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,082 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@acf3473 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13, skipping insertion in model container
[2025-02-06 19:50:13,082 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,108 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-02-06 19:50:13,296 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-02-06 19:50:13,310 INFO  L200         MainTranslator]: Completed pre-run
[2025-02-06 19:50:13,347 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-02-06 19:50:13,366 INFO  L204         MainTranslator]: Completed translation
[2025-02-06 19:50:13,367 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13 WrapperNode
[2025-02-06 19:50:13,367 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-02-06 19:50:13,368 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-02-06 19:50:13,368 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-02-06 19:50:13,368 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-02-06 19:50:13,373 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,380 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,410 INFO  L138                Inliner]: procedures = 32, calls = 37, calls flagged for inlining = 32, calls inlined = 37, statements flattened = 363
[2025-02-06 19:50:13,413 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-02-06 19:50:13,414 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-02-06 19:50:13,414 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-02-06 19:50:13,414 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-02-06 19:50:13,421 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,421 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,423 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,446 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-02-06 19:50:13,446 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,446 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,454 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,459 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,460 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,461 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,467 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-02-06 19:50:13,467 INFO  L112        PluginConnector]: ------------------------IcfgBuilder----------------------------
[2025-02-06 19:50:13,467 INFO  L270        PluginConnector]: Initializing IcfgBuilder...
[2025-02-06 19:50:13,468 INFO  L274        PluginConnector]: IcfgBuilder initialized
[2025-02-06 19:50:13,470 INFO  L184        PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (1/1) ...
[2025-02-06 19:50:13,475 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-02-06 19:50:13,491 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3
[2025-02-06 19:50:13,505 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-02-06 19:50:13,510 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-02-06 19:50:13,533 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-02-06 19:50:13,533 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-02-06 19:50:13,533 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-02-06 19:50:13,533 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-02-06 19:50:13,614 INFO  L257             CfgBuilder]: Building ICFG
[2025-02-06 19:50:13,616 INFO  L287             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-02-06 19:50:14,013 INFO  L?                        ?]: Removed 68 outVars from TransFormulas that were not future-live.
[2025-02-06 19:50:14,014 INFO  L308             CfgBuilder]: Performing block encoding
[2025-02-06 19:50:14,028 INFO  L332             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-02-06 19:50:14,028 INFO  L337             CfgBuilder]: Removed 0 assume(true) statements.
[2025-02-06 19:50:14,029 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:14 BoogieIcfgContainer
[2025-02-06 19:50:14,029 INFO  L131        PluginConnector]: ------------------------ END IcfgBuilder----------------------------
[2025-02-06 19:50:14,030 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-02-06 19:50:14,030 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-02-06 19:50:14,037 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-02-06 19:50:14,037 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:50:14,038 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:13" (1/3) ...
[2025-02-06 19:50:14,040 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72d7b2ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:14, skipping insertion in model container
[2025-02-06 19:50:14,040 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:50:14,041 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:13" (2/3) ...
[2025-02-06 19:50:14,041 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@72d7b2ea and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:14, skipping insertion in model container
[2025-02-06 19:50:14,041 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:50:14,041 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:14" (3/3) ...
[2025-02-06 19:50:14,044 INFO  L363   chiAutomizerObserver]: Analyzing ICFG kundu1.cil.c
[2025-02-06 19:50:14,097 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-02-06 19:50:14,098 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-02-06 19:50:14,098 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-02-06 19:50:14,098 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-02-06 19:50:14,098 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-02-06 19:50:14,099 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-02-06 19:50:14,099 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-02-06 19:50:14,099 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-02-06 19:50:14,105 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 133 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 132 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,132 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 103
[2025-02-06 19:50:14,132 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:14,132 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:14,140 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,140 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,141 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-02-06 19:50:14,141 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 133 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 132 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,146 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 103
[2025-02-06 19:50:14,146 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:14,146 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:14,147 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,147 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,155 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:14,156 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:14,161 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,161 INFO  L85        PathProgramCache]: Analyzing trace with hash 47334983, now seen corresponding path program 1 times
[2025-02-06 19:50:14,169 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,170 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054913390]
[2025-02-06 19:50:14,170 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:14,171 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,238 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-02-06 19:50:14,252 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-02-06 19:50:14,253 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:14,253 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,353 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,353 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,353 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054913390]
[2025-02-06 19:50:14,354 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054913390] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,354 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,354 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:50:14,356 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044256618]
[2025-02-06 19:50:14,356 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,359 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-02-06 19:50:14,361 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,361 INFO  L85        PathProgramCache]: Analyzing trace with hash 853613033, now seen corresponding path program 1 times
[2025-02-06 19:50:14,361 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,361 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [299585975]
[2025-02-06 19:50:14,361 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:14,361 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,375 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes.
[2025-02-06 19:50:14,376 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements.
[2025-02-06 19:50:14,376 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:14,376 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,395 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,399 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,399 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [299585975]
[2025-02-06 19:50:14,399 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [299585975] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,399 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,399 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-02-06 19:50:14,399 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1911453036]
[2025-02-06 19:50:14,399 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,400 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:14,402 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:14,428 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:14,428 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:14,430 INFO  L87              Difference]: Start difference. First operand  has 133 states, 131 states have (on average 1.4351145038167938) internal successors, (188), 132 states have internal predecessors, (188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,449 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:14,450 INFO  L93              Difference]: Finished difference Result 127 states and 176 transitions.
[2025-02-06 19:50:14,452 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 127 states and 176 transitions.
[2025-02-06 19:50:14,454 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 94
[2025-02-06 19:50:14,461 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 127 states to 119 states and 168 transitions.
[2025-02-06 19:50:14,462 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 119
[2025-02-06 19:50:14,463 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 119
[2025-02-06 19:50:14,463 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 119 states and 168 transitions.
[2025-02-06 19:50:14,464 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:14,464 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 119 states and 168 transitions.
[2025-02-06 19:50:14,476 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 119 states and 168 transitions.
[2025-02-06 19:50:14,493 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119.
[2025-02-06 19:50:14,494 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 119 states, 119 states have (on average 1.411764705882353) internal successors, (168), 118 states have internal predecessors, (168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,499 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 168 transitions.
[2025-02-06 19:50:14,500 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 119 states and 168 transitions.
[2025-02-06 19:50:14,501 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:14,503 INFO  L432   stractBuchiCegarLoop]: Abstraction has 119 states and 168 transitions.
[2025-02-06 19:50:14,504 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-02-06 19:50:14,504 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 168 transitions.
[2025-02-06 19:50:14,505 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 94
[2025-02-06 19:50:14,505 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:14,505 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:14,506 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,506 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,507 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:14,507 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:14,509 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,509 INFO  L85        PathProgramCache]: Analyzing trace with hash -1305974714, now seen corresponding path program 1 times
[2025-02-06 19:50:14,509 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,509 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1340787827]
[2025-02-06 19:50:14,509 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:14,509 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,515 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-02-06 19:50:14,520 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-02-06 19:50:14,520 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:14,520 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,552 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,552 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,552 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1340787827]
[2025-02-06 19:50:14,552 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1340787827] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,553 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,553 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:50:14,553 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1794013272]
[2025-02-06 19:50:14,553 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,553 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-02-06 19:50:14,553 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,554 INFO  L85        PathProgramCache]: Analyzing trace with hash -880660716, now seen corresponding path program 1 times
[2025-02-06 19:50:14,554 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,554 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [118866644]
[2025-02-06 19:50:14,554 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:14,554 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,564 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes.
[2025-02-06 19:50:14,581 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements.
[2025-02-06 19:50:14,581 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:14,582 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,705 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,705 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,705 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [118866644]
[2025-02-06 19:50:14,705 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [118866644] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,706 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,706 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:14,706 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401199061]
[2025-02-06 19:50:14,706 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,706 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:14,706 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:14,707 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:14,707 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:14,708 INFO  L87              Difference]: Start difference. First operand 119 states and 168 transitions. cyclomatic complexity: 50 Second operand  has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,727 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:14,727 INFO  L93              Difference]: Finished difference Result 119 states and 167 transitions.
[2025-02-06 19:50:14,727 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 119 states and 167 transitions.
[2025-02-06 19:50:14,729 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 94
[2025-02-06 19:50:14,734 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 119 states to 119 states and 167 transitions.
[2025-02-06 19:50:14,734 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 119
[2025-02-06 19:50:14,737 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 119
[2025-02-06 19:50:14,738 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 119 states and 167 transitions.
[2025-02-06 19:50:14,738 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:14,738 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 119 states and 167 transitions.
[2025-02-06 19:50:14,739 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 119 states and 167 transitions.
[2025-02-06 19:50:14,744 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119.
[2025-02-06 19:50:14,745 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 119 states, 119 states have (on average 1.403361344537815) internal successors, (167), 118 states have internal predecessors, (167), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,745 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 167 transitions.
[2025-02-06 19:50:14,746 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 119 states and 167 transitions.
[2025-02-06 19:50:14,746 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:14,747 INFO  L432   stractBuchiCegarLoop]: Abstraction has 119 states and 167 transitions.
[2025-02-06 19:50:14,747 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-02-06 19:50:14,747 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 119 states and 167 transitions.
[2025-02-06 19:50:14,748 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 94
[2025-02-06 19:50:14,748 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:14,748 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:14,749 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,749 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:14,749 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:14,749 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:14,753 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,753 INFO  L85        PathProgramCache]: Analyzing trace with hash -795440537, now seen corresponding path program 1 times
[2025-02-06 19:50:14,753 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,753 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [107226684]
[2025-02-06 19:50:14,753 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:14,754 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,759 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-02-06 19:50:14,768 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-02-06 19:50:14,768 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:14,769 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,833 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,833 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,833 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [107226684]
[2025-02-06 19:50:14,833 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [107226684] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,833 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,833 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:50:14,833 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304435659]
[2025-02-06 19:50:14,833 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,834 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-02-06 19:50:14,834 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:14,834 INFO  L85        PathProgramCache]: Analyzing trace with hash -880660716, now seen corresponding path program 2 times
[2025-02-06 19:50:14,834 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:14,834 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567370551]
[2025-02-06 19:50:14,834 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:50:14,834 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:14,845 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 36 statements into 1 equivalence classes.
[2025-02-06 19:50:14,852 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 36 of 36 statements.
[2025-02-06 19:50:14,852 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:50:14,852 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:14,917 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:14,918 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:14,918 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567370551]
[2025-02-06 19:50:14,918 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567370551] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:14,918 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:14,918 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:14,918 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068730413]
[2025-02-06 19:50:14,918 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:14,919 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:14,919 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:14,919 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:14,919 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:14,919 INFO  L87              Difference]: Start difference. First operand 119 states and 167 transitions. cyclomatic complexity: 49 Second operand  has 3 states, 3 states have (on average 7.0) internal successors, (21), 3 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,973 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:14,973 INFO  L93              Difference]: Finished difference Result 208 states and 288 transitions.
[2025-02-06 19:50:14,973 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 208 states and 288 transitions.
[2025-02-06 19:50:14,975 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 184
[2025-02-06 19:50:14,980 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 208 states to 208 states and 288 transitions.
[2025-02-06 19:50:14,980 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 208
[2025-02-06 19:50:14,980 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 208
[2025-02-06 19:50:14,980 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 208 states and 288 transitions.
[2025-02-06 19:50:14,981 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:14,981 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 208 states and 288 transitions.
[2025-02-06 19:50:14,982 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 208 states and 288 transitions.
[2025-02-06 19:50:14,994 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 204.
[2025-02-06 19:50:14,996 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 204 states, 204 states have (on average 1.3872549019607843) internal successors, (283), 203 states have internal predecessors, (283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:14,997 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 283 transitions.
[2025-02-06 19:50:14,997 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 204 states and 283 transitions.
[2025-02-06 19:50:14,998 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:14,999 INFO  L432   stractBuchiCegarLoop]: Abstraction has 204 states and 283 transitions.
[2025-02-06 19:50:14,999 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-02-06 19:50:14,999 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 204 states and 283 transitions.
[2025-02-06 19:50:15,000 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 180
[2025-02-06 19:50:15,001 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,001 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,003 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,003 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,003 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:15,003 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:15,003 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,004 INFO  L85        PathProgramCache]: Analyzing trace with hash -1347008982, now seen corresponding path program 1 times
[2025-02-06 19:50:15,004 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,004 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688310994]
[2025-02-06 19:50:15,004 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,004 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,013 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes.
[2025-02-06 19:50:15,018 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements.
[2025-02-06 19:50:15,018 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,018 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,059 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,059 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,059 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1688310994]
[2025-02-06 19:50:15,059 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1688310994] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,059 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,059 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4
[2025-02-06 19:50:15,060 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590400742]
[2025-02-06 19:50:15,060 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,060 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-02-06 19:50:15,060 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,060 INFO  L85        PathProgramCache]: Analyzing trace with hash 1471110743, now seen corresponding path program 1 times
[2025-02-06 19:50:15,060 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,060 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1593872066]
[2025-02-06 19:50:15,060 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,060 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,069 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes.
[2025-02-06 19:50:15,072 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements.
[2025-02-06 19:50:15,072 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,072 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,123 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,123 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,123 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1593872066]
[2025-02-06 19:50:15,123 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1593872066] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,123 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,123 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:15,123 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1219944318]
[2025-02-06 19:50:15,124 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,124 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:15,124 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:15,124 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants.
[2025-02-06 19:50:15,124 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12
[2025-02-06 19:50:15,124 INFO  L87              Difference]: Start difference. First operand 204 states and 283 transitions. cyclomatic complexity: 80 Second operand  has 4 states, 4 states have (on average 5.25) internal successors, (21), 4 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,249 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:15,250 INFO  L93              Difference]: Finished difference Result 430 states and 588 transitions.
[2025-02-06 19:50:15,250 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 588 transitions.
[2025-02-06 19:50:15,253 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 402
[2025-02-06 19:50:15,256 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 430 states and 588 transitions.
[2025-02-06 19:50:15,256 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 430
[2025-02-06 19:50:15,256 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 430
[2025-02-06 19:50:15,257 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 430 states and 588 transitions.
[2025-02-06 19:50:15,258 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:15,261 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 430 states and 588 transitions.
[2025-02-06 19:50:15,262 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 430 states and 588 transitions.
[2025-02-06 19:50:15,279 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 349.
[2025-02-06 19:50:15,280 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 349 states, 349 states have (on average 1.3724928366762177) internal successors, (479), 348 states have internal predecessors, (479), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,281 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 349 states to 349 states and 479 transitions.
[2025-02-06 19:50:15,281 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 349 states and 479 transitions.
[2025-02-06 19:50:15,282 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. 
[2025-02-06 19:50:15,282 INFO  L432   stractBuchiCegarLoop]: Abstraction has 349 states and 479 transitions.
[2025-02-06 19:50:15,282 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-02-06 19:50:15,282 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 349 states and 479 transitions.
[2025-02-06 19:50:15,284 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 326
[2025-02-06 19:50:15,284 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,284 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,285 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,285 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,285 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:15,285 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~1#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:15,286 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,286 INFO  L85        PathProgramCache]: Analyzing trace with hash 360461253, now seen corresponding path program 1 times
[2025-02-06 19:50:15,286 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,286 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259009766]
[2025-02-06 19:50:15,286 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,286 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,291 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,294 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,295 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,295 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,318 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,319 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,319 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259009766]
[2025-02-06 19:50:15,320 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259009766] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,320 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,320 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:50:15,320 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2013375793]
[2025-02-06 19:50:15,320 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,320 INFO  L757   eck$LassoCheckResult]: stem already infeasible
[2025-02-06 19:50:15,321 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,321 INFO  L85        PathProgramCache]: Analyzing trace with hash 1324942576, now seen corresponding path program 1 times
[2025-02-06 19:50:15,322 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,322 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772126901]
[2025-02-06 19:50:15,322 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,322 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,330 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes.
[2025-02-06 19:50:15,335 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements.
[2025-02-06 19:50:15,335 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,335 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,376 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,376 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,376 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772126901]
[2025-02-06 19:50:15,376 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772126901] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,376 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,377 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:15,377 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820127232]
[2025-02-06 19:50:15,377 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,377 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:15,378 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:15,378 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:15,379 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:15,379 INFO  L87              Difference]: Start difference. First operand 349 states and 479 transitions. cyclomatic complexity: 131 Second operand  has 3 states, 3 states have (on average 7.333333333333333) internal successors, (22), 3 states have internal predecessors, (22), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,418 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:15,419 INFO  L93              Difference]: Finished difference Result 500 states and 677 transitions.
[2025-02-06 19:50:15,419 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 500 states and 677 transitions.
[2025-02-06 19:50:15,422 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 478
[2025-02-06 19:50:15,425 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 500 states to 500 states and 677 transitions.
[2025-02-06 19:50:15,425 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 500
[2025-02-06 19:50:15,425 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 500
[2025-02-06 19:50:15,425 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 500 states and 677 transitions.
[2025-02-06 19:50:15,427 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:15,427 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 500 states and 677 transitions.
[2025-02-06 19:50:15,428 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 500 states and 677 transitions.
[2025-02-06 19:50:15,438 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 500 to 498.
[2025-02-06 19:50:15,439 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 498 states, 498 states have (on average 1.355421686746988) internal successors, (675), 497 states have internal predecessors, (675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,440 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 498 states to 498 states and 675 transitions.
[2025-02-06 19:50:15,441 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 498 states and 675 transitions.
[2025-02-06 19:50:15,441 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:15,442 INFO  L432   stractBuchiCegarLoop]: Abstraction has 498 states and 675 transitions.
[2025-02-06 19:50:15,442 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-02-06 19:50:15,442 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 498 states and 675 transitions.
[2025-02-06 19:50:15,445 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 476
[2025-02-06 19:50:15,446 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,446 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,447 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,447 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,447 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:15,448 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:15,448 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,448 INFO  L85        PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 1 times
[2025-02-06 19:50:15,448 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,448 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260548745]
[2025-02-06 19:50:15,449 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,449 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,454 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,459 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,459 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,459 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,460 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:15,463 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,466 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,467 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,468 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,489 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:15,490 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,490 INFO  L85        PathProgramCache]: Analyzing trace with hash -1820351885, now seen corresponding path program 1 times
[2025-02-06 19:50:15,490 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,490 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [506775283]
[2025-02-06 19:50:15,490 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,492 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,513 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes.
[2025-02-06 19:50:15,518 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements.
[2025-02-06 19:50:15,519 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,519 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,552 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,553 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,553 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [506775283]
[2025-02-06 19:50:15,553 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [506775283] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,556 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,556 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:15,556 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [271638209]
[2025-02-06 19:50:15,556 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,556 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:15,556 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:15,556 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-02-06 19:50:15,556 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-02-06 19:50:15,557 INFO  L87              Difference]: Start difference. First operand 498 states and 675 transitions. cyclomatic complexity: 178 Second operand  has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,606 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:15,606 INFO  L93              Difference]: Finished difference Result 540 states and 717 transitions.
[2025-02-06 19:50:15,606 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 540 states and 717 transitions.
[2025-02-06 19:50:15,610 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 518
[2025-02-06 19:50:15,613 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 540 states to 540 states and 717 transitions.
[2025-02-06 19:50:15,614 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 540
[2025-02-06 19:50:15,614 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 540
[2025-02-06 19:50:15,614 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 540 states and 717 transitions.
[2025-02-06 19:50:15,615 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:15,615 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 540 states and 717 transitions.
[2025-02-06 19:50:15,616 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 540 states and 717 transitions.
[2025-02-06 19:50:15,621 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 516.
[2025-02-06 19:50:15,622 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 516 states, 516 states have (on average 1.3430232558139534) internal successors, (693), 515 states have internal predecessors, (693), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,624 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 693 transitions.
[2025-02-06 19:50:15,625 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 516 states and 693 transitions.
[2025-02-06 19:50:15,625 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-02-06 19:50:15,627 INFO  L432   stractBuchiCegarLoop]: Abstraction has 516 states and 693 transitions.
[2025-02-06 19:50:15,628 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-02-06 19:50:15,628 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 516 states and 693 transitions.
[2025-02-06 19:50:15,631 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 494
[2025-02-06 19:50:15,631 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,631 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,632 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,632 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,632 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:15,632 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:15,633 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,634 INFO  L85        PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 2 times
[2025-02-06 19:50:15,634 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,634 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591131017]
[2025-02-06 19:50:15,634 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:50:15,634 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,638 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,643 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,644 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:50:15,644 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,644 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:15,650 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,655 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,655 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,655 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,661 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:15,662 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,662 INFO  L85        PathProgramCache]: Analyzing trace with hash 1760204618, now seen corresponding path program 1 times
[2025-02-06 19:50:15,662 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,664 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812808347]
[2025-02-06 19:50:15,664 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,664 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,668 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes.
[2025-02-06 19:50:15,676 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements.
[2025-02-06 19:50:15,677 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,677 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,721 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,721 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,721 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1812808347]
[2025-02-06 19:50:15,721 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1812808347] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,721 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,722 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5
[2025-02-06 19:50:15,722 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777772710]
[2025-02-06 19:50:15,722 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,722 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:15,722 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:15,722 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants.
[2025-02-06 19:50:15,722 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20
[2025-02-06 19:50:15,723 INFO  L87              Difference]: Start difference. First operand 516 states and 693 transitions. cyclomatic complexity: 178 Second operand  has 5 states, 5 states have (on average 7.6) internal successors, (38), 5 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,776 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:15,777 INFO  L93              Difference]: Finished difference Result 534 states and 704 transitions.
[2025-02-06 19:50:15,777 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 534 states and 704 transitions.
[2025-02-06 19:50:15,781 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 512
[2025-02-06 19:50:15,783 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 534 states to 534 states and 704 transitions.
[2025-02-06 19:50:15,784 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 534
[2025-02-06 19:50:15,784 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 534
[2025-02-06 19:50:15,784 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 534 states and 704 transitions.
[2025-02-06 19:50:15,785 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:15,785 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 534 states and 704 transitions.
[2025-02-06 19:50:15,786 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 534 states and 704 transitions.
[2025-02-06 19:50:15,791 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 534.
[2025-02-06 19:50:15,793 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 534 states, 534 states have (on average 1.3183520599250935) internal successors, (704), 533 states have internal predecessors, (704), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,795 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 534 states to 534 states and 704 transitions.
[2025-02-06 19:50:15,795 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 534 states and 704 transitions.
[2025-02-06 19:50:15,795 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. 
[2025-02-06 19:50:15,797 INFO  L432   stractBuchiCegarLoop]: Abstraction has 534 states and 704 transitions.
[2025-02-06 19:50:15,797 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-02-06 19:50:15,797 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 534 states and 704 transitions.
[2025-02-06 19:50:15,800 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 512
[2025-02-06 19:50:15,800 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,800 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,800 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,801 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,802 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" 
[2025-02-06 19:50:15,802 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret11#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret12#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret12#1;havoc start_simulation_#t~ret12#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" 
[2025-02-06 19:50:15,802 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,802 INFO  L85        PathProgramCache]: Analyzing trace with hash 1190706632, now seen corresponding path program 3 times
[2025-02-06 19:50:15,802 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,803 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [308775324]
[2025-02-06 19:50:15,803 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-02-06 19:50:15,803 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,808 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,811 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,811 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-02-06 19:50:15,811 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,811 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:15,813 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes.
[2025-02-06 19:50:15,815 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements.
[2025-02-06 19:50:15,815 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,815 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,819 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:15,820 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,820 INFO  L85        PathProgramCache]: Analyzing trace with hash -277851671, now seen corresponding path program 1 times
[2025-02-06 19:50:15,820 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,820 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1228993725]
[2025-02-06 19:50:15,820 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,820 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,830 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes.
[2025-02-06 19:50:15,833 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements.
[2025-02-06 19:50:15,834 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,834 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,864 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,864 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,864 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1228993725]
[2025-02-06 19:50:15,864 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1228993725] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,864 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,864 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:50:15,864 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2019882093]
[2025-02-06 19:50:15,865 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:15,865 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:50:15,865 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:15,865 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:15,865 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:15,865 INFO  L87              Difference]: Start difference. First operand 534 states and 704 transitions. cyclomatic complexity: 171 Second operand  has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,898 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:15,899 INFO  L93              Difference]: Finished difference Result 774 states and 1001 transitions.
[2025-02-06 19:50:15,899 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 774 states and 1001 transitions.
[2025-02-06 19:50:15,903 INFO  L131   ngComponentsAnalysis]: Automaton has 3 accepting balls. 741
[2025-02-06 19:50:15,907 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 774 states to 774 states and 1001 transitions.
[2025-02-06 19:50:15,907 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 774
[2025-02-06 19:50:15,908 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 774
[2025-02-06 19:50:15,908 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 774 states and 1001 transitions.
[2025-02-06 19:50:15,909 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:15,909 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 774 states and 1001 transitions.
[2025-02-06 19:50:15,910 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 774 states and 1001 transitions.
[2025-02-06 19:50:15,919 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 774 to 774.
[2025-02-06 19:50:15,920 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 774 states, 774 states have (on average 1.29328165374677) internal successors, (1001), 773 states have internal predecessors, (1001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:15,923 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 774 states to 774 states and 1001 transitions.
[2025-02-06 19:50:15,923 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 774 states and 1001 transitions.
[2025-02-06 19:50:15,923 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:15,925 INFO  L432   stractBuchiCegarLoop]: Abstraction has 774 states and 1001 transitions.
[2025-02-06 19:50:15,925 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-02-06 19:50:15,925 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 774 states and 1001 transitions.
[2025-02-06 19:50:15,929 INFO  L131   ngComponentsAnalysis]: Automaton has 3 accepting balls. 741
[2025-02-06 19:50:15,929 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:15,929 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:15,930 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,930 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:15,930 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-02-06 19:50:15,930 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~C_1_st~0);" 
[2025-02-06 19:50:15,931 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,931 INFO  L85        PathProgramCache]: Analyzing trace with hash 1807779335, now seen corresponding path program 1 times
[2025-02-06 19:50:15,931 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,931 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [189493445]
[2025-02-06 19:50:15,931 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,931 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,936 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:15,939 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:15,940 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,940 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,940 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:15,941 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:15,943 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:15,943 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,944 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,950 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:15,950 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,950 INFO  L85        PathProgramCache]: Analyzing trace with hash 502320936, now seen corresponding path program 1 times
[2025-02-06 19:50:15,950 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,950 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [452054127]
[2025-02-06 19:50:15,950 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,950 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,954 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes.
[2025-02-06 19:50:15,955 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements.
[2025-02-06 19:50:15,955 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,955 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,955 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:15,956 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes.
[2025-02-06 19:50:15,957 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements.
[2025-02-06 19:50:15,957 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,957 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:15,959 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:15,960 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:15,960 INFO  L85        PathProgramCache]: Analyzing trace with hash 354398178, now seen corresponding path program 1 times
[2025-02-06 19:50:15,960 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:15,960 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368318944]
[2025-02-06 19:50:15,960 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:15,961 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:15,965 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes.
[2025-02-06 19:50:15,969 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements.
[2025-02-06 19:50:15,969 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:15,969 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:50:15,996 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:50:15,996 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:50:15,996 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [368318944]
[2025-02-06 19:50:15,996 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [368318944] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:50:15,996 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:50:15,996 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2
[2025-02-06 19:50:15,996 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278518194]
[2025-02-06 19:50:15,999 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:50:16,045 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:50:16,045 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:50:16,045 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:50:16,046 INFO  L87              Difference]: Start difference. First operand 774 states and 1001 transitions. cyclomatic complexity: 230 Second operand  has 3 states, 2 states have (on average 16.5) internal successors, (33), 3 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:16,112 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:50:16,112 INFO  L93              Difference]: Finished difference Result 1251 states and 1595 transitions.
[2025-02-06 19:50:16,112 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1251 states and 1595 transitions.
[2025-02-06 19:50:16,119 INFO  L131   ngComponentsAnalysis]: Automaton has 3 accepting balls. 1209
[2025-02-06 19:50:16,126 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1251 states to 1251 states and 1595 transitions.
[2025-02-06 19:50:16,126 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1251
[2025-02-06 19:50:16,127 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1251
[2025-02-06 19:50:16,127 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1251 states and 1595 transitions.
[2025-02-06 19:50:16,129 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:50:16,129 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1251 states and 1595 transitions.
[2025-02-06 19:50:16,130 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1251 states and 1595 transitions.
[2025-02-06 19:50:16,144 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1251 to 1251.
[2025-02-06 19:50:16,146 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1251 states, 1251 states have (on average 1.2749800159872102) internal successors, (1595), 1250 states have internal predecessors, (1595), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:50:16,150 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1251 states to 1251 states and 1595 transitions.
[2025-02-06 19:50:16,150 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1251 states and 1595 transitions.
[2025-02-06 19:50:16,151 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:50:16,152 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1251 states and 1595 transitions.
[2025-02-06 19:50:16,152 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-02-06 19:50:16,152 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1251 states and 1595 transitions.
[2025-02-06 19:50:16,158 INFO  L131   ngComponentsAnalysis]: Automaton has 3 accepting balls. 1209
[2025-02-06 19:50:16,158 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:50:16,158 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:50:16,158 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:16,158 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:50:16,158 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_#t~ret12#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret8#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;havoc is_C_1_triggered_~__retres1~1#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~1#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~1#1;" "activate_threads_#t~ret9#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~1#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret8#1, activate_threads_#t~ret9#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" 
[2025-02-06 19:50:16,158 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet7#1;eval_~tmp___1~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___1~0#1);" 
[2025-02-06 19:50:16,159 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:16,159 INFO  L85        PathProgramCache]: Analyzing trace with hash 1807779335, now seen corresponding path program 2 times
[2025-02-06 19:50:16,159 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:16,159 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084562572]
[2025-02-06 19:50:16,159 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:50:16,160 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:16,166 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:16,169 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:16,169 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:50:16,169 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,169 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:16,171 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:16,173 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:16,173 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,173 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,179 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:16,180 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:16,180 INFO  L85        PathProgramCache]: Analyzing trace with hash -1607920039, now seen corresponding path program 1 times
[2025-02-06 19:50:16,180 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:16,180 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [390102464]
[2025-02-06 19:50:16,180 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:16,180 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:16,185 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-02-06 19:50:16,186 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-02-06 19:50:16,186 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,186 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,186 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:16,187 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes.
[2025-02-06 19:50:16,188 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements.
[2025-02-06 19:50:16,188 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,188 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,190 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:16,190 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:50:16,190 INFO  L85        PathProgramCache]: Analyzing trace with hash -1898558241, now seen corresponding path program 1 times
[2025-02-06 19:50:16,190 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:50:16,190 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874092194]
[2025-02-06 19:50:16,191 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:50:16,191 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:50:16,196 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-02-06 19:50:16,200 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-02-06 19:50:16,200 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,200 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,200 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:16,202 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-02-06 19:50:16,204 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-02-06 19:50:16,205 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,205 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,211 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:50:16,843 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:16,847 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:16,847 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,847 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,847 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:50:16,856 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes.
[2025-02-06 19:50:16,859 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements.
[2025-02-06 19:50:16,860 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:50:16,860 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:50:16,941 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:50:16 BoogieIcfgContainer
[2025-02-06 19:50:16,941 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-02-06 19:50:16,942 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-02-06 19:50:16,942 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-02-06 19:50:16,942 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-02-06 19:50:16,942 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:14" (3/4) ...
[2025-02-06 19:50:16,944 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-02-06 19:50:17,006 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-02-06 19:50:17,007 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-02-06 19:50:17,008 INFO  L158              Benchmark]: Toolchain (without parser) took 3931.94ms. Allocated memory is still 142.6MB. Free memory was 105.4MB in the beginning and 61.2MB in the end (delta: 44.2MB). Peak memory consumption was 40.5MB. Max. memory is 16.1GB.
[2025-02-06 19:50:17,010 INFO  L158              Benchmark]: CDTParser took 0.29ms. Allocated memory is still 201.3MB. Free memory is still 126.4MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:50:17,010 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 290.91ms. Allocated memory is still 142.6MB. Free memory was 105.4MB in the beginning and 91.7MB in the end (delta: 13.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
[2025-02-06 19:50:17,010 INFO  L158              Benchmark]: Boogie Procedure Inliner took 45.21ms. Allocated memory is still 142.6MB. Free memory was 91.7MB in the beginning and 89.8MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:50:17,010 INFO  L158              Benchmark]: Boogie Preprocessor took 52.94ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 87.9MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:50:17,010 INFO  L158              Benchmark]: IcfgBuilder took 561.59ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 65.6MB in the end (delta: 22.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB.
[2025-02-06 19:50:17,011 INFO  L158              Benchmark]: BuchiAutomizer took 2911.31ms. Allocated memory is still 142.6MB. Free memory was 65.6MB in the beginning and 66.4MB in the end (delta: -785.5kB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:50:17,011 INFO  L158              Benchmark]: Witness Printer took 65.09ms. Allocated memory is still 142.6MB. Free memory was 66.4MB in the beginning and 61.2MB in the end (delta: 5.2MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:50:17,012 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.29ms. Allocated memory is still 201.3MB. Free memory is still 126.4MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 290.91ms. Allocated memory is still 142.6MB. Free memory was 105.4MB in the beginning and 91.7MB in the end (delta: 13.7MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 45.21ms. Allocated memory is still 142.6MB. Free memory was 91.7MB in the beginning and 89.8MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB.
 * Boogie Preprocessor took 52.94ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 87.9MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB.
 * IcfgBuilder took 561.59ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 65.6MB in the end (delta: 22.3MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 2911.31ms. Allocated memory is still 142.6MB. Free memory was 65.6MB in the beginning and 66.4MB in the end (delta: -785.5kB). There was no memory consumed. Max. memory is 16.1GB.
 * Witness Printer took 65.09ms. Allocated memory is still 142.6MB. Free memory was 66.4MB in the beginning and 61.2MB in the end (delta: 5.2MB). There was no memory consumed. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1251 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 2.7s and 10 iterations.  TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 111 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1139 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1139 mSDsluCounter, 3043 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1628 mSDsCounter, 62 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 208 IncrementalHoareTripleChecker+Invalid, 270 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 62 mSolverCounterUnsat, 1415 mSDtfsCounter, 208 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 279]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L25]               int max_loop ;
[L26]               int num ;
[L27]               int i  ;
[L28]               int e  ;
[L29]               int timer ;
[L30]               char data_0  ;
[L31]               char data_1  ;
[L74]               int P_1_pc;
[L75]               int P_1_st  ;
[L76]               int P_1_i  ;
[L77]               int P_1_ev  ;
[L132]              int C_1_pc  ;
[L133]              int C_1_st  ;
[L134]              int C_1_i  ;
[L135]              int C_1_ev  ;
[L136]              int C_1_pr  ;
        VAL         [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L500]              int count ;
[L501]              int __retres2 ;
[L505]              num  =    0
[L506]              i  =    0
[L507]              max_loop = 2
[L509]              timer  =    0
[L510]              P_1_pc  =    0
[L511]              C_1_pc  =    0
[L513]              count = 0
[L514]  CALL        init_model()
[L493]              P_1_i = 1
[L494]              C_1_i = 1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L514]  RET         init_model()
[L515]  CALL        start_simulation()
[L431]              int kernel_st ;
[L432]              int tmp ;
[L433]              int tmp___0 ;
[L437]              kernel_st = 0
[L438]  FCALL       update_channels()
[L439]  CALL        init_threads()
[L236]  COND TRUE   (int )P_1_i == 1
[L237]              P_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L241]  COND TRUE   (int )C_1_i == 1
[L242]              C_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L439]  RET         init_threads()
[L440]  FCALL       fire_delta_events()
[L441]  CALL        activate_threads()
[L375]              int tmp ;
[L376]              int tmp___0 ;
[L377]              int tmp___1 ;
[L381]  CALL, EXPR  is_P_1_triggered()
[L114]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L117]  COND FALSE  !((int )P_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L127]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L129]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L381]  RET, EXPR   is_P_1_triggered()
[L381]              tmp = is_P_1_triggered()
[L383]  COND FALSE  !(\read(tmp))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L389]  CALL, EXPR  is_C_1_triggered()
[L196]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L199]  COND FALSE  !((int )C_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L209]  COND FALSE  !((int )C_1_pc == 2)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L219]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L221]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L389]  RET, EXPR   is_C_1_triggered()
[L389]              tmp___1 = is_C_1_triggered()
[L391]  COND FALSE  !(\read(tmp___1))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L441]  RET         activate_threads()
[L442]  FCALL       reset_delta_events()
[L445]  COND TRUE   1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L448]              kernel_st = 1
[L449]  CALL        eval()
[L272]              int tmp ;
[L273]              int tmp___0 ;
[L274]              int tmp___1 ;
[L275]              int tmp___2 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
Loop:
[L279]  COND TRUE   1
[L282]  CALL, EXPR  exists_runnable_thread()
[L251]              int __retres1 ;
[L254]  COND TRUE   (int )P_1_st == 0
[L255]              __retres1 = 1
[L268]              return (__retres1);
[L282]  RET, EXPR   exists_runnable_thread()
[L282]              tmp___2 = exists_runnable_thread()
[L284]  COND TRUE   \read(tmp___2)
[L289]  COND TRUE   (int )P_1_st == 0
[L291]              tmp = __VERIFIER_nondet_int()
[L293]  COND FALSE  !(\read(tmp))
[L304]  COND TRUE   (int )C_1_st == 0
[L306]              tmp___1 = __VERIFIER_nondet_int()
[L308]  COND FALSE  !(\read(tmp___1))
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 279]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L25]               int max_loop ;
[L26]               int num ;
[L27]               int i  ;
[L28]               int e  ;
[L29]               int timer ;
[L30]               char data_0  ;
[L31]               char data_1  ;
[L74]               int P_1_pc;
[L75]               int P_1_st  ;
[L76]               int P_1_i  ;
[L77]               int P_1_ev  ;
[L132]              int C_1_pc  ;
[L133]              int C_1_st  ;
[L134]              int C_1_i  ;
[L135]              int C_1_ev  ;
[L136]              int C_1_pr  ;
        VAL         [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0]
[L500]              int count ;
[L501]              int __retres2 ;
[L505]              num  =    0
[L506]              i  =    0
[L507]              max_loop = 2
[L509]              timer  =    0
[L510]              P_1_pc  =    0
[L511]              C_1_pc  =    0
[L513]              count = 0
[L514]  CALL        init_model()
[L493]              P_1_i = 1
[L494]              C_1_i = 1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L514]  RET         init_model()
[L515]  CALL        start_simulation()
[L431]              int kernel_st ;
[L432]              int tmp ;
[L433]              int tmp___0 ;
[L437]              kernel_st = 0
[L438]  FCALL       update_channels()
[L439]  CALL        init_threads()
[L236]  COND TRUE   (int )P_1_i == 1
[L237]              P_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L241]  COND TRUE   (int )C_1_i == 1
[L242]              C_1_st = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L439]  RET         init_threads()
[L440]  FCALL       fire_delta_events()
[L441]  CALL        activate_threads()
[L375]              int tmp ;
[L376]              int tmp___0 ;
[L377]              int tmp___1 ;
[L381]  CALL, EXPR  is_P_1_triggered()
[L114]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L117]  COND FALSE  !((int )P_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L127]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L129]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L381]  RET, EXPR   is_P_1_triggered()
[L381]              tmp = is_P_1_triggered()
[L383]  COND FALSE  !(\read(tmp))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L389]  CALL, EXPR  is_C_1_triggered()
[L196]              int __retres1 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L199]  COND FALSE  !((int )C_1_pc == 1)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L209]  COND FALSE  !((int )C_1_pc == 2)
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L219]              __retres1 = 0
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L221]              return (__retres1);
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L389]  RET, EXPR   is_C_1_triggered()
[L389]              tmp___1 = is_C_1_triggered()
[L391]  COND FALSE  !(\read(tmp___1))
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L441]  RET         activate_threads()
[L442]  FCALL       reset_delta_events()
[L445]  COND TRUE   1
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
[L448]              kernel_st = 1
[L449]  CALL        eval()
[L272]              int tmp ;
[L273]              int tmp___0 ;
[L274]              int tmp___1 ;
[L275]              int tmp___2 ;
        VAL         [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0]
Loop:
[L279]  COND TRUE   1
[L282]  CALL, EXPR  exists_runnable_thread()
[L251]              int __retres1 ;
[L254]  COND TRUE   (int )P_1_st == 0
[L255]              __retres1 = 1
[L268]              return (__retres1);
[L282]  RET, EXPR   exists_runnable_thread()
[L282]              tmp___2 = exists_runnable_thread()
[L284]  COND TRUE   \read(tmp___2)
[L289]  COND TRUE   (int )P_1_st == 0
[L291]              tmp = __VERIFIER_nondet_int()
[L293]  COND FALSE  !(\read(tmp))
[L304]  COND TRUE   (int )C_1_st == 0
[L306]              tmp___1 = __VERIFIER_nondet_int()
[L308]  COND FALSE  !(\read(tmp___1))
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-02-06 19:50:17,033 INFO  L552       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)