./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c74d959057dcef9924c2fba34a5baac5be90cef6ad1eac335d6f9d2397fc60bb --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:50:21,023 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:50:21,099 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:50:21,105 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:50:21,108 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:50:21,109 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:50:21,139 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:50:21,140 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:50:21,140 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:50:21,141 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:50:21,141 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:50:21,142 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:50:21,142 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:50:21,142 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:50:21,142 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:50:21,143 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:50:21,143 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:50:21,144 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:50:21,144 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:50:21,145 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:50:21,145 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c74d959057dcef9924c2fba34a5baac5be90cef6ad1eac335d6f9d2397fc60bb [2025-02-06 19:50:21,422 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:50:21,431 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:50:21,433 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:50:21,434 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:50:21,435 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:50:21,436 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c [2025-02-06 19:50:22,715 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/714eeb697/c065609567b24e2b9c9922c574a99b3e/FLAG9b8e644db [2025-02-06 19:50:23,006 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:50:23,010 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_1.cil-1.c [2025-02-06 19:50:23,027 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/714eeb697/c065609567b24e2b9c9922c574a99b3e/FLAG9b8e644db [2025-02-06 19:50:23,053 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/714eeb697/c065609567b24e2b9c9922c574a99b3e [2025-02-06 19:50:23,056 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:50:23,057 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:50:23,059 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:23,059 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:50:23,064 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:50:23,065 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,066 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@acf3473 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23, skipping insertion in model container [2025-02-06 19:50:23,066 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,084 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:50:23,261 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:23,272 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:50:23,302 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:23,330 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:50:23,331 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23 WrapperNode [2025-02-06 19:50:23,331 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:23,332 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:23,332 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:50:23,332 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:50:23,338 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,347 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,370 INFO L138 Inliner]: procedures = 24, calls = 24, calls flagged for inlining = 19, calls inlined = 23, statements flattened = 253 [2025-02-06 19:50:23,371 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:23,371 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:50:23,371 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:50:23,371 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:50:23,378 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,378 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,379 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,393 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:50:23,394 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,394 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,398 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,399 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,400 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,401 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,402 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:50:23,403 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:50:23,403 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:50:23,403 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:50:23,404 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (1/1) ... [2025-02-06 19:50:23,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:23,419 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:23,430 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:23,434 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:50:23,450 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:50:23,451 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:50:23,451 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:50:23,451 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:50:23,518 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:50:23,520 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:50:23,800 INFO L? ?]: Removed 39 outVars from TransFormulas that were not future-live. [2025-02-06 19:50:23,800 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:50:23,808 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:50:23,809 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:50:23,809 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:23 BoogieIcfgContainer [2025-02-06 19:50:23,809 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:50:23,810 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:50:23,810 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:50:23,814 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:50:23,814 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:23,814 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:23" (1/3) ... [2025-02-06 19:50:23,815 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8fdfefc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:23, skipping insertion in model container [2025-02-06 19:50:23,815 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:23,815 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:23" (2/3) ... [2025-02-06 19:50:23,815 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@8fdfefc and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:23, skipping insertion in model container [2025-02-06 19:50:23,816 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:23,816 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:23" (3/3) ... [2025-02-06 19:50:23,817 INFO L363 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_1.cil-1.c [2025-02-06 19:50:23,859 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:50:23,859 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:50:23,859 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:50:23,860 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:50:23,860 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:50:23,860 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:50:23,861 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:50:23,861 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:50:23,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 87 states, 85 states have (on average 1.4352941176470588) internal successors, (122), 86 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:23,888 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2025-02-06 19:50:23,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:23,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:23,895 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-02-06 19:50:23,896 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:23,896 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:50:23,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 87 states, 85 states have (on average 1.4352941176470588) internal successors, (122), 86 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:23,900 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 76 [2025-02-06 19:50:23,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:23,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:23,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-02-06 19:50:23,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:23,907 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;" [2025-02-06 19:50:23,907 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume !true;" "havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:23,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:23,910 INFO L85 PathProgramCache]: Analyzing trace with hash 1384039324, now seen corresponding path program 1 times [2025-02-06 19:50:23,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:23,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993515668] [2025-02-06 19:50:23,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:23,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:23,983 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:23,997 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:23,998 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:23,998 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,098 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,099 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,099 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [993515668] [2025-02-06 19:50:24,100 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [993515668] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,100 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,100 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:24,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1922791098] [2025-02-06 19:50:24,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,106 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:24,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,108 INFO L85 PathProgramCache]: Analyzing trace with hash 371884777, now seen corresponding path program 1 times [2025-02-06 19:50:24,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [745206585] [2025-02-06 19:50:24,108 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,115 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-02-06 19:50:24,121 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-02-06 19:50:24,121 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,121 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,131 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,132 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [745206585] [2025-02-06 19:50:24,132 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [745206585] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,133 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,133 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:24,133 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722423755] [2025-02-06 19:50:24,133 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,134 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,135 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,156 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:24,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:24,159 INFO L87 Difference]: Start difference. First operand has 87 states, 85 states have (on average 1.4352941176470588) internal successors, (122), 86 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,183 INFO L93 Difference]: Finished difference Result 81 states and 108 transitions. [2025-02-06 19:50:24,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81 states and 108 transitions. [2025-02-06 19:50:24,188 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2025-02-06 19:50:24,197 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81 states to 73 states and 100 transitions. [2025-02-06 19:50:24,199 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2025-02-06 19:50:24,200 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2025-02-06 19:50:24,201 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 100 transitions. [2025-02-06 19:50:24,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 100 transitions. [2025-02-06 19:50:24,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 100 transitions. [2025-02-06 19:50:24,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2025-02-06 19:50:24,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.36986301369863) internal successors, (100), 72 states have internal predecessors, (100), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 100 transitions. [2025-02-06 19:50:24,235 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 100 transitions. [2025-02-06 19:50:24,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:24,239 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 100 transitions. [2025-02-06 19:50:24,241 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:50:24,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 100 transitions. [2025-02-06 19:50:24,242 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2025-02-06 19:50:24,242 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:24,242 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:24,245 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,245 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,245 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;" [2025-02-06 19:50:24,245 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:24,246 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,247 INFO L85 PathProgramCache]: Analyzing trace with hash 1384038363, now seen corresponding path program 1 times [2025-02-06 19:50:24,247 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,247 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941438810] [2025-02-06 19:50:24,247 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,247 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,258 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:24,267 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:24,269 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,304 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,308 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941438810] [2025-02-06 19:50:24,308 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941438810] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,308 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,308 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:24,308 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1910983627] [2025-02-06 19:50:24,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,308 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:24,309 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,309 INFO L85 PathProgramCache]: Analyzing trace with hash -777328657, now seen corresponding path program 1 times [2025-02-06 19:50:24,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1414011544] [2025-02-06 19:50:24,309 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,315 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-02-06 19:50:24,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-02-06 19:50:24,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1414011544] [2025-02-06 19:50:24,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1414011544] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:24,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1184436652] [2025-02-06 19:50:24,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,401 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,401 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:24,402 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:24,402 INFO L87 Difference]: Start difference. First operand 73 states and 100 transitions. cyclomatic complexity: 28 Second operand has 3 states, 3 states have (on average 2.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,417 INFO L93 Difference]: Finished difference Result 73 states and 99 transitions. [2025-02-06 19:50:24,417 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 73 states and 99 transitions. [2025-02-06 19:50:24,418 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2025-02-06 19:50:24,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 73 states to 73 states and 99 transitions. [2025-02-06 19:50:24,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 73 [2025-02-06 19:50:24,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 73 [2025-02-06 19:50:24,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 73 states and 99 transitions. [2025-02-06 19:50:24,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,422 INFO L218 hiAutomatonCegarLoop]: Abstraction has 73 states and 99 transitions. [2025-02-06 19:50:24,423 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states and 99 transitions. [2025-02-06 19:50:24,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2025-02-06 19:50:24,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.356164383561644) internal successors, (99), 72 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 99 transitions. [2025-02-06 19:50:24,430 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 99 transitions. [2025-02-06 19:50:24,430 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:24,431 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 99 transitions. [2025-02-06 19:50:24,431 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:50:24,431 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 99 transitions. [2025-02-06 19:50:24,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 67 [2025-02-06 19:50:24,432 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:24,432 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:24,432 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,432 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" [2025-02-06 19:50:24,432 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:24,433 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,433 INFO L85 PathProgramCache]: Analyzing trace with hash 1384038332, now seen corresponding path program 1 times [2025-02-06 19:50:24,433 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,433 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692377317] [2025-02-06 19:50:24,433 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,443 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:24,449 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:24,449 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,450 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:24,453 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:24,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:24,461 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,483 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:24,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,484 INFO L85 PathProgramCache]: Analyzing trace with hash -777328657, now seen corresponding path program 2 times [2025-02-06 19:50:24,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461256832] [2025-02-06 19:50:24,484 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:24,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,492 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 16 statements into 1 equivalence classes. [2025-02-06 19:50:24,497 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-02-06 19:50:24,499 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:24,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,554 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,554 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,555 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1461256832] [2025-02-06 19:50:24,555 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1461256832] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,555 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:24,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [526764455] [2025-02-06 19:50:24,555 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,555 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,556 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,556 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:24,556 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:24,556 INFO L87 Difference]: Start difference. First operand 73 states and 99 transitions. cyclomatic complexity: 27 Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,612 INFO L93 Difference]: Finished difference Result 78 states and 104 transitions. [2025-02-06 19:50:24,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78 states and 104 transitions. [2025-02-06 19:50:24,613 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2025-02-06 19:50:24,614 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78 states to 78 states and 104 transitions. [2025-02-06 19:50:24,614 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78 [2025-02-06 19:50:24,614 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78 [2025-02-06 19:50:24,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 104 transitions. [2025-02-06 19:50:24,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78 states and 104 transitions. [2025-02-06 19:50:24,615 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 104 transitions. [2025-02-06 19:50:24,618 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 76. [2025-02-06 19:50:24,618 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76 states, 76 states have (on average 1.3421052631578947) internal successors, (102), 75 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76 states to 76 states and 102 transitions. [2025-02-06 19:50:24,618 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76 states and 102 transitions. [2025-02-06 19:50:24,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:24,621 INFO L432 stractBuchiCegarLoop]: Abstraction has 76 states and 102 transitions. [2025-02-06 19:50:24,621 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:50:24,621 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76 states and 102 transitions. [2025-02-06 19:50:24,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 70 [2025-02-06 19:50:24,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:24,622 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:24,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,622 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" [2025-02-06 19:50:24,622 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret10#1;havoc stop_simulation_#t~ret10#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret10#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-02-06 19:50:24,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,623 INFO L85 PathProgramCache]: Analyzing trace with hash 1384038332, now seen corresponding path program 2 times [2025-02-06 19:50:24,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460225493] [2025-02-06 19:50:24,623 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:24,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,629 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:24,632 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:24,632 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:24,632 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,632 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:24,657 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:50:24,664 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:50:24,664 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,664 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:24,669 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,669 INFO L85 PathProgramCache]: Analyzing trace with hash -1408200579, now seen corresponding path program 1 times [2025-02-06 19:50:24,669 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,669 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11937176] [2025-02-06 19:50:24,669 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,673 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-02-06 19:50:24,677 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-02-06 19:50:24,680 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,681 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,703 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11937176] [2025-02-06 19:50:24,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11937176] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:24,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [75264572] [2025-02-06 19:50:24,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,707 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,707 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,707 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:24,707 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:24,708 INFO L87 Difference]: Start difference. First operand 76 states and 102 transitions. cyclomatic complexity: 27 Second operand has 3 states, 3 states have (on average 5.666666666666667) internal successors, (17), 3 states have internal predecessors, (17), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,746 INFO L93 Difference]: Finished difference Result 115 states and 150 transitions. [2025-02-06 19:50:24,746 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 150 transitions. [2025-02-06 19:50:24,748 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2025-02-06 19:50:24,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 150 transitions. [2025-02-06 19:50:24,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-02-06 19:50:24,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-02-06 19:50:24,753 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 150 transitions. [2025-02-06 19:50:24,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 150 transitions. [2025-02-06 19:50:24,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 150 transitions. [2025-02-06 19:50:24,760 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 105. [2025-02-06 19:50:24,761 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.3047619047619048) internal successors, (137), 104 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 137 transitions. [2025-02-06 19:50:24,762 INFO L240 hiAutomatonCegarLoop]: Abstraction has 105 states and 137 transitions. [2025-02-06 19:50:24,763 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:24,764 INFO L432 stractBuchiCegarLoop]: Abstraction has 105 states and 137 transitions. [2025-02-06 19:50:24,764 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:50:24,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 137 transitions. [2025-02-06 19:50:24,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:50:24,765 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:24,765 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:24,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,766 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:24,766 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume !(0 == ~p_dw_st~0);" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet9#1;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1;" "assume !(0 == ~c_dr_pc~0);" "assume 1 == ~c_dr_pc~0;" "do_read_c_~a~0#1 := ~a_t~0;" "do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1;" "assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1;" "assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0;" "havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2;" "assume ~p_last_write~0 == ~c_last_read~0;" "assume ~p_num_write~0 == ~c_num_read~0;" "assume true;" "assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1;" "havoc do_read_c_~a~0#1;assume { :end_inline_do_read_c } true;" [2025-02-06 19:50:24,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,767 INFO L85 PathProgramCache]: Analyzing trace with hash -1379019877, now seen corresponding path program 1 times [2025-02-06 19:50:24,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826879670] [2025-02-06 19:50:24,767 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:24,774 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:24,775 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,775 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:24,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:24,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:24,779 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:24,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,783 INFO L85 PathProgramCache]: Analyzing trace with hash 905493999, now seen corresponding path program 1 times [2025-02-06 19:50:24,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1499597968] [2025-02-06 19:50:24,783 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,788 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:24,790 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:24,790 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1499597968] [2025-02-06 19:50:24,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1499597968] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:24,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1964150212] [2025-02-06 19:50:24,808 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,808 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,808 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,808 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:24,809 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:24,809 INFO L87 Difference]: Start difference. First operand 105 states and 137 transitions. cyclomatic complexity: 33 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,840 INFO L93 Difference]: Finished difference Result 115 states and 148 transitions. [2025-02-06 19:50:24,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 148 transitions. [2025-02-06 19:50:24,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2025-02-06 19:50:24,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 148 transitions. [2025-02-06 19:50:24,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-02-06 19:50:24,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-02-06 19:50:24,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 148 transitions. [2025-02-06 19:50:24,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 148 transitions. [2025-02-06 19:50:24,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 148 transitions. [2025-02-06 19:50:24,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 105. [2025-02-06 19:50:24,850 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 105 states, 105 states have (on average 1.2857142857142858) internal successors, (135), 104 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 135 transitions. [2025-02-06 19:50:24,851 INFO L240 hiAutomatonCegarLoop]: Abstraction has 105 states and 135 transitions. [2025-02-06 19:50:24,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:24,852 INFO L432 stractBuchiCegarLoop]: Abstraction has 105 states and 135 transitions. [2025-02-06 19:50:24,852 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:50:24,852 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 105 states and 135 transitions. [2025-02-06 19:50:24,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:50:24,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:24,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:24,855 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,855 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:24,855 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:24,856 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume 0 == ~p_dw_pc~0;" "assume true;" "assume true;" "assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1;" "havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true;" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet9#1;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1;" "assume !(0 == ~c_dr_pc~0);" "assume 1 == ~c_dr_pc~0;" "do_read_c_~a~0#1 := ~a_t~0;" "do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1;" "assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1;" "assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0;" "havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2;" "assume ~p_last_write~0 == ~c_last_read~0;" "assume ~p_num_write~0 == ~c_num_read~0;" "assume true;" "assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1;" "havoc do_read_c_~a~0#1;assume { :end_inline_do_read_c } true;" [2025-02-06 19:50:24,856 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1379019877, now seen corresponding path program 2 times [2025-02-06 19:50:24,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [227559077] [2025-02-06 19:50:24,857 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:24,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,862 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:24,868 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:24,869 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:24,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,870 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:24,876 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:50:24,878 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:50:24,878 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,879 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:24,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:24,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:24,886 INFO L85 PathProgramCache]: Analyzing trace with hash -2053570511, now seen corresponding path program 1 times [2025-02-06 19:50:24,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:24,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [942017489] [2025-02-06 19:50:24,886 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:24,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:24,896 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:24,900 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:24,902 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:24,902 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:24,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:24,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:24,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [942017489] [2025-02-06 19:50:24,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [942017489] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:24,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:24,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:24,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [215699710] [2025-02-06 19:50:24,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:24,937 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:24,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:24,937 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:24,937 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:24,937 INFO L87 Difference]: Start difference. First operand 105 states and 135 transitions. cyclomatic complexity: 31 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:24,978 INFO L93 Difference]: Finished difference Result 195 states and 247 transitions. [2025-02-06 19:50:24,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 195 states and 247 transitions. [2025-02-06 19:50:24,979 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 156 [2025-02-06 19:50:24,984 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 195 states to 195 states and 247 transitions. [2025-02-06 19:50:24,984 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-02-06 19:50:24,984 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-02-06 19:50:24,985 INFO L73 IsDeterministic]: Start isDeterministic. Operand 195 states and 247 transitions. [2025-02-06 19:50:24,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:24,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 195 states and 247 transitions. [2025-02-06 19:50:24,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states and 247 transitions. [2025-02-06 19:50:24,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2025-02-06 19:50:24,998 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2666666666666666) internal successors, (247), 194 states have internal predecessors, (247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:24,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 247 transitions. [2025-02-06 19:50:25,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 247 transitions. [2025-02-06 19:50:25,003 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:25,003 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 247 transitions. [2025-02-06 19:50:25,003 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:50:25,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 247 transitions. [2025-02-06 19:50:25,005 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 156 [2025-02-06 19:50:25,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:25,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:25,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,005 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume 0 == ~p_dw_pc~0;" "assume true;" "assume true;" "assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1;" "havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true;" [2025-02-06 19:50:25,005 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == ~c_dr_st~0);" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume !(0 == ~p_dw_st~0);" [2025-02-06 19:50:25,006 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,006 INFO L85 PathProgramCache]: Analyzing trace with hash -2006154003, now seen corresponding path program 1 times [2025-02-06 19:50:25,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392387880] [2025-02-06 19:50:25,006 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,016 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-02-06 19:50:25,022 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-02-06 19:50:25,022 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,022 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,113 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,114 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,114 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392387880] [2025-02-06 19:50:25,114 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392387880] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,114 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,114 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 19:50:25,114 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1733576661] [2025-02-06 19:50:25,114 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,114 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:25,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,114 INFO L85 PathProgramCache]: Analyzing trace with hash 148420815, now seen corresponding path program 1 times [2025-02-06 19:50:25,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,115 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [519879847] [2025-02-06 19:50:25,115 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,117 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:25,119 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:25,119 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,119 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,166 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,166 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [519879847] [2025-02-06 19:50:25,166 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [519879847] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,167 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,167 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:25,167 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1782653483] [2025-02-06 19:50:25,167 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,167 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:25,167 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:25,167 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:25,168 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:25,168 INFO L87 Difference]: Start difference. First operand 195 states and 247 transitions. cyclomatic complexity: 56 Second operand has 5 states, 5 states have (on average 1.8) internal successors, (9), 5 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,203 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:25,203 INFO L93 Difference]: Finished difference Result 199 states and 249 transitions. [2025-02-06 19:50:25,203 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 199 states and 249 transitions. [2025-02-06 19:50:25,205 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 160 [2025-02-06 19:50:25,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 199 states to 199 states and 249 transitions. [2025-02-06 19:50:25,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199 [2025-02-06 19:50:25,208 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199 [2025-02-06 19:50:25,208 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199 states and 249 transitions. [2025-02-06 19:50:25,209 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:25,209 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199 states and 249 transitions. [2025-02-06 19:50:25,209 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states and 249 transitions. [2025-02-06 19:50:25,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 195. [2025-02-06 19:50:25,221 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2564102564102564) internal successors, (245), 194 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,221 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 245 transitions. [2025-02-06 19:50:25,222 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 245 transitions. [2025-02-06 19:50:25,223 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:25,223 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 245 transitions. [2025-02-06 19:50:25,224 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:50:25,224 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 245 transitions. [2025-02-06 19:50:25,225 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 156 [2025-02-06 19:50:25,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:25,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:25,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,227 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume 0 == ~p_dw_pc~0;" "assume true;" "assume true;" "assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1;" "havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true;" [2025-02-06 19:50:25,228 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == ~c_dr_st~0);" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume !(0 == ~p_dw_st~0);" [2025-02-06 19:50:25,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,228 INFO L85 PathProgramCache]: Analyzing trace with hash -2006154003, now seen corresponding path program 2 times [2025-02-06 19:50:25,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1434848666] [2025-02-06 19:50:25,229 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:25,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,234 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 1 equivalence classes. [2025-02-06 19:50:25,237 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-02-06 19:50:25,237 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:25,237 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,319 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,319 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,320 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1434848666] [2025-02-06 19:50:25,320 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1434848666] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,320 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,320 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 19:50:25,320 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [37377576] [2025-02-06 19:50:25,320 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,320 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:25,321 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,321 INFO L85 PathProgramCache]: Analyzing trace with hash 145650252, now seen corresponding path program 1 times [2025-02-06 19:50:25,321 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,321 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [222170464] [2025-02-06 19:50:25,321 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,323 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:25,324 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:25,324 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,324 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,332 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,332 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [222170464] [2025-02-06 19:50:25,332 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [222170464] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,332 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,332 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:25,332 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980186502] [2025-02-06 19:50:25,332 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,333 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:25,333 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:25,333 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:25,333 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:25,333 INFO L87 Difference]: Start difference. First operand 195 states and 245 transitions. cyclomatic complexity: 54 Second operand has 3 states, 3 states have (on average 3.0) internal successors, (9), 2 states have internal predecessors, (9), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:25,356 INFO L93 Difference]: Finished difference Result 287 states and 361 transitions. [2025-02-06 19:50:25,356 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 287 states and 361 transitions. [2025-02-06 19:50:25,359 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 236 [2025-02-06 19:50:25,361 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 287 states to 287 states and 361 transitions. [2025-02-06 19:50:25,361 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 287 [2025-02-06 19:50:25,362 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 287 [2025-02-06 19:50:25,362 INFO L73 IsDeterministic]: Start isDeterministic. Operand 287 states and 361 transitions. [2025-02-06 19:50:25,362 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:25,362 INFO L218 hiAutomatonCegarLoop]: Abstraction has 287 states and 361 transitions. [2025-02-06 19:50:25,363 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states and 361 transitions. [2025-02-06 19:50:25,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 195. [2025-02-06 19:50:25,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195 states, 195 states have (on average 1.2512820512820513) internal successors, (244), 194 states have internal predecessors, (244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 244 transitions. [2025-02-06 19:50:25,372 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195 states and 244 transitions. [2025-02-06 19:50:25,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:25,373 INFO L432 stractBuchiCegarLoop]: Abstraction has 195 states and 244 transitions. [2025-02-06 19:50:25,373 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:50:25,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195 states and 244 transitions. [2025-02-06 19:50:25,375 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 144 [2025-02-06 19:50:25,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:25,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:25,375 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,375 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,376 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume 0 == ~p_dw_pc~0;" "assume true;" "assume true;" "assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1;" "havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true;" [2025-02-06 19:50:25,376 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet9#1;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume !(0 != eval_~tmp___0~1#1);" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume 0 == ~c_dr_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume !(0 == ~p_dw_st~0);" [2025-02-06 19:50:25,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,376 INFO L85 PathProgramCache]: Analyzing trace with hash -2006154003, now seen corresponding path program 3 times [2025-02-06 19:50:25,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930811333] [2025-02-06 19:50:25,376 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:25,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,385 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 21 statements into 1 equivalence classes. [2025-02-06 19:50:25,387 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-02-06 19:50:25,387 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:25,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,452 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,453 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,453 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930811333] [2025-02-06 19:50:25,453 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930811333] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,453 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,453 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 19:50:25,453 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1279686705] [2025-02-06 19:50:25,453 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,454 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:25,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,454 INFO L85 PathProgramCache]: Analyzing trace with hash -1265597703, now seen corresponding path program 1 times [2025-02-06 19:50:25,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996764097] [2025-02-06 19:50:25,454 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:25,458 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:25,458 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,458 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:25,459 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:25,459 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:25,460 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:25,460 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,460 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:25,462 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:25,537 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:25,537 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-06 19:50:25,538 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2025-02-06 19:50:25,538 INFO L87 Difference]: Start difference. First operand 195 states and 244 transitions. cyclomatic complexity: 54 Second operand has 7 states, 7 states have (on average 3.0) internal successors, (21), 7 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,628 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:25,628 INFO L93 Difference]: Finished difference Result 205 states and 244 transitions. [2025-02-06 19:50:25,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205 states and 244 transitions. [2025-02-06 19:50:25,630 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 107 [2025-02-06 19:50:25,631 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205 states to 199 states and 236 transitions. [2025-02-06 19:50:25,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 199 [2025-02-06 19:50:25,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 199 [2025-02-06 19:50:25,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199 states and 236 transitions. [2025-02-06 19:50:25,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:25,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199 states and 236 transitions. [2025-02-06 19:50:25,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states and 236 transitions. [2025-02-06 19:50:25,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 163. [2025-02-06 19:50:25,635 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 163 states, 163 states have (on average 1.2085889570552146) internal successors, (197), 162 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 197 transitions. [2025-02-06 19:50:25,636 INFO L240 hiAutomatonCegarLoop]: Abstraction has 163 states and 197 transitions. [2025-02-06 19:50:25,636 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-06 19:50:25,637 INFO L432 stractBuchiCegarLoop]: Abstraction has 163 states and 197 transitions. [2025-02-06 19:50:25,637 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:50:25,637 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 163 states and 197 transitions. [2025-02-06 19:50:25,638 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 89 [2025-02-06 19:50:25,638 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:25,638 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:25,639 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,639 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:25,639 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret7#1, eval_#t~nondet8#1, eval_#t~nondet9#1, eval_~tmp~1#1, eval_~tmp___0~1#1, eval_~tmp___1~0#1;havoc eval_~tmp~1#1;havoc eval_~tmp___0~1#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume !(0 == ~p_dw_pc~0);" "assume 1 == ~p_dw_pc~0;" "havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1;" "assume !(0 != immediate_notify_threads_~tmp~0#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1;" "assume !(0 != immediate_notify_threads_~tmp___0~0#1);" [2025-02-06 19:50:25,639 INFO L754 eck$LassoCheckResult]: Loop: "havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;assume { :end_inline_immediate_notify_threads } true;~q_write_ev~0 := 2;" "assume true;" "assume 0 == ~q_free~0;~p_dw_st~0 := 2;~p_dw_pc~0 := 1;" "havoc do_write_p_#t~nondet6#1;assume { :end_inline_do_write_p } true;" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet9#1;eval_~tmp___0~1#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1;" "assume 0 != eval_~tmp___0~1#1;~c_dr_st~0 := 1;assume { :begin_inline_do_read_c } true;havoc do_read_c_~a~0#1;havoc do_read_c_~a~0#1;" "assume !(0 == ~c_dr_pc~0);" "assume 1 == ~c_dr_pc~0;" "do_read_c_~a~0#1 := ~a_t~0;" "do_read_c_~a~0#1 := ~q_buf_0~0;~c_last_read~0 := do_read_c_~a~0#1;~c_num_read~0 := 1 + ~c_num_read~0;~q_free~0 := 1;~q_read_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1;" "assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1;" "assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0;" "havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;assume { :end_inline_immediate_notify_threads } true;~q_read_ev~0 := 2;" "assume ~p_last_write~0 == ~c_last_read~0;" "assume ~p_num_write~0 == ~c_num_read~0;" "assume true;" "assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 1;~a_t~0 := do_read_c_~a~0#1;" "havoc do_read_c_~a~0#1;assume { :end_inline_do_read_c } true;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret7#1;havoc eval_#t~ret7#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet8#1;eval_~tmp~1#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume 0 != eval_~tmp~1#1;~p_dw_st~0 := 1;assume { :begin_inline_do_write_p } true;havoc do_write_p_#t~nondet6#1;" "assume !(0 == ~p_dw_pc~0);" "assume 1 == ~p_dw_pc~0;" "havoc do_write_p_#t~nondet6#1;~q_buf_0~0 := do_write_p_#t~nondet6#1;havoc do_write_p_#t~nondet6#1;~p_last_write~0 := ~q_buf_0~0;~p_num_write~0 := 1 + ~p_num_write~0;~q_free~0 := 0;~q_write_ev~0 := 1;assume { :begin_inline_immediate_notify_threads } true;havoc immediate_notify_threads_#t~ret4#1, immediate_notify_threads_#t~ret5#1, immediate_notify_threads_~tmp~0#1, immediate_notify_threads_~tmp___0~0#1;havoc immediate_notify_threads_~tmp~0#1;havoc immediate_notify_threads_~tmp___0~0#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "immediate_notify_threads_#t~ret4#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;immediate_notify_threads_~tmp~0#1 := immediate_notify_threads_#t~ret4#1;havoc immediate_notify_threads_#t~ret4#1;" "assume 0 != immediate_notify_threads_~tmp~0#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "immediate_notify_threads_#t~ret5#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;immediate_notify_threads_~tmp___0~0#1 := immediate_notify_threads_#t~ret5#1;havoc immediate_notify_threads_#t~ret5#1;" "assume 0 != immediate_notify_threads_~tmp___0~0#1;~c_dr_st~0 := 0;" [2025-02-06 19:50:25,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,642 INFO L85 PathProgramCache]: Analyzing trace with hash -995543360, now seen corresponding path program 1 times [2025-02-06 19:50:25,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1872105178] [2025-02-06 19:50:25,642 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,649 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:25,653 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:25,653 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1872105178] [2025-02-06 19:50:25,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1872105178] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:25,677 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1231369557] [2025-02-06 19:50:25,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,677 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:25,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:25,677 INFO L85 PathProgramCache]: Analyzing trace with hash -2100686086, now seen corresponding path program 1 times [2025-02-06 19:50:25,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:25,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936599944] [2025-02-06 19:50:25,677 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:25,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:25,685 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-02-06 19:50:25,687 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:50:25,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:25,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:25,727 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:25,728 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:25,728 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936599944] [2025-02-06 19:50:25,728 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936599944] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:25,728 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:25,728 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:25,729 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [980669455] [2025-02-06 19:50:25,729 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:25,729 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:25,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:25,730 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:25,731 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:25,731 INFO L87 Difference]: Start difference. First operand 163 states and 197 transitions. cyclomatic complexity: 37 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:25,733 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:25,733 INFO L93 Difference]: Finished difference Result 17 states and 16 transitions. [2025-02-06 19:50:25,733 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17 states and 16 transitions. [2025-02-06 19:50:25,734 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-02-06 19:50:25,734 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17 states to 0 states and 0 transitions. [2025-02-06 19:50:25,734 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2025-02-06 19:50:25,734 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2025-02-06 19:50:25,734 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2025-02-06 19:50:25,735 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:25,735 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-02-06 19:50:25,735 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-02-06 19:50:25,735 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:25,736 INFO L432 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-02-06 19:50:25,736 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:50:25,736 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2025-02-06 19:50:25,736 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-02-06 19:50:25,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2025-02-06 19:50:25,744 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:50:25 BoogieIcfgContainer [2025-02-06 19:50:25,745 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:50:25,745 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:50:25,745 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:50:25,745 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:50:25,746 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:23" (3/4) ... [2025-02-06 19:50:25,748 INFO L149 WitnessPrinter]: No result that supports witness generation found [2025-02-06 19:50:25,749 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:50:25,751 INFO L158 Benchmark]: Toolchain (without parser) took 2692.43ms. Allocated memory is still 142.6MB. Free memory was 111.5MB in the beginning and 89.6MB in the end (delta: 21.9MB). Peak memory consumption was 21.5MB. Max. memory is 16.1GB. [2025-02-06 19:50:25,752 INFO L158 Benchmark]: CDTParser took 0.32ms. Allocated memory is still 201.3MB. Free memory is still 131.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:25,752 INFO L158 Benchmark]: CACSL2BoogieTranslator took 272.72ms. Allocated memory is still 142.6MB. Free memory was 111.5MB in the beginning and 99.7MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:25,753 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.70ms. Allocated memory is still 142.6MB. Free memory was 99.7MB in the beginning and 97.3MB in the end (delta: 2.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:25,753 INFO L158 Benchmark]: Boogie Preprocessor took 31.27ms. Allocated memory is still 142.6MB. Free memory was 97.3MB in the beginning and 96.5MB in the end (delta: 861.9kB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:25,753 INFO L158 Benchmark]: IcfgBuilder took 405.98ms. Allocated memory is still 142.6MB. Free memory was 96.5MB in the beginning and 78.6MB in the end (delta: 17.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-02-06 19:50:25,753 INFO L158 Benchmark]: BuchiAutomizer took 1934.96ms. Allocated memory is still 142.6MB. Free memory was 77.7MB in the beginning and 89.6MB in the end (delta: -11.9MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:25,753 INFO L158 Benchmark]: Witness Printer took 3.60ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 89.6MB in the end (delta: 24.1kB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:25,755 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.32ms. Allocated memory is still 201.3MB. Free memory is still 131.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 272.72ms. Allocated memory is still 142.6MB. Free memory was 111.5MB in the beginning and 99.7MB in the end (delta: 11.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.70ms. Allocated memory is still 142.6MB. Free memory was 99.7MB in the beginning and 97.3MB in the end (delta: 2.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 31.27ms. Allocated memory is still 142.6MB. Free memory was 97.3MB in the beginning and 96.5MB in the end (delta: 861.9kB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 405.98ms. Allocated memory is still 142.6MB. Free memory was 96.5MB in the beginning and 78.6MB in the end (delta: 17.9MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 1934.96ms. Allocated memory is still 142.6MB. Free memory was 77.7MB in the beginning and 89.6MB in the end (delta: -11.9MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 3.60ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 89.6MB in the end (delta: 24.1kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 10 terminating modules (10 trivial, 0 deterministic, 0 nondeterministic). 10 modules have a trivial ranking function, the largest among these consists of 7 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 1.8s and 11 iterations. TraceHistogramMax:1. Analysis of lassos took 1.2s. Construction of modules took 0.2s. Büchi inclusion checks took 0.3s. Highest rank in rank-based complementation 0. Minimization of det autom 10. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 154 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 539 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 539 mSDsluCounter, 2255 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1209 mSDsCounter, 34 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 178 IncrementalHoareTripleChecker+Invalid, 212 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 34 mSolverCounterUnsat, 1046 mSDtfsCounter, 178 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI4 SFLT0 conc0 concLT0 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2025-02-06 19:50:25,767 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE