./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:50:23,483 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:50:23,557 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:50:23,565 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:50:23,567 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:50:23,567 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:50:23,596 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:50:23,597 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:50:23,597 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:50:23,598 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:50:23,599 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:50:23,599 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:50:23,599 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:50:23,599 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:50:23,599 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:50:23,599 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:50:23,599 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:50:23,600 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:50:23,600 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:50:23,600 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:50:23,601 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:50:23,601 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:50:23,602 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:50:23,602 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:50:23,602 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:50:23,602 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> b74079121634b4e5d8b815834e604eed77442466d93875e78a8cab3fe135fa1f [2025-02-06 19:50:23,879 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:50:23,888 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:50:23,890 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:50:23,891 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:50:23,891 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:50:23,892 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2025-02-06 19:50:25,166 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/ef357e4c1/9c4841eaf4c043a88c757430c09df127/FLAGbd9f2a44f [2025-02-06 19:50:25,420 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:50:25,421 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_2.cil-1.c [2025-02-06 19:50:25,430 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/ef357e4c1/9c4841eaf4c043a88c757430c09df127/FLAGbd9f2a44f [2025-02-06 19:50:25,444 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/ef357e4c1/9c4841eaf4c043a88c757430c09df127 [2025-02-06 19:50:25,446 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:50:25,449 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:50:25,451 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:25,451 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:50:25,454 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:50:25,455 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,456 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1ed0f9a0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25, skipping insertion in model container [2025-02-06 19:50:25,456 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,481 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:50:25,622 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:25,632 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:50:25,658 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:25,677 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:50:25,677 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25 WrapperNode [2025-02-06 19:50:25,677 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:25,678 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:25,678 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:50:25,678 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:50:25,684 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,691 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,710 INFO L138 Inliner]: procedures = 29, calls = 32, calls flagged for inlining = 27, calls inlined = 29, statements flattened = 295 [2025-02-06 19:50:25,711 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:25,711 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:50:25,711 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:50:25,711 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:50:25,718 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,718 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,720 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,734 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:50:25,734 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,734 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,738 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,739 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,740 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,741 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,743 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:50:25,743 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:50:25,743 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:50:25,744 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:50:25,744 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (1/1) ... [2025-02-06 19:50:25,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:25,760 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:25,771 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:25,777 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:50:25,791 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:50:25,791 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:50:25,791 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:50:25,791 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:50:25,844 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:50:25,845 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:50:26,149 INFO L? ?]: Removed 41 outVars from TransFormulas that were not future-live. [2025-02-06 19:50:26,149 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:50:26,158 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:50:26,159 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:50:26,159 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:26 BoogieIcfgContainer [2025-02-06 19:50:26,159 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:50:26,160 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:50:26,160 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:50:26,165 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:50:26,166 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:26,166 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:25" (1/3) ... [2025-02-06 19:50:26,167 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1964fba0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:26, skipping insertion in model container [2025-02-06 19:50:26,167 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:26,167 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:25" (2/3) ... [2025-02-06 19:50:26,167 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1964fba0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:26, skipping insertion in model container [2025-02-06 19:50:26,167 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:26,167 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:26" (3/3) ... [2025-02-06 19:50:26,168 INFO L363 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_2.cil-1.c [2025-02-06 19:50:26,208 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:50:26,208 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:50:26,209 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:50:26,209 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:50:26,209 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:50:26,209 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:50:26,209 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:50:26,209 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:50:26,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 108 states, 106 states have (on average 1.4811320754716981) internal successors, (157), 107 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:26,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:26,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:26,246 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,247 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:50:26,248 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 108 states, 106 states have (on average 1.4811320754716981) internal successors, (157), 107 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,253 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 71 [2025-02-06 19:50:26,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:26,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:26,257 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,258 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,264 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:26,265 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume !true;" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:26,269 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,270 INFO L85 PathProgramCache]: Analyzing trace with hash 1570986537, now seen corresponding path program 1 times [2025-02-06 19:50:26,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,278 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43781369] [2025-02-06 19:50:26,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:26,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,353 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:26,371 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:26,372 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:26,372 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:26,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:26,485 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:26,485 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43781369] [2025-02-06 19:50:26,486 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [43781369] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:26,486 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:26,486 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:26,487 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284773414] [2025-02-06 19:50:26,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:26,494 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:26,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1642634187, now seen corresponding path program 1 times [2025-02-06 19:50:26,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083498123] [2025-02-06 19:50:26,496 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:26,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-02-06 19:50:26,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-02-06 19:50:26,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:26,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:26,529 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:26,530 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:26,530 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083498123] [2025-02-06 19:50:26,531 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083498123] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:26,531 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:26,531 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:26,531 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1160036888] [2025-02-06 19:50:26,531 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:26,532 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:26,533 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:26,557 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:26,558 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:26,559 INFO L87 Difference]: Start difference. First operand has 108 states, 106 states have (on average 1.4811320754716981) internal successors, (157), 107 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:26,586 INFO L93 Difference]: Finished difference Result 104 states and 146 transitions. [2025-02-06 19:50:26,587 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 104 states and 146 transitions. [2025-02-06 19:50:26,590 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-02-06 19:50:26,596 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 104 states to 97 states and 139 transitions. [2025-02-06 19:50:26,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-02-06 19:50:26,597 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-02-06 19:50:26,599 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 139 transitions. [2025-02-06 19:50:26,600 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:26,602 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 139 transitions. [2025-02-06 19:50:26,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 139 transitions. [2025-02-06 19:50:26,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-02-06 19:50:26,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.4329896907216495) internal successors, (139), 96 states have internal predecessors, (139), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,631 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 139 transitions. [2025-02-06 19:50:26,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 139 transitions. [2025-02-06 19:50:26,635 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:26,638 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 139 transitions. [2025-02-06 19:50:26,639 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:50:26,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 139 transitions. [2025-02-06 19:50:26,641 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-02-06 19:50:26,642 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:26,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:26,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,646 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:26,647 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:26,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,648 INFO L85 PathProgramCache]: Analyzing trace with hash 1359635624, now seen corresponding path program 1 times [2025-02-06 19:50:26,648 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159874038] [2025-02-06 19:50:26,649 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:26,649 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,661 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:26,665 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:26,666 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:26,666 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:26,706 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:26,706 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:26,706 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [159874038] [2025-02-06 19:50:26,707 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [159874038] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:26,707 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:26,707 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:26,707 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269432375] [2025-02-06 19:50:26,707 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:26,707 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:26,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1322444771, now seen corresponding path program 1 times [2025-02-06 19:50:26,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1747775614] [2025-02-06 19:50:26,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:26,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,719 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:26,738 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:26,738 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:26,738 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:26,808 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:26,809 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:26,809 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1747775614] [2025-02-06 19:50:26,809 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1747775614] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:26,809 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:26,809 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:26,809 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979531357] [2025-02-06 19:50:26,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:26,810 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:26,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:26,810 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:26,810 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:26,811 INFO L87 Difference]: Start difference. First operand 97 states and 139 transitions. cyclomatic complexity: 43 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:26,825 INFO L93 Difference]: Finished difference Result 97 states and 138 transitions. [2025-02-06 19:50:26,825 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 138 transitions. [2025-02-06 19:50:26,827 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-02-06 19:50:26,828 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 97 states and 138 transitions. [2025-02-06 19:50:26,828 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97 [2025-02-06 19:50:26,828 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97 [2025-02-06 19:50:26,828 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97 states and 138 transitions. [2025-02-06 19:50:26,829 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:26,829 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97 states and 138 transitions. [2025-02-06 19:50:26,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states and 138 transitions. [2025-02-06 19:50:26,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2025-02-06 19:50:26,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97 states, 97 states have (on average 1.422680412371134) internal successors, (138), 96 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:26,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 138 transitions. [2025-02-06 19:50:26,847 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97 states and 138 transitions. [2025-02-06 19:50:26,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:26,848 INFO L432 stractBuchiCegarLoop]: Abstraction has 97 states and 138 transitions. [2025-02-06 19:50:26,848 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:50:26,849 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97 states and 138 transitions. [2025-02-06 19:50:26,850 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 65 [2025-02-06 19:50:26,850 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:26,850 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:26,851 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,851 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:26,851 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:26,851 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~q_read_ev~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:26,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1768459849, now seen corresponding path program 1 times [2025-02-06 19:50:26,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260298290] [2025-02-06 19:50:26,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:26,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,860 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:26,866 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:26,867 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:26,867 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:26,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:26,931 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:26,931 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260298290] [2025-02-06 19:50:26,931 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260298290] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:26,931 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:26,931 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:26,932 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [466799720] [2025-02-06 19:50:26,932 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:26,932 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:26,932 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:26,933 INFO L85 PathProgramCache]: Analyzing trace with hash -1322444771, now seen corresponding path program 2 times [2025-02-06 19:50:26,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:26,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655390090] [2025-02-06 19:50:26,933 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:26,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:26,941 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:26,949 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:26,953 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:26,954 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1655390090] [2025-02-06 19:50:27,030 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1655390090] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:27,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651398974] [2025-02-06 19:50:27,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,031 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:27,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,031 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:27,031 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:27,032 INFO L87 Difference]: Start difference. First operand 97 states and 138 transitions. cyclomatic complexity: 42 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,074 INFO L93 Difference]: Finished difference Result 157 states and 220 transitions. [2025-02-06 19:50:27,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157 states and 220 transitions. [2025-02-06 19:50:27,076 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 125 [2025-02-06 19:50:27,077 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157 states to 157 states and 220 transitions. [2025-02-06 19:50:27,077 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 157 [2025-02-06 19:50:27,078 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 157 [2025-02-06 19:50:27,078 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157 states and 220 transitions. [2025-02-06 19:50:27,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 157 states and 220 transitions. [2025-02-06 19:50:27,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states and 220 transitions. [2025-02-06 19:50:27,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 154. [2025-02-06 19:50:27,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 154 states, 154 states have (on average 1.4090909090909092) internal successors, (217), 153 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 217 transitions. [2025-02-06 19:50:27,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 154 states and 217 transitions. [2025-02-06 19:50:27,090 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:27,091 INFO L432 stractBuchiCegarLoop]: Abstraction has 154 states and 217 transitions. [2025-02-06 19:50:27,091 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:50:27,091 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 154 states and 217 transitions. [2025-02-06 19:50:27,094 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 122 [2025-02-06 19:50:27,094 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:27,094 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:27,095 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,095 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,095 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:27,095 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:27,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,096 INFO L85 PathProgramCache]: Analyzing trace with hash -7838388, now seen corresponding path program 1 times [2025-02-06 19:50:27,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [190851953] [2025-02-06 19:50:27,096 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,103 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,152 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [190851953] [2025-02-06 19:50:27,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [190851953] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,153 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,153 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:27,153 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017951495] [2025-02-06 19:50:27,153 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,154 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:27,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,154 INFO L85 PathProgramCache]: Analyzing trace with hash 511764410, now seen corresponding path program 1 times [2025-02-06 19:50:27,155 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068924518] [2025-02-06 19:50:27,155 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,164 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:27,169 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:27,170 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,170 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,227 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,227 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068924518] [2025-02-06 19:50:27,227 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068924518] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,227 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:27,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1616228491] [2025-02-06 19:50:27,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,227 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:27,227 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,228 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:27,228 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:27,228 INFO L87 Difference]: Start difference. First operand 154 states and 217 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 6.5) internal successors, (26), 4 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,311 INFO L93 Difference]: Finished difference Result 326 states and 454 transitions. [2025-02-06 19:50:27,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 326 states and 454 transitions. [2025-02-06 19:50:27,316 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 287 [2025-02-06 19:50:27,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 326 states to 326 states and 454 transitions. [2025-02-06 19:50:27,321 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 326 [2025-02-06 19:50:27,322 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 326 [2025-02-06 19:50:27,322 INFO L73 IsDeterministic]: Start isDeterministic. Operand 326 states and 454 transitions. [2025-02-06 19:50:27,323 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,323 INFO L218 hiAutomatonCegarLoop]: Abstraction has 326 states and 454 transitions. [2025-02-06 19:50:27,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 326 states and 454 transitions. [2025-02-06 19:50:27,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 326 to 258. [2025-02-06 19:50:27,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 258 states, 258 states have (on average 1.4069767441860466) internal successors, (363), 257 states have internal predecessors, (363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 363 transitions. [2025-02-06 19:50:27,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 258 states and 363 transitions. [2025-02-06 19:50:27,340 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:27,341 INFO L432 stractBuchiCegarLoop]: Abstraction has 258 states and 363 transitions. [2025-02-06 19:50:27,341 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:50:27,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 258 states and 363 transitions. [2025-02-06 19:50:27,343 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 226 [2025-02-06 19:50:27,343 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:27,343 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:27,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,344 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,344 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:27,344 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:27,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1005946225, now seen corresponding path program 1 times [2025-02-06 19:50:27,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1718770330] [2025-02-06 19:50:27,345 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,350 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,357 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,357 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,357 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,357 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:27,363 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,366 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,366 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,390 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:27,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1281093911, now seen corresponding path program 1 times [2025-02-06 19:50:27,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119541176] [2025-02-06 19:50:27,390 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,396 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:27,398 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:27,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,447 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119541176] [2025-02-06 19:50:27,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119541176] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:27,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356910962] [2025-02-06 19:50:27,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,448 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:27,448 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,448 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:27,448 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:27,448 INFO L87 Difference]: Start difference. First operand 258 states and 363 transitions. cyclomatic complexity: 107 Second operand has 5 states, 5 states have (on average 7.2) internal successors, (36), 5 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,494 INFO L93 Difference]: Finished difference Result 278 states and 383 transitions. [2025-02-06 19:50:27,495 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 278 states and 383 transitions. [2025-02-06 19:50:27,497 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 246 [2025-02-06 19:50:27,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 278 states to 278 states and 383 transitions. [2025-02-06 19:50:27,500 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 278 [2025-02-06 19:50:27,500 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 278 [2025-02-06 19:50:27,500 INFO L73 IsDeterministic]: Start isDeterministic. Operand 278 states and 383 transitions. [2025-02-06 19:50:27,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,504 INFO L218 hiAutomatonCegarLoop]: Abstraction has 278 states and 383 transitions. [2025-02-06 19:50:27,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 278 states and 383 transitions. [2025-02-06 19:50:27,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 278 to 270. [2025-02-06 19:50:27,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.3888888888888888) internal successors, (375), 269 states have internal predecessors, (375), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 375 transitions. [2025-02-06 19:50:27,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 270 states and 375 transitions. [2025-02-06 19:50:27,518 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:27,518 INFO L432 stractBuchiCegarLoop]: Abstraction has 270 states and 375 transitions. [2025-02-06 19:50:27,518 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:50:27,518 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 375 transitions. [2025-02-06 19:50:27,520 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 238 [2025-02-06 19:50:27,523 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:27,523 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:27,524 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,524 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,524 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:27,525 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:27,525 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,525 INFO L85 PathProgramCache]: Analyzing trace with hash -1005946225, now seen corresponding path program 2 times [2025-02-06 19:50:27,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1492455503] [2025-02-06 19:50:27,525 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:27,525 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,534 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,539 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,539 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:27,539 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,539 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:27,544 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,546 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,550 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,551 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:27,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,560 INFO L85 PathProgramCache]: Analyzing trace with hash -364457569, now seen corresponding path program 1 times [2025-02-06 19:50:27,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144513202] [2025-02-06 19:50:27,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,570 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:50:27,578 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:50:27,578 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144513202] [2025-02-06 19:50:27,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144513202] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:27,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026628286] [2025-02-06 19:50:27,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,639 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:27,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,640 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:27,640 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:27,640 INFO L87 Difference]: Start difference. First operand 270 states and 375 transitions. cyclomatic complexity: 107 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,691 INFO L93 Difference]: Finished difference Result 276 states and 378 transitions. [2025-02-06 19:50:27,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 276 states and 378 transitions. [2025-02-06 19:50:27,696 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 244 [2025-02-06 19:50:27,698 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 276 states to 276 states and 378 transitions. [2025-02-06 19:50:27,699 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 276 [2025-02-06 19:50:27,699 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 276 [2025-02-06 19:50:27,700 INFO L73 IsDeterministic]: Start isDeterministic. Operand 276 states and 378 transitions. [2025-02-06 19:50:27,700 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 276 states and 378 transitions. [2025-02-06 19:50:27,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states and 378 transitions. [2025-02-06 19:50:27,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 276. [2025-02-06 19:50:27,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 276 states, 276 states have (on average 1.3695652173913044) internal successors, (378), 275 states have internal predecessors, (378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 276 states to 276 states and 378 transitions. [2025-02-06 19:50:27,714 INFO L240 hiAutomatonCegarLoop]: Abstraction has 276 states and 378 transitions. [2025-02-06 19:50:27,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:27,719 INFO L432 stractBuchiCegarLoop]: Abstraction has 276 states and 378 transitions. [2025-02-06 19:50:27,719 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:50:27,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 276 states and 378 transitions. [2025-02-06 19:50:27,721 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 244 [2025-02-06 19:50:27,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:27,721 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:27,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,724 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:27,724 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret13#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 != start_simulation_~tmp~4#1);" [2025-02-06 19:50:27,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,725 INFO L85 PathProgramCache]: Analyzing trace with hash -1005946225, now seen corresponding path program 3 times [2025-02-06 19:50:27,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558428580] [2025-02-06 19:50:27,725 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:27,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,730 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,734 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,734 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:27,734 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,734 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:27,736 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:27,738 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:27,738 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,738 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,742 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:27,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,742 INFO L85 PathProgramCache]: Analyzing trace with hash -1361529922, now seen corresponding path program 1 times [2025-02-06 19:50:27,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [86975293] [2025-02-06 19:50:27,742 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,743 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,747 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:50:27,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:50:27,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,769 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [86975293] [2025-02-06 19:50:27,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [86975293] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:27,770 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530810216] [2025-02-06 19:50:27,770 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,770 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:27,770 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,770 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:27,770 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:27,770 INFO L87 Difference]: Start difference. First operand 276 states and 378 transitions. cyclomatic complexity: 104 Second operand has 3 states, 3 states have (on average 12.333333333333334) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,796 INFO L93 Difference]: Finished difference Result 377 states and 503 transitions. [2025-02-06 19:50:27,796 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 377 states and 503 transitions. [2025-02-06 19:50:27,799 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 341 [2025-02-06 19:50:27,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 377 states to 377 states and 503 transitions. [2025-02-06 19:50:27,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 377 [2025-02-06 19:50:27,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 377 [2025-02-06 19:50:27,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 377 states and 503 transitions. [2025-02-06 19:50:27,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 377 states and 503 transitions. [2025-02-06 19:50:27,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states and 503 transitions. [2025-02-06 19:50:27,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 377. [2025-02-06 19:50:27,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 377 states, 377 states have (on average 1.3342175066312998) internal successors, (503), 376 states have internal predecessors, (503), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 503 transitions. [2025-02-06 19:50:27,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 377 states and 503 transitions. [2025-02-06 19:50:27,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:27,813 INFO L432 stractBuchiCegarLoop]: Abstraction has 377 states and 503 transitions. [2025-02-06 19:50:27,813 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:50:27,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 377 states and 503 transitions. [2025-02-06 19:50:27,815 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 341 [2025-02-06 19:50:27,815 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:27,815 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:27,816 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,816 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:27,816 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:27,816 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume !(0 == ~c_dr_st~0);" [2025-02-06 19:50:27,817 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,817 INFO L85 PathProgramCache]: Analyzing trace with hash -346675986, now seen corresponding path program 1 times [2025-02-06 19:50:27,817 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,817 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591759407] [2025-02-06 19:50:27,817 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,817 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,822 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:27,826 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:27,826 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,826 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,826 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:27,829 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:27,831 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:27,831 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,831 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,838 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:27,841 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,841 INFO L85 PathProgramCache]: Analyzing trace with hash 928100209, now seen corresponding path program 1 times [2025-02-06 19:50:27,841 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [146297115] [2025-02-06 19:50:27,841 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,843 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:27,844 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:27,849 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,850 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:27,850 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:27,851 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:27,851 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,851 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:27,852 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:27,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:27,853 INFO L85 PathProgramCache]: Analyzing trace with hash 681690404, now seen corresponding path program 1 times [2025-02-06 19:50:27,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:27,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [786430622] [2025-02-06 19:50:27,853 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:27,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:27,860 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:50:27,864 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:50:27,864 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:27,864 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:27,894 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:27,894 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:27,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [786430622] [2025-02-06 19:50:27,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [786430622] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:27,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:27,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:27,895 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1595047819] [2025-02-06 19:50:27,895 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:27,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:27,948 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:27,948 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:27,948 INFO L87 Difference]: Start difference. First operand 377 states and 503 transitions. cyclomatic complexity: 130 Second operand has 3 states, 2 states have (on average 18.5) internal successors, (37), 3 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,973 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:27,973 INFO L93 Difference]: Finished difference Result 525 states and 683 transitions. [2025-02-06 19:50:27,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 525 states and 683 transitions. [2025-02-06 19:50:27,977 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2025-02-06 19:50:27,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 525 states to 525 states and 683 transitions. [2025-02-06 19:50:27,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 525 [2025-02-06 19:50:27,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 525 [2025-02-06 19:50:27,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 525 states and 683 transitions. [2025-02-06 19:50:27,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:27,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 525 states and 683 transitions. [2025-02-06 19:50:27,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states and 683 transitions. [2025-02-06 19:50:27,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 525. [2025-02-06 19:50:27,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 525 states, 525 states have (on average 1.3009523809523809) internal successors, (683), 524 states have internal predecessors, (683), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:27,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 683 transitions. [2025-02-06 19:50:27,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 525 states and 683 transitions. [2025-02-06 19:50:27,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:27,997 INFO L432 stractBuchiCegarLoop]: Abstraction has 525 states and 683 transitions. [2025-02-06 19:50:27,998 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:50:27,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 525 states and 683 transitions. [2025-02-06 19:50:28,000 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 488 [2025-02-06 19:50:28,000 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:28,000 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:28,003 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:28,003 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:28,003 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(19, 2);call #Ultimate.allocInit(12, 3);~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:28,003 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp___0~2#1);" [2025-02-06 19:50:28,004 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:28,004 INFO L85 PathProgramCache]: Analyzing trace with hash -346675986, now seen corresponding path program 2 times [2025-02-06 19:50:28,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:28,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [492471573] [2025-02-06 19:50:28,004 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:28,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:28,011 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:28,016 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:28,016 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:28,016 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,016 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:28,018 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:28,024 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:28,024 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,024 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,031 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:28,031 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:28,031 INFO L85 PathProgramCache]: Analyzing trace with hash -1293664519, now seen corresponding path program 1 times [2025-02-06 19:50:28,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:28,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542859247] [2025-02-06 19:50:28,032 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:28,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:28,034 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:28,038 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:28,039 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,039 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,039 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:28,040 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:28,041 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:28,041 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,041 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,043 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:28,043 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:28,044 INFO L85 PathProgramCache]: Analyzing trace with hash -342433882, now seen corresponding path program 1 times [2025-02-06 19:50:28,044 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:28,044 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246640831] [2025-02-06 19:50:28,044 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:28,044 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:28,049 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-02-06 19:50:28,053 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-02-06 19:50:28,054 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,054 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:28,057 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-02-06 19:50:28,059 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-02-06 19:50:28,059 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,059 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:28,748 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:28,753 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:28,753 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,753 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,753 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:28,761 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:28,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:28,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:28,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:28,860 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:50:28 BoogieIcfgContainer [2025-02-06 19:50:28,863 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:50:28,864 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:50:28,864 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:50:28,864 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:50:28,867 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:26" (3/4) ... [2025-02-06 19:50:28,869 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:50:28,964 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:50:28,965 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:50:28,965 INFO L158 Benchmark]: Toolchain (without parser) took 3517.84ms. Allocated memory is still 142.6MB. Free memory was 114.1MB in the beginning and 108.7MB in the end (delta: 5.4MB). Peak memory consumption was 79.6MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,966 INFO L158 Benchmark]: CDTParser took 0.16ms. Allocated memory is still 201.3MB. Free memory is still 124.4MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:28,966 INFO L158 Benchmark]: CACSL2BoogieTranslator took 227.10ms. Allocated memory is still 142.6MB. Free memory was 114.1MB in the beginning and 101.3MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,966 INFO L158 Benchmark]: Boogie Procedure Inliner took 32.75ms. Allocated memory is still 142.6MB. Free memory was 101.3MB in the beginning and 99.5MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,966 INFO L158 Benchmark]: Boogie Preprocessor took 31.28ms. Allocated memory is still 142.6MB. Free memory was 99.5MB in the beginning and 97.9MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:28,967 INFO L158 Benchmark]: IcfgBuilder took 415.83ms. Allocated memory is still 142.6MB. Free memory was 97.9MB in the beginning and 77.5MB in the end (delta: 20.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,967 INFO L158 Benchmark]: BuchiAutomizer took 2703.61ms. Allocated memory is still 142.6MB. Free memory was 77.5MB in the beginning and 46.6MB in the end (delta: 30.9MB). Peak memory consumption was 32.5MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,967 INFO L158 Benchmark]: Witness Printer took 100.67ms. Allocated memory is still 142.6MB. Free memory was 46.6MB in the beginning and 108.7MB in the end (delta: -62.1MB). Peak memory consumption was 13.6MB. Max. memory is 16.1GB. [2025-02-06 19:50:28,969 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.16ms. Allocated memory is still 201.3MB. Free memory is still 124.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 227.10ms. Allocated memory is still 142.6MB. Free memory was 114.1MB in the beginning and 101.3MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 32.75ms. Allocated memory is still 142.6MB. Free memory was 101.3MB in the beginning and 99.5MB in the end (delta: 1.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 31.28ms. Allocated memory is still 142.6MB. Free memory was 99.5MB in the beginning and 97.9MB in the end (delta: 1.5MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 415.83ms. Allocated memory is still 142.6MB. Free memory was 97.9MB in the beginning and 77.5MB in the end (delta: 20.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 2703.61ms. Allocated memory is still 142.6MB. Free memory was 77.5MB in the beginning and 46.6MB in the end (delta: 30.9MB). Peak memory consumption was 32.5MB. Max. memory is 16.1GB. * Witness Printer took 100.67ms. Allocated memory is still 142.6MB. Free memory was 46.6MB in the beginning and 108.7MB in the end (delta: -62.1MB). Peak memory consumption was 13.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 8 terminating modules (8 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.8 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 525 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.5s and 9 iterations. TraceHistogramMax:1. Analysis of lassos took 1.9s. Construction of modules took 0.1s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 8. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 8 MinimizatonAttempts, 79 StatesRemovedByMinimization, 3 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 794 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 794 mSDsluCounter, 2203 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1148 mSDsCounter, 36 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 117 IncrementalHoareTripleChecker+Invalid, 153 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 36 mSolverCounterUnsat, 1055 mSDtfsCounter, 117 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI4 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 339]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 339]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int q_buf_0 ; [L26] int q_free ; [L27] int q_read_ev ; [L28] int q_write_ev ; [L29] int q_req_up ; [L30] int q_ev ; [L51] int p_num_write ; [L52] int p_last_write ; [L53] int p_dw_st ; [L54] int p_dw_pc ; [L55] int p_dw_i ; [L56] int c_num_read ; [L57] int c_last_read ; [L58] int c_dr_st ; [L59] int c_dr_pc ; [L60] int c_dr_i ; [L164] static int a_t ; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0] [L466] int __retres1 ; [L470] CALL init_model() [L452] q_free = 1 [L453] q_write_ev = 2 [L454] q_read_ev = q_write_ev [L455] p_num_write = 0 [L456] p_dw_pc = 0 [L457] p_dw_i = 1 [L458] c_num_read = 0 [L459] c_dr_pc = 0 [L460] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L470] RET init_model() [L471] CALL start_simulation() [L406] int kernel_st ; [L407] int tmp ; [L411] kernel_st = 0 [L412] CALL update_channels() [L222] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L412] RET update_channels() [L413] CALL init_threads() [L237] COND TRUE (int )p_dw_i == 1 [L238] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L242] COND TRUE (int )c_dr_i == 1 [L243] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L413] RET init_threads() [L414] CALL fire_delta_events() [L275] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L280] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L414] RET fire_delta_events() [L415] CALL activate_threads() [L308] int tmp ; [L309] int tmp___0 ; [L313] CALL, EXPR is_do_write_p_triggered() [L62] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L65] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L75] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L77] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L313] RET, EXPR is_do_write_p_triggered() [L313] tmp = is_do_write_p_triggered() [L315] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] CALL, EXPR is_do_read_c_triggered() [L81] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L84] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L94] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L96] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L321] RET, EXPR is_do_read_c_triggered() [L321] tmp___0 = is_do_read_c_triggered() [L323] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L415] RET activate_threads() [L416] CALL reset_delta_events() [L293] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L298] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L416] RET reset_delta_events() [L419] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] [L422] kernel_st = 1 [L423] CALL eval() [L333] int tmp ; [L334] int tmp___0 ; [L335] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2] Loop: [L339] COND TRUE 1 [L342] CALL, EXPR exists_runnable_thread() [L252] int __retres1 ; [L255] COND TRUE (int )p_dw_st == 0 [L256] __retres1 = 1 [L268] return (__retres1); [L342] RET, EXPR exists_runnable_thread() [L342] tmp___1 = exists_runnable_thread() [L344] COND TRUE \read(tmp___1) [L349] COND TRUE (int )p_dw_st == 0 [L351] tmp = __VERIFIER_nondet_int() [L353] COND FALSE !(\read(tmp)) [L364] COND TRUE (int )c_dr_st == 0 [L366] tmp___0 = __VERIFIER_nondet_int() [L368] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:50:28,988 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)