./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:50:29,749 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:50:29,828 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:50:29,833 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:50:29,833 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:50:29,833 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:50:29,851 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:50:29,852 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:50:29,852 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:50:29,853 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:50:29,853 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:50:29,853 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:50:29,853 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:50:29,853 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:50:29,854 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:50:29,854 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:50:29,854 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:50:29,855 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:50:29,856 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:50:29,856 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:50:29,856 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:50:29,856 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2025-02-06 19:50:30,151 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:50:30,162 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:50:30,165 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:50:30,166 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:50:30,167 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:50:30,168 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2025-02-06 19:50:31,466 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/edf88d394/35fee0af1572452897447edee72f6986/FLAG050d15b50 [2025-02-06 19:50:31,702 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:50:31,703 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2025-02-06 19:50:31,711 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/edf88d394/35fee0af1572452897447edee72f6986/FLAG050d15b50 [2025-02-06 19:50:31,724 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/edf88d394/35fee0af1572452897447edee72f6986 [2025-02-06 19:50:31,726 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:50:31,727 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:50:31,728 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:31,728 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:50:31,731 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:50:31,734 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:31" (1/1) ... [2025-02-06 19:50:31,735 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@27194523 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:31, skipping insertion in model container [2025-02-06 19:50:31,735 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:31" (1/1) ... [2025-02-06 19:50:31,762 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:50:31,953 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:31,968 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:50:32,012 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:32,033 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:50:32,034 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32 WrapperNode [2025-02-06 19:50:32,034 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:32,035 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:32,035 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:50:32,035 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:50:32,041 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,054 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,085 INFO L138 Inliner]: procedures = 31, calls = 36, calls flagged for inlining = 31, calls inlined = 35, statements flattened = 398 [2025-02-06 19:50:32,085 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:32,086 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:50:32,086 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:50:32,086 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:50:32,095 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,096 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,099 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,124 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:50:32,124 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,124 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,134 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,135 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,138 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,139 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,140 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:50:32,144 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:50:32,144 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:50:32,144 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:50:32,145 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,157 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:32,168 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:32,182 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:32,185 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:50:32,209 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:50:32,209 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:50:32,209 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:50:32,209 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:50:32,275 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:50:32,277 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:50:32,635 INFO L1309 $ProcedureCfgBuilder]: dead code at ProgramPoint L217: do_read_c_~a~0#1 := ~a_t~0; [2025-02-06 19:50:32,636 INFO L1309 $ProcedureCfgBuilder]: dead code at ProgramPoint L218: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2025-02-06 19:50:32,636 INFO L1309 $ProcedureCfgBuilder]: dead code at ProgramPoint L218: assume !(1 == ~q_free~0); [2025-02-06 19:50:32,671 INFO L? ?]: Removed 54 outVars from TransFormulas that were not future-live. [2025-02-06 19:50:32,672 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:50:32,687 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:50:32,687 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:50:32,687 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:32 BoogieIcfgContainer [2025-02-06 19:50:32,687 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:50:32,688 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:50:32,688 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:50:32,694 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:50:32,694 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:32,695 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:31" (1/3) ... [2025-02-06 19:50:32,696 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@236c0c2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:32, skipping insertion in model container [2025-02-06 19:50:32,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:32,697 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (2/3) ... [2025-02-06 19:50:32,698 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@236c0c2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:32, skipping insertion in model container [2025-02-06 19:50:32,698 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:32,698 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:32" (3/3) ... [2025-02-06 19:50:32,700 INFO L363 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2025-02-06 19:50:32,748 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:50:32,748 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:50:32,748 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:50:32,748 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:50:32,748 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:50:32,749 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:50:32,749 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:50:32,749 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:50:32,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 147 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 146 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:32,781 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2025-02-06 19:50:32,781 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:32,781 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:32,791 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:32,791 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:32,791 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:50:32,793 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 147 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 146 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:32,799 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2025-02-06 19:50:32,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:32,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:32,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:32,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:32,810 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:32,811 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume !true;" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:32,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:32,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1859495649, now seen corresponding path program 1 times [2025-02-06 19:50:32,827 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:32,827 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1229558048] [2025-02-06 19:50:32,827 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:32,828 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:32,895 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:32,915 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:32,915 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:32,915 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,040 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,041 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,042 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1229558048] [2025-02-06 19:50:33,043 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1229558048] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,043 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,043 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:33,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1176294274] [2025-02-06 19:50:33,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,049 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:33,050 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,050 INFO L85 PathProgramCache]: Analyzing trace with hash 1524693563, now seen corresponding path program 1 times [2025-02-06 19:50:33,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1074609654] [2025-02-06 19:50:33,051 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,063 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:50:33,069 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:50:33,069 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,069 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1074609654] [2025-02-06 19:50:33,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1074609654] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:33,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2112982419] [2025-02-06 19:50:33,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,093 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,095 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,120 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:33,121 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:33,123 INFO L87 Difference]: Start difference. First operand has 147 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 146 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,148 INFO L93 Difference]: Finished difference Result 143 states and 209 transitions. [2025-02-06 19:50:33,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 143 states and 209 transitions. [2025-02-06 19:50:33,158 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:50:33,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 143 states to 136 states and 202 transitions. [2025-02-06 19:50:33,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2025-02-06 19:50:33,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2025-02-06 19:50:33,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 202 transitions. [2025-02-06 19:50:33,166 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,166 INFO L218 hiAutomatonCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-02-06 19:50:33,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 202 transitions. [2025-02-06 19:50:33,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2025-02-06 19:50:33,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.4852941176470589) internal successors, (202), 135 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 202 transitions. [2025-02-06 19:50:33,204 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-02-06 19:50:33,205 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:33,208 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-02-06 19:50:33,208 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:50:33,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 202 transitions. [2025-02-06 19:50:33,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:50:33,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,212 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:33,212 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:33,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,213 INFO L85 PathProgramCache]: Analyzing trace with hash -2070846562, now seen corresponding path program 1 times [2025-02-06 19:50:33,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612494326] [2025-02-06 19:50:33,214 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:33,230 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:33,230 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612494326] [2025-02-06 19:50:33,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612494326] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:33,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934659279] [2025-02-06 19:50:33,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,278 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:33,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1296593156, now seen corresponding path program 1 times [2025-02-06 19:50:33,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192707857] [2025-02-06 19:50:33,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,310 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:33,324 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:33,324 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,324 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,399 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,399 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,399 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1192707857] [2025-02-06 19:50:33,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1192707857] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:33,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554547095] [2025-02-06 19:50:33,400 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,400 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,400 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,400 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:33,400 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:33,401 INFO L87 Difference]: Start difference. First operand 136 states and 202 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,418 INFO L93 Difference]: Finished difference Result 136 states and 201 transitions. [2025-02-06 19:50:33,418 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 136 states and 201 transitions. [2025-02-06 19:50:33,419 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:50:33,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 136 states to 136 states and 201 transitions. [2025-02-06 19:50:33,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2025-02-06 19:50:33,421 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2025-02-06 19:50:33,421 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 201 transitions. [2025-02-06 19:50:33,422 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,422 INFO L218 hiAutomatonCegarLoop]: Abstraction has 136 states and 201 transitions. [2025-02-06 19:50:33,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 201 transitions. [2025-02-06 19:50:33,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2025-02-06 19:50:33,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.4779411764705883) internal successors, (201), 135 states have internal predecessors, (201), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,427 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 201 transitions. [2025-02-06 19:50:33,427 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 201 transitions. [2025-02-06 19:50:33,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:33,428 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 201 transitions. [2025-02-06 19:50:33,428 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:50:33,429 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 201 transitions. [2025-02-06 19:50:33,432 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:50:33,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,435 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,435 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,435 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:33,435 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:33,438 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,438 INFO L85 PathProgramCache]: Analyzing trace with hash -1662022337, now seen corresponding path program 1 times [2025-02-06 19:50:33,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124355757] [2025-02-06 19:50:33,439 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,445 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:50:33,457 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:50:33,458 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,458 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,517 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124355757] [2025-02-06 19:50:33,517 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124355757] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,517 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:33,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [330733990] [2025-02-06 19:50:33,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,517 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:33,518 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1296593156, now seen corresponding path program 2 times [2025-02-06 19:50:33,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901223435] [2025-02-06 19:50:33,518 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:33,518 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,532 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:33,538 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:33,542 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:33,543 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,596 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901223435] [2025-02-06 19:50:33,596 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901223435] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,596 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,596 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:33,596 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663181468] [2025-02-06 19:50:33,596 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,597 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,597 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,597 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:33,597 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:33,597 INFO L87 Difference]: Start difference. First operand 136 states and 201 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,651 INFO L93 Difference]: Finished difference Result 225 states and 323 transitions. [2025-02-06 19:50:33,651 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 323 transitions. [2025-02-06 19:50:33,653 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2025-02-06 19:50:33,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 323 transitions. [2025-02-06 19:50:33,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2025-02-06 19:50:33,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2025-02-06 19:50:33,658 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 323 transitions. [2025-02-06 19:50:33,659 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,660 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 323 transitions. [2025-02-06 19:50:33,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 323 transitions. [2025-02-06 19:50:33,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 222. [2025-02-06 19:50:33,673 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 222 states, 222 states have (on average 1.4414414414414414) internal successors, (320), 221 states have internal predecessors, (320), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 320 transitions. [2025-02-06 19:50:33,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 222 states and 320 transitions. [2025-02-06 19:50:33,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:33,681 INFO L432 stractBuchiCegarLoop]: Abstraction has 222 states and 320 transitions. [2025-02-06 19:50:33,681 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:50:33,682 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 222 states and 320 transitions. [2025-02-06 19:50:33,683 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 187 [2025-02-06 19:50:33,683 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,683 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,686 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,686 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,687 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:33,687 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:33,687 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,687 INFO L85 PathProgramCache]: Analyzing trace with hash -619888774, now seen corresponding path program 1 times [2025-02-06 19:50:33,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,688 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [330667567] [2025-02-06 19:50:33,688 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,688 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,693 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:50:33,701 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:50:33,701 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,701 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,766 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [330667567] [2025-02-06 19:50:33,766 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [330667567] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,766 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:33,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1132442268] [2025-02-06 19:50:33,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,766 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:33,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,767 INFO L85 PathProgramCache]: Analyzing trace with hash -387989650, now seen corresponding path program 1 times [2025-02-06 19:50:33,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889386914] [2025-02-06 19:50:33,767 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,775 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:33,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:33,780 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,780 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [889386914] [2025-02-06 19:50:33,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [889386914] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:33,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [885507328] [2025-02-06 19:50:33,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,828 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,828 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,828 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:33,828 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:33,828 INFO L87 Difference]: Start difference. First operand 222 states and 320 transitions. cyclomatic complexity: 100 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,956 INFO L93 Difference]: Finished difference Result 479 states and 681 transitions. [2025-02-06 19:50:33,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 681 transitions. [2025-02-06 19:50:33,962 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 431 [2025-02-06 19:50:33,966 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 681 transitions. [2025-02-06 19:50:33,966 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2025-02-06 19:50:33,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2025-02-06 19:50:33,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 681 transitions. [2025-02-06 19:50:33,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 479 states and 681 transitions. [2025-02-06 19:50:33,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 681 transitions. [2025-02-06 19:50:33,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 381. [2025-02-06 19:50:33,994 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 381 states have (on average 1.4330708661417322) internal successors, (546), 380 states have internal predecessors, (546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,996 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 546 transitions. [2025-02-06 19:50:33,996 INFO L240 hiAutomatonCegarLoop]: Abstraction has 381 states and 546 transitions. [2025-02-06 19:50:33,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:33,997 INFO L432 stractBuchiCegarLoop]: Abstraction has 381 states and 546 transitions. [2025-02-06 19:50:33,997 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:50:33,997 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 381 states and 546 transitions. [2025-02-06 19:50:33,999 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 346 [2025-02-06 19:50:33,999 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,999 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,001 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume 2 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:34,001 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume 2 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:34,001 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1634102593, now seen corresponding path program 1 times [2025-02-06 19:50:34,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87133389] [2025-02-06 19:50:34,001 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,010 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,015 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,015 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,015 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,067 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,068 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,068 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87133389] [2025-02-06 19:50:34,068 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87133389] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,068 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,068 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:34,068 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1417906104] [2025-02-06 19:50:34,068 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,068 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:34,069 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,069 INFO L85 PathProgramCache]: Analyzing trace with hash 1635016000, now seen corresponding path program 1 times [2025-02-06 19:50:34,069 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1258666622] [2025-02-06 19:50:34,069 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,079 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-06 19:50:34,084 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-06 19:50:34,084 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,084 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,149 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,149 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1258666622] [2025-02-06 19:50:34,149 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1258666622] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,149 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,149 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:34,149 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304367760] [2025-02-06 19:50:34,149 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,150 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,150 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:34,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:34,150 INFO L87 Difference]: Start difference. First operand 381 states and 546 transitions. cyclomatic complexity: 167 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,234 INFO L93 Difference]: Finished difference Result 562 states and 774 transitions. [2025-02-06 19:50:34,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 562 states and 774 transitions. [2025-02-06 19:50:34,238 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-02-06 19:50:34,241 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 562 states to 562 states and 774 transitions. [2025-02-06 19:50:34,241 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 562 [2025-02-06 19:50:34,242 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 562 [2025-02-06 19:50:34,242 INFO L73 IsDeterministic]: Start isDeterministic. Operand 562 states and 774 transitions. [2025-02-06 19:50:34,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 562 states and 774 transitions. [2025-02-06 19:50:34,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 562 states and 774 transitions. [2025-02-06 19:50:34,256 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 562 to 556. [2025-02-06 19:50:34,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 556 states have (on average 1.381294964028777) internal successors, (768), 555 states have internal predecessors, (768), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 768 transitions. [2025-02-06 19:50:34,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 556 states and 768 transitions. [2025-02-06 19:50:34,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:34,261 INFO L432 stractBuchiCegarLoop]: Abstraction has 556 states and 768 transitions. [2025-02-06 19:50:34,261 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:50:34,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 556 states and 768 transitions. [2025-02-06 19:50:34,266 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-02-06 19:50:34,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,267 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,267 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,267 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:34,267 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:34,268 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,268 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 1 times [2025-02-06 19:50:34,268 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,268 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [493908620] [2025-02-06 19:50:34,268 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,268 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,276 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,280 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,280 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,285 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,289 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,289 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,315 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,316 INFO L85 PathProgramCache]: Analyzing trace with hash -2133503965, now seen corresponding path program 1 times [2025-02-06 19:50:34,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413844691] [2025-02-06 19:50:34,316 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,322 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-06 19:50:34,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-06 19:50:34,329 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [413844691] [2025-02-06 19:50:34,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [413844691] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:34,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1224131895] [2025-02-06 19:50:34,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,389 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,389 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,389 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:34,389 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:34,390 INFO L87 Difference]: Start difference. First operand 556 states and 768 transitions. cyclomatic complexity: 216 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,444 INFO L93 Difference]: Finished difference Result 598 states and 810 transitions. [2025-02-06 19:50:34,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 598 states and 810 transitions. [2025-02-06 19:50:34,449 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2025-02-06 19:50:34,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 598 states to 598 states and 810 transitions. [2025-02-06 19:50:34,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 598 [2025-02-06 19:50:34,454 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 598 [2025-02-06 19:50:34,454 INFO L73 IsDeterministic]: Start isDeterministic. Operand 598 states and 810 transitions. [2025-02-06 19:50:34,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 598 states and 810 transitions. [2025-02-06 19:50:34,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states and 810 transitions. [2025-02-06 19:50:34,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 574. [2025-02-06 19:50:34,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.3693379790940767) internal successors, (786), 573 states have internal predecessors, (786), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 786 transitions. [2025-02-06 19:50:34,468 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 786 transitions. [2025-02-06 19:50:34,468 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:34,469 INFO L432 stractBuchiCegarLoop]: Abstraction has 574 states and 786 transitions. [2025-02-06 19:50:34,471 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:50:34,471 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 786 transitions. [2025-02-06 19:50:34,474 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 511 [2025-02-06 19:50:34,475 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,475 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,475 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,477 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,477 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:34,478 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:34,478 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,478 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 2 times [2025-02-06 19:50:34,478 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [479904445] [2025-02-06 19:50:34,478 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:34,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,484 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,489 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,489 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:34,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,489 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,491 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,495 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,497 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,497 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,504 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,505 INFO L85 PathProgramCache]: Analyzing trace with hash 531232814, now seen corresponding path program 1 times [2025-02-06 19:50:34,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [934910996] [2025-02-06 19:50:34,505 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,511 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,515 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,515 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,515 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,568 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [934910996] [2025-02-06 19:50:34,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [934910996] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:50:34,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1679933947] [2025-02-06 19:50:34,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,571 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,571 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,572 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:50:34,572 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:50:34,572 INFO L87 Difference]: Start difference. First operand 574 states and 786 transitions. cyclomatic complexity: 216 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,628 INFO L93 Difference]: Finished difference Result 592 states and 796 transitions. [2025-02-06 19:50:34,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 796 transitions. [2025-02-06 19:50:34,632 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2025-02-06 19:50:34,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 796 transitions. [2025-02-06 19:50:34,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2025-02-06 19:50:34,636 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2025-02-06 19:50:34,636 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 796 transitions. [2025-02-06 19:50:34,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 796 transitions. [2025-02-06 19:50:34,638 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 796 transitions. [2025-02-06 19:50:34,649 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 592. [2025-02-06 19:50:34,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 592 states, 592 states have (on average 1.3445945945945945) internal successors, (796), 591 states have internal predecessors, (796), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,652 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 592 states and 796 transitions. [2025-02-06 19:50:34,652 INFO L240 hiAutomatonCegarLoop]: Abstraction has 592 states and 796 transitions. [2025-02-06 19:50:34,652 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:34,653 INFO L432 stractBuchiCegarLoop]: Abstraction has 592 states and 796 transitions. [2025-02-06 19:50:34,653 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:50:34,653 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 592 states and 796 transitions. [2025-02-06 19:50:34,656 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2025-02-06 19:50:34,656 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,656 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,656 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,656 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,657 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:50:34,657 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-02-06 19:50:34,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,657 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 3 times [2025-02-06 19:50:34,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [710654845] [2025-02-06 19:50:34,657 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:34,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,663 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,666 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,666 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:34,666 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,666 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,673 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:50:34,675 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:50:34,676 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,676 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,685 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,685 INFO L85 PathProgramCache]: Analyzing trace with hash 464226061, now seen corresponding path program 1 times [2025-02-06 19:50:34,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2084116689] [2025-02-06 19:50:34,685 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,699 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2084116689] [2025-02-06 19:50:34,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2084116689] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,730 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:34,730 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1320471794] [2025-02-06 19:50:34,730 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,730 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,730 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,730 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:34,730 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:34,731 INFO L87 Difference]: Start difference. First operand 592 states and 796 transitions. cyclomatic complexity: 208 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,766 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,767 INFO L93 Difference]: Finished difference Result 813 states and 1069 transitions. [2025-02-06 19:50:34,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 813 states and 1069 transitions. [2025-02-06 19:50:34,772 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 744 [2025-02-06 19:50:34,776 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 813 states to 813 states and 1069 transitions. [2025-02-06 19:50:34,776 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 813 [2025-02-06 19:50:34,777 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 813 [2025-02-06 19:50:34,777 INFO L73 IsDeterministic]: Start isDeterministic. Operand 813 states and 1069 transitions. [2025-02-06 19:50:34,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,778 INFO L218 hiAutomatonCegarLoop]: Abstraction has 813 states and 1069 transitions. [2025-02-06 19:50:34,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 813 states and 1069 transitions. [2025-02-06 19:50:34,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 813 to 813. [2025-02-06 19:50:34,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 813 states, 813 states have (on average 1.3148831488314883) internal successors, (1069), 812 states have internal predecessors, (1069), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,812 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 813 states to 813 states and 1069 transitions. [2025-02-06 19:50:34,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 813 states and 1069 transitions. [2025-02-06 19:50:34,813 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:34,816 INFO L432 stractBuchiCegarLoop]: Abstraction has 813 states and 1069 transitions. [2025-02-06 19:50:34,816 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:50:34,816 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 813 states and 1069 transitions. [2025-02-06 19:50:34,820 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 744 [2025-02-06 19:50:34,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,822 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:34,823 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume !(0 == ~c_dr_st~0);" [2025-02-06 19:50:34,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,824 INFO L85 PathProgramCache]: Analyzing trace with hash 1305611587, now seen corresponding path program 1 times [2025-02-06 19:50:34,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1580164973] [2025-02-06 19:50:34,824 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,829 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:34,831 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:34,833 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,833 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,833 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,835 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:34,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:34,838 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,845 INFO L85 PathProgramCache]: Analyzing trace with hash 2141702457, now seen corresponding path program 1 times [2025-02-06 19:50:34,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833416610] [2025-02-06 19:50:34,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,848 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:34,849 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:34,849 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,849 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,849 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,850 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:50:34,850 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:50:34,850 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,852 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,852 INFO L85 PathProgramCache]: Analyzing trace with hash 1405322807, now seen corresponding path program 1 times [2025-02-06 19:50:34,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2082890857] [2025-02-06 19:50:34,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,857 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:34,859 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:34,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2082890857] [2025-02-06 19:50:34,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2082890857] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:34,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [723420552] [2025-02-06 19:50:34,877 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,930 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,930 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:34,930 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:34,931 INFO L87 Difference]: Start difference. First operand 813 states and 1069 transitions. cyclomatic complexity: 263 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,964 INFO L93 Difference]: Finished difference Result 931 states and 1214 transitions. [2025-02-06 19:50:34,964 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 931 states and 1214 transitions. [2025-02-06 19:50:34,970 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 858 [2025-02-06 19:50:34,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 931 states to 931 states and 1214 transitions. [2025-02-06 19:50:34,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 931 [2025-02-06 19:50:34,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 931 [2025-02-06 19:50:34,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 931 states and 1214 transitions. [2025-02-06 19:50:34,977 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,977 INFO L218 hiAutomatonCegarLoop]: Abstraction has 931 states and 1214 transitions. [2025-02-06 19:50:34,978 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 931 states and 1214 transitions. [2025-02-06 19:50:34,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 931 to 822. [2025-02-06 19:50:34,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 822 states, 822 states have (on average 1.3126520681265206) internal successors, (1079), 821 states have internal predecessors, (1079), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 822 states to 822 states and 1079 transitions. [2025-02-06 19:50:34,992 INFO L240 hiAutomatonCegarLoop]: Abstraction has 822 states and 1079 transitions. [2025-02-06 19:50:34,992 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:34,993 INFO L432 stractBuchiCegarLoop]: Abstraction has 822 states and 1079 transitions. [2025-02-06 19:50:34,993 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:50:34,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 822 states and 1079 transitions. [2025-02-06 19:50:34,997 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 750 [2025-02-06 19:50:34,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,998 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-02-06 19:50:34,998 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp___0~2#1);" [2025-02-06 19:50:34,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1305611587, now seen corresponding path program 2 times [2025-02-06 19:50:34,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835106064] [2025-02-06 19:50:34,999 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:34,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:35,003 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:35,006 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:35,006 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:35,006 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,006 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:35,008 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:35,010 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:35,010 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,010 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,016 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:35,018 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:35,019 INFO L85 PathProgramCache]: Analyzing trace with hash 1968266873, now seen corresponding path program 1 times [2025-02-06 19:50:35,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:35,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680156284] [2025-02-06 19:50:35,019 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:35,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:35,022 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:35,023 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:35,024 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,024 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,024 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:35,025 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:50:35,026 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:50:35,027 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,027 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,029 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:35,033 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:35,033 INFO L85 PathProgramCache]: Analyzing trace with hash 615334203, now seen corresponding path program 1 times [2025-02-06 19:50:35,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:35,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [379871240] [2025-02-06 19:50:35,033 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:35,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:35,041 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:35,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:35,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,044 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:35,046 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:35,048 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:35,048 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,052 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:35,843 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:35,848 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:35,848 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,848 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,848 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:35,857 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:50:35,861 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:50:35,862 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:35,862 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:35,985 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:50:35 BoogieIcfgContainer [2025-02-06 19:50:35,985 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:50:35,986 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:50:35,986 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:50:35,986 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:50:35,987 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:32" (3/4) ... [2025-02-06 19:50:35,992 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:50:36,054 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:50:36,054 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:50:36,057 INFO L158 Benchmark]: Toolchain (without parser) took 4327.48ms. Allocated memory is still 142.6MB. Free memory was 112.8MB in the beginning and 93.3MB in the end (delta: 19.5MB). Peak memory consumption was 18.2MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,057 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 226.5MB. Free memory is still 147.7MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:36,057 INFO L158 Benchmark]: CACSL2BoogieTranslator took 306.68ms. Allocated memory is still 142.6MB. Free memory was 112.8MB in the beginning and 99.1MB in the end (delta: 13.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,057 INFO L158 Benchmark]: Boogie Procedure Inliner took 50.05ms. Allocated memory is still 142.6MB. Free memory was 99.1MB in the beginning and 97.2MB in the end (delta: 2.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,058 INFO L158 Benchmark]: Boogie Preprocessor took 57.77ms. Allocated memory is still 142.6MB. Free memory was 97.2MB in the beginning and 95.2MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:50:36,058 INFO L158 Benchmark]: IcfgBuilder took 543.25ms. Allocated memory is still 142.6MB. Free memory was 95.2MB in the beginning and 70.1MB in the end (delta: 25.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,059 INFO L158 Benchmark]: BuchiAutomizer took 3297.44ms. Allocated memory is still 142.6MB. Free memory was 70.1MB in the beginning and 98.8MB in the end (delta: -28.7MB). Peak memory consumption was 43.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,060 INFO L158 Benchmark]: Witness Printer took 68.03ms. Allocated memory is still 142.6MB. Free memory was 98.8MB in the beginning and 93.3MB in the end (delta: 5.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:50:36,061 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 226.5MB. Free memory is still 147.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 306.68ms. Allocated memory is still 142.6MB. Free memory was 112.8MB in the beginning and 99.1MB in the end (delta: 13.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 50.05ms. Allocated memory is still 142.6MB. Free memory was 99.1MB in the beginning and 97.2MB in the end (delta: 2.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 57.77ms. Allocated memory is still 142.6MB. Free memory was 97.2MB in the beginning and 95.2MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 543.25ms. Allocated memory is still 142.6MB. Free memory was 95.2MB in the beginning and 70.1MB in the end (delta: 25.0MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 3297.44ms. Allocated memory is still 142.6MB. Free memory was 70.1MB in the beginning and 98.8MB in the end (delta: -28.7MB). Peak memory consumption was 43.4MB. Max. memory is 16.1GB. * Witness Printer took 68.03ms. Allocated memory is still 142.6MB. Free memory was 98.8MB in the beginning and 93.3MB in the end (delta: 5.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 822 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.1s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 2.2s. Construction of modules took 0.2s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.2s AutomataMinimizationTime, 9 MinimizatonAttempts, 240 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1515 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1515 mSDsluCounter, 3376 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1742 mSDsCounter, 73 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 241 IncrementalHoareTripleChecker+Invalid, 314 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 73 mSolverCounterUnsat, 1634 mSDtfsCounter, 241 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:50:36,079 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)