./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pipeline.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pipeline.cil-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:50:30,157 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:50:30,193 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:50:30,196 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:50:30,196 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:50:30,196 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:50:30,210 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:50:30,210 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:50:30,211 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:50:30,211 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:50:30,211 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:50:30,211 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:50:30,211 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:50:30,212 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:50:30,212 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:50:30,212 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:50:30,213 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:50:30,213 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 [2025-02-06 19:50:30,535 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:50:30,550 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:50:30,556 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:50:30,557 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:50:30,561 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:50:30,562 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pipeline.cil-2.c [2025-02-06 19:50:31,802 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c4fecb0b6/51539e82a6b546359974dfe0464466aa/FLAGaeb3bd9de [2025-02-06 19:50:32,078 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:50:32,084 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-2.c [2025-02-06 19:50:32,103 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c4fecb0b6/51539e82a6b546359974dfe0464466aa/FLAGaeb3bd9de [2025-02-06 19:50:32,142 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/c4fecb0b6/51539e82a6b546359974dfe0464466aa [2025-02-06 19:50:32,144 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:50:32,145 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:50:32,147 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:32,150 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:50:32,153 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:50:32,154 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,154 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@64c2629d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32, skipping insertion in model container [2025-02-06 19:50:32,154 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,180 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:50:32,340 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:32,355 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:50:32,407 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:50:32,424 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:50:32,424 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32 WrapperNode [2025-02-06 19:50:32,425 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:50:32,425 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:32,426 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:50:32,426 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:50:32,430 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,438 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,461 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1031 [2025-02-06 19:50:32,462 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:50:32,462 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:50:32,462 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:50:32,462 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:50:32,468 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,469 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,471 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,482 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:50:32,483 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,483 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,491 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,492 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,494 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,495 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,497 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:50:32,497 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:50:32,497 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:50:32,498 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:50:32,498 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (1/1) ... [2025-02-06 19:50:32,502 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:32,511 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:32,526 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:32,530 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:50:32,544 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:50:32,545 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:50:32,545 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:50:32,545 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:50:32,609 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:50:32,610 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:50:33,302 INFO L? ?]: Removed 76 outVars from TransFormulas that were not future-live. [2025-02-06 19:50:33,303 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:50:33,315 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:50:33,315 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:50:33,315 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:33 BoogieIcfgContainer [2025-02-06 19:50:33,315 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:50:33,316 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:50:33,316 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:50:33,320 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:50:33,321 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:33,321 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:50:32" (1/3) ... [2025-02-06 19:50:33,321 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da16baa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:33, skipping insertion in model container [2025-02-06 19:50:33,322 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:33,322 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:50:32" (2/3) ... [2025-02-06 19:50:33,322 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@2da16baa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:50:33, skipping insertion in model container [2025-02-06 19:50:33,322 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:50:33,322 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:50:33" (3/3) ... [2025-02-06 19:50:33,323 INFO L363 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-2.c [2025-02-06 19:50:33,378 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:50:33,379 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:50:33,379 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:50:33,379 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:50:33,379 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:50:33,379 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:50:33,379 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:50:33,380 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:50:33,388 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,419 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2025-02-06 19:50:33,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,426 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,427 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,427 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:50:33,428 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,439 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2025-02-06 19:50:33,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,443 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,443 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,449 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-02-06 19:50:33,449 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !true;" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:33,456 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,456 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 1 times [2025-02-06 19:50:33,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1813124138] [2025-02-06 19:50:33,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,516 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:33,545 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:33,547 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,547 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:33,547 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:33,555 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:33,567 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:33,568 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:33,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:33,598 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,598 INFO L85 PathProgramCache]: Analyzing trace with hash 520539416, now seen corresponding path program 1 times [2025-02-06 19:50:33,598 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,599 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [378972168] [2025-02-06 19:50:33,599 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,599 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,605 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:50:33,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:50:33,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,634 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,634 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,634 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [378972168] [2025-02-06 19:50:33,634 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [378972168] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,634 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,634 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:33,635 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175116190] [2025-02-06 19:50:33,635 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,638 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,639 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,656 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-02-06 19:50:33,656 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-02-06 19:50:33,658 INFO L87 Difference]: Start difference. First operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,689 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2025-02-06 19:50:33,691 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2025-02-06 19:50:33,696 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2025-02-06 19:50:33,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2025-02-06 19:50:33,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2025-02-06 19:50:33,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2025-02-06 19:50:33,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2025-02-06 19:50:33,708 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,708 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-02-06 19:50:33,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2025-02-06 19:50:33,736 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2025-02-06 19:50:33,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2025-02-06 19:50:33,739 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-02-06 19:50:33,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-02-06 19:50:33,741 INFO L432 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-02-06 19:50:33,741 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:50:33,741 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2025-02-06 19:50:33,743 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2025-02-06 19:50:33,743 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,743 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,744 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,744 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,745 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-02-06 19:50:33,745 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:33,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 2 times [2025-02-06 19:50:33,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [343139184] [2025-02-06 19:50:33,746 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:33,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,752 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:33,760 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:33,760 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:33,760 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:33,760 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:33,762 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:33,770 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:33,770 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:33,778 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:33,778 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,778 INFO L85 PathProgramCache]: Analyzing trace with hash 16513805, now seen corresponding path program 1 times [2025-02-06 19:50:33,778 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,778 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565562209] [2025-02-06 19:50:33,779 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,779 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:33,787 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:33,788 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565562209] [2025-02-06 19:50:33,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565562209] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,831 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,831 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:33,831 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [743042850] [2025-02-06 19:50:33,831 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:33,831 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:33,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:33,831 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:33,831 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:33,832 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,897 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:33,897 INFO L93 Difference]: Finished difference Result 506 states and 918 transitions. [2025-02-06 19:50:33,897 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 506 states and 918 transitions. [2025-02-06 19:50:33,900 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 433 [2025-02-06 19:50:33,902 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 506 states to 506 states and 918 transitions. [2025-02-06 19:50:33,902 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 506 [2025-02-06 19:50:33,903 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 506 [2025-02-06 19:50:33,903 INFO L73 IsDeterministic]: Start isDeterministic. Operand 506 states and 918 transitions. [2025-02-06 19:50:33,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:33,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-02-06 19:50:33,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states and 918 transitions. [2025-02-06 19:50:33,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2025-02-06 19:50:33,916 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 506 states, 506 states have (on average 1.8142292490118577) internal successors, (918), 505 states have internal predecessors, (918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:33,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 918 transitions. [2025-02-06 19:50:33,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-02-06 19:50:33,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:33,918 INFO L432 stractBuchiCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-02-06 19:50:33,918 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:50:33,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 506 states and 918 transitions. [2025-02-06 19:50:33,920 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 433 [2025-02-06 19:50:33,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:33,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:33,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:33,922 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-02-06 19:50:33,922 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:33,922 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:33,922 INFO L85 PathProgramCache]: Analyzing trace with hash -658770066, now seen corresponding path program 1 times [2025-02-06 19:50:33,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:33,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058810798] [2025-02-06 19:50:33,922 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:33,923 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:33,927 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:33,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:33,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:33,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:33,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:33,999 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:33,999 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058810798] [2025-02-06 19:50:33,999 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058810798] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:33,999 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:33,999 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:33,999 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [431519566] [2025-02-06 19:50:33,999 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,000 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:34,000 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,000 INFO L85 PathProgramCache]: Analyzing trace with hash 1813465164, now seen corresponding path program 1 times [2025-02-06 19:50:34,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1066742329] [2025-02-06 19:50:34,000 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,005 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,014 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,014 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,014 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1066742329] [2025-02-06 19:50:34,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1066742329] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:34,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1530935525] [2025-02-06 19:50:34,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,036 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,037 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:34,037 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:34,037 INFO L87 Difference]: Start difference. First operand 506 states and 918 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,099 INFO L93 Difference]: Finished difference Result 918 states and 1644 transitions. [2025-02-06 19:50:34,099 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 918 states and 1644 transitions. [2025-02-06 19:50:34,104 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 791 [2025-02-06 19:50:34,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 918 states to 918 states and 1644 transitions. [2025-02-06 19:50:34,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 918 [2025-02-06 19:50:34,108 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 918 [2025-02-06 19:50:34,109 INFO L73 IsDeterministic]: Start isDeterministic. Operand 918 states and 1644 transitions. [2025-02-06 19:50:34,110 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,110 INFO L218 hiAutomatonCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-02-06 19:50:34,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 918 states and 1644 transitions. [2025-02-06 19:50:34,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 918 to 918. [2025-02-06 19:50:34,129 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 918 states, 918 states have (on average 1.7908496732026145) internal successors, (1644), 917 states have internal predecessors, (1644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 918 states to 918 states and 1644 transitions. [2025-02-06 19:50:34,131 INFO L240 hiAutomatonCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-02-06 19:50:34,132 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:34,132 INFO L432 stractBuchiCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-02-06 19:50:34,132 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:50:34,132 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 918 states and 1644 transitions. [2025-02-06 19:50:34,136 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 791 [2025-02-06 19:50:34,136 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,136 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,137 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-02-06 19:50:34,137 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:34,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 3 times [2025-02-06 19:50:34,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1017559638] [2025-02-06 19:50:34,142 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:34,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,153 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:34,159 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:34,159 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:34,159 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,159 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,169 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:34,204 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:34,204 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,204 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:34,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,219 INFO L85 PathProgramCache]: Analyzing trace with hash 47533612, now seen corresponding path program 1 times [2025-02-06 19:50:34,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [522996139] [2025-02-06 19:50:34,219 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,226 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,233 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,233 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,233 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [522996139] [2025-02-06 19:50:34,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [522996139] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,272 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:34,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2117768265] [2025-02-06 19:50:34,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,272 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:34,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:34,273 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:34,273 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:34,273 INFO L87 Difference]: Start difference. First operand 918 states and 1644 transitions. cyclomatic complexity: 728 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:34,466 INFO L93 Difference]: Finished difference Result 1140 states and 1974 transitions. [2025-02-06 19:50:34,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1140 states and 1974 transitions. [2025-02-06 19:50:34,474 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 976 [2025-02-06 19:50:34,484 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1140 states to 1140 states and 1974 transitions. [2025-02-06 19:50:34,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1140 [2025-02-06 19:50:34,485 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1140 [2025-02-06 19:50:34,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1140 states and 1974 transitions. [2025-02-06 19:50:34,489 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:34,489 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-02-06 19:50:34,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states and 1974 transitions. [2025-02-06 19:50:34,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 1140. [2025-02-06 19:50:34,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1140 states, 1140 states have (on average 1.731578947368421) internal successors, (1974), 1139 states have internal predecessors, (1974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:34,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1140 states to 1140 states and 1974 transitions. [2025-02-06 19:50:34,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-02-06 19:50:34,528 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:34,529 INFO L432 stractBuchiCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-02-06 19:50:34,529 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:50:34,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1140 states and 1974 transitions. [2025-02-06 19:50:34,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 976 [2025-02-06 19:50:34,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:34,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:34,539 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,539 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:34,539 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" [2025-02-06 19:50:34,539 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:34,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,542 INFO L85 PathProgramCache]: Analyzing trace with hash 968443117, now seen corresponding path program 1 times [2025-02-06 19:50:34,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [857067938] [2025-02-06 19:50:34,542 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,551 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:34,559 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:34,559 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,559 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:34,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:34,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:34,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [857067938] [2025-02-06 19:50:34,628 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [857067938] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:34,628 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:34,628 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:34,628 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755334065] [2025-02-06 19:50:34,628 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:34,628 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:34,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:34,629 INFO L85 PathProgramCache]: Analyzing trace with hash 47532651, now seen corresponding path program 1 times [2025-02-06 19:50:34,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:34,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [674198535] [2025-02-06 19:50:34,629 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:34,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:34,638 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,640 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,640 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,640 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,640 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:34,641 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:34,647 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:34,647 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:34,647 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:34,655 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:35,312 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:35,314 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:35,314 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:35,314 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:35,314 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-02-06 19:50:35,314 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,314 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:35,314 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:35,314 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration5_Loop [2025-02-06 19:50:35,314 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:35,314 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:35,329 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,336 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,341 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,349 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,372 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,376 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,381 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,385 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,400 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,402 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,412 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,414 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,418 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,421 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,425 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,430 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,747 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:35,748 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-02-06 19:50:35,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,750 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:35,752 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:35,754 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-02-06 19:50:35,755 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:35,755 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:35,771 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-02-06 19:50:35,771 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet4#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-02-06 19:50:35,778 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-02-06 19:50:35,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,779 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:35,781 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:35,783 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-02-06 19:50:35,784 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:35,784 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:35,796 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-02-06 19:50:35,796 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-02-06 19:50:35,802 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:35,803 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,803 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:35,806 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:35,807 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-02-06 19:50:35,809 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-02-06 19:50:35,809 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:35,833 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:35,833 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,833 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:35,836 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:35,837 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-02-06 19:50:35,838 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-02-06 19:50:35,838 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-02-06 19:50:35,860 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-02-06 19:50:35,870 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-02-06 19:50:35,871 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:50:35,871 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:50:35,871 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:50:35,871 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:50:35,871 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-02-06 19:50:35,871 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:35,871 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:50:35,871 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:50:35,871 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration5_Loop [2025-02-06 19:50:35,871 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:50:35,871 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:50:35,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,888 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,916 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,923 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,940 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,957 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,971 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,984 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,986 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:35,998 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:36,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:36,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:36,013 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:36,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:50:36,297 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:50:36,301 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-02-06 19:50:36,302 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:36,302 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:36,306 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:36,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-02-06 19:50:36,309 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:36,320 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:36,320 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:36,321 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:36,321 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:36,321 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:36,327 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:36,327 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:36,328 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:36,334 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-02-06 19:50:36,335 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:36,335 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:36,339 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:36,339 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-02-06 19:50:36,341 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:36,352 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:36,352 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:36,352 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:36,352 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:36,352 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:36,352 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:36,352 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:36,355 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:50:36,361 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-02-06 19:50:36,362 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:36,362 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:36,363 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:36,365 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-02-06 19:50:36,366 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:50:36,376 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:50:36,376 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:50:36,376 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:50:36,376 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:50:36,376 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:50:36,377 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:50:36,377 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:50:36,380 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-02-06 19:50:36,383 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-02-06 19:50:36,386 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-02-06 19:50:36,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:50:36,391 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:50:36,395 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:50:36,397 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-02-06 19:50:36,398 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-02-06 19:50:36,398 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-02-06 19:50:36,398 INFO L474 LassoAnalysis]: Proved termination. [2025-02-06 19:50:36,399 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~main_dbl_ev~0) = -1*~main_dbl_ev~0 + 1 Supporting invariants [] [2025-02-06 19:50:36,408 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-02-06 19:50:36,412 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-02-06 19:50:36,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:36,479 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:36,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:36,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:36,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:36,507 INFO L256 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-02-06 19:50:36,508 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:36,571 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:36,583 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:36,583 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:36,583 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:36,584 INFO L256 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-02-06 19:50:36,585 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:50:36,647 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-02-06 19:50:36,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:36,703 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-02-06 19:50:36,704 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1140 states and 1974 transitions. cyclomatic complexity: 836 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:36,890 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1140 states and 1974 transitions. cyclomatic complexity: 836. Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 4148 states and 7215 transitions. Complement of second has 5 states. [2025-02-06 19:50:36,891 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-02-06 19:50:36,892 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:36,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1400 transitions. [2025-02-06 19:50:36,901 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 44 letters. [2025-02-06 19:50:36,906 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:36,906 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 84 letters. Loop has 44 letters. [2025-02-06 19:50:36,907 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:36,907 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 88 letters. [2025-02-06 19:50:36,908 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:50:36,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4148 states and 7215 transitions. [2025-02-06 19:50:36,938 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2928 [2025-02-06 19:50:36,962 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4148 states to 4148 states and 7215 transitions. [2025-02-06 19:50:36,962 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3098 [2025-02-06 19:50:36,967 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3135 [2025-02-06 19:50:36,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4148 states and 7215 transitions. [2025-02-06 19:50:36,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:36,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4148 states and 7215 transitions. [2025-02-06 19:50:36,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4148 states and 7215 transitions. [2025-02-06 19:50:37,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4148 to 3133. [2025-02-06 19:50:37,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3133 states, 3133 states have (on average 1.7405043089690393) internal successors, (5453), 3132 states have internal predecessors, (5453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:37,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3133 states to 3133 states and 5453 transitions. [2025-02-06 19:50:37,038 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3133 states and 5453 transitions. [2025-02-06 19:50:37,038 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:37,039 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:37,039 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:37,039 INFO L87 Difference]: Start difference. First operand 3133 states and 5453 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:37,339 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:37,339 INFO L93 Difference]: Finished difference Result 5016 states and 8751 transitions. [2025-02-06 19:50:37,339 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5016 states and 8751 transitions. [2025-02-06 19:50:37,367 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2990 [2025-02-06 19:50:37,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5016 states to 5016 states and 8751 transitions. [2025-02-06 19:50:37,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3383 [2025-02-06 19:50:37,395 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3383 [2025-02-06 19:50:37,396 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5016 states and 8751 transitions. [2025-02-06 19:50:37,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:37,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5016 states and 8751 transitions. [2025-02-06 19:50:37,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5016 states and 8751 transitions. [2025-02-06 19:50:37,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5016 to 3684. [2025-02-06 19:50:37,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3684 states, 3684 states have (on average 1.752442996742671) internal successors, (6456), 3683 states have internal predecessors, (6456), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:37,483 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3684 states to 3684 states and 6456 transitions. [2025-02-06 19:50:37,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3684 states and 6456 transitions. [2025-02-06 19:50:37,484 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:37,485 INFO L432 stractBuchiCegarLoop]: Abstraction has 3684 states and 6456 transitions. [2025-02-06 19:50:37,485 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:50:37,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3684 states and 6456 transitions. [2025-02-06 19:50:37,503 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2284 [2025-02-06 19:50:37,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:37,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:37,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:37,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:37,505 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" [2025-02-06 19:50:37,505 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:37,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:37,506 INFO L85 PathProgramCache]: Analyzing trace with hash -1973214483, now seen corresponding path program 1 times [2025-02-06 19:50:37,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:37,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053654096] [2025-02-06 19:50:37,506 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:37,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:37,513 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:37,517 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:37,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:37,518 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:37,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:37,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:37,570 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2053654096] [2025-02-06 19:50:37,570 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2053654096] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:37,573 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:37,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:37,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [448882472] [2025-02-06 19:50:37,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:37,574 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:37,574 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:37,574 INFO L85 PathProgramCache]: Analyzing trace with hash -1460073879, now seen corresponding path program 1 times [2025-02-06 19:50:37,574 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:37,574 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [377214278] [2025-02-06 19:50:37,574 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:37,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:37,584 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:37,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:37,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:37,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:37,618 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:37,619 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:37,619 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [377214278] [2025-02-06 19:50:37,619 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [377214278] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:37,619 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:37,619 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:37,619 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461679056] [2025-02-06 19:50:37,619 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:37,619 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:37,619 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:37,619 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:37,619 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:37,620 INFO L87 Difference]: Start difference. First operand 3684 states and 6456 transitions. cyclomatic complexity: 2778 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:37,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:37,826 INFO L93 Difference]: Finished difference Result 6129 states and 10529 transitions. [2025-02-06 19:50:37,826 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6129 states and 10529 transitions. [2025-02-06 19:50:37,857 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3866 [2025-02-06 19:50:37,888 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6129 states to 6129 states and 10529 transitions. [2025-02-06 19:50:37,889 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4117 [2025-02-06 19:50:37,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4117 [2025-02-06 19:50:37,893 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6129 states and 10529 transitions. [2025-02-06 19:50:37,894 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:37,894 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6129 states and 10529 transitions. [2025-02-06 19:50:37,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6129 states and 10529 transitions. [2025-02-06 19:50:37,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6129 to 6099. [2025-02-06 19:50:37,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6099 states, 6099 states have (on average 1.7165109034267914) internal successors, (10469), 6098 states have internal predecessors, (10469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:37,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6099 states to 6099 states and 10469 transitions. [2025-02-06 19:50:37,991 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6099 states and 10469 transitions. [2025-02-06 19:50:37,991 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:37,993 INFO L432 stractBuchiCegarLoop]: Abstraction has 6099 states and 10469 transitions. [2025-02-06 19:50:37,993 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:50:37,993 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6099 states and 10469 transitions. [2025-02-06 19:50:38,015 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3846 [2025-02-06 19:50:38,016 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:38,016 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:38,017 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,017 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,017 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" [2025-02-06 19:50:38,017 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:38,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:38,018 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474381, now seen corresponding path program 1 times [2025-02-06 19:50:38,018 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:38,018 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1739829035] [2025-02-06 19:50:38,018 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:38,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:38,023 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:38,027 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:38,027 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:38,027 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:38,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:38,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:38,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1739829035] [2025-02-06 19:50:38,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1739829035] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:38,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:38,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:38,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21096639] [2025-02-06 19:50:38,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:38,094 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:38,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:38,094 INFO L85 PathProgramCache]: Analyzing trace with hash -622400022, now seen corresponding path program 1 times [2025-02-06 19:50:38,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:38,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [362169194] [2025-02-06 19:50:38,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:38,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:38,098 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:38,100 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:38,100 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:38,100 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:38,119 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:38,119 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:38,119 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [362169194] [2025-02-06 19:50:38,119 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [362169194] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:38,119 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:38,119 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:38,120 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [532486069] [2025-02-06 19:50:38,120 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:38,120 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:38,120 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:38,120 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:38,120 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:38,120 INFO L87 Difference]: Start difference. First operand 6099 states and 10469 transitions. cyclomatic complexity: 4376 Second operand has 4 states, 3 states have (on average 13.333333333333334) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:38,438 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:38,438 INFO L93 Difference]: Finished difference Result 10308 states and 17358 transitions. [2025-02-06 19:50:38,438 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10308 states and 17358 transitions. [2025-02-06 19:50:38,469 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 6468 [2025-02-06 19:50:38,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10308 states to 10308 states and 17358 transitions. [2025-02-06 19:50:38,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6928 [2025-02-06 19:50:38,504 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6928 [2025-02-06 19:50:38,504 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10308 states and 17358 transitions. [2025-02-06 19:50:38,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:38,505 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10308 states and 17358 transitions. [2025-02-06 19:50:38,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10308 states and 17358 transitions. [2025-02-06 19:50:38,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10308 to 7825. [2025-02-06 19:50:38,597 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7825 states, 7825 states have (on average 1.6929073482428114) internal successors, (13247), 7824 states have internal predecessors, (13247), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:38,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7825 states to 7825 states and 13247 transitions. [2025-02-06 19:50:38,617 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7825 states and 13247 transitions. [2025-02-06 19:50:38,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:38,618 INFO L432 stractBuchiCegarLoop]: Abstraction has 7825 states and 13247 transitions. [2025-02-06 19:50:38,618 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:50:38,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7825 states and 13247 transitions. [2025-02-06 19:50:38,640 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4906 [2025-02-06 19:50:38,640 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:38,640 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:38,641 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,641 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,641 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" [2025-02-06 19:50:38,642 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-02-06 19:50:38,642 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:38,642 INFO L85 PathProgramCache]: Analyzing trace with hash 1873008558, now seen corresponding path program 1 times [2025-02-06 19:50:38,642 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:38,642 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091032805] [2025-02-06 19:50:38,642 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:38,642 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:38,646 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-06 19:50:38,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:50:38,648 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:38,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:38,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:38,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:38,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1091032805] [2025-02-06 19:50:38,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1091032805] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:38,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:38,678 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:38,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1481480042] [2025-02-06 19:50:38,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:38,678 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:38,678 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:38,679 INFO L85 PathProgramCache]: Analyzing trace with hash -622400022, now seen corresponding path program 2 times [2025-02-06 19:50:38,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:38,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565303466] [2025-02-06 19:50:38,679 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:38,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:38,682 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:38,683 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:38,683 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:38,683 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:38,698 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:38,698 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:38,698 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [565303466] [2025-02-06 19:50:38,698 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [565303466] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:38,698 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:38,698 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:50:38,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1143972793] [2025-02-06 19:50:38,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:38,699 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:38,699 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:38,699 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:38,699 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:38,699 INFO L87 Difference]: Start difference. First operand 7825 states and 13247 transitions. cyclomatic complexity: 5428 Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:38,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:38,823 INFO L93 Difference]: Finished difference Result 8387 states and 14042 transitions. [2025-02-06 19:50:38,823 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8387 states and 14042 transitions. [2025-02-06 19:50:38,851 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5274 [2025-02-06 19:50:38,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8387 states to 8387 states and 14042 transitions. [2025-02-06 19:50:38,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5630 [2025-02-06 19:50:38,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5630 [2025-02-06 19:50:38,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8387 states and 14042 transitions. [2025-02-06 19:50:38,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:38,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8387 states and 14042 transitions. [2025-02-06 19:50:38,886 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8387 states and 14042 transitions. [2025-02-06 19:50:38,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8387 to 7284. [2025-02-06 19:50:38,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7284 states, 7284 states have (on average 1.6801208127402527) internal successors, (12238), 7283 states have internal predecessors, (12238), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:38,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7284 states to 7284 states and 12238 transitions. [2025-02-06 19:50:38,964 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7284 states and 12238 transitions. [2025-02-06 19:50:38,964 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:38,964 INFO L432 stractBuchiCegarLoop]: Abstraction has 7284 states and 12238 transitions. [2025-02-06 19:50:38,964 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:50:38,965 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7284 states and 12238 transitions. [2025-02-06 19:50:38,980 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4568 [2025-02-06 19:50:38,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:38,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:38,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:38,981 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:38,981 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-02-06 19:50:38,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:38,982 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 1 times [2025-02-06 19:50:38,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:38,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [171890872] [2025-02-06 19:50:38,982 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:38,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:38,985 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:38,988 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:38,988 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:38,988 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:38,988 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:38,990 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:38,996 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:38,996 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:38,996 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:39,010 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:39,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:39,011 INFO L85 PathProgramCache]: Analyzing trace with hash 672742392, now seen corresponding path program 1 times [2025-02-06 19:50:39,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:39,016 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063459160] [2025-02-06 19:50:39,016 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:39,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:39,019 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:39,025 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:39,025 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:39,025 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:39,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:39,057 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:39,057 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063459160] [2025-02-06 19:50:39,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063459160] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:39,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:39,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:39,057 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2080752745] [2025-02-06 19:50:39,057 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:39,057 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:39,057 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:39,058 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:39,058 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:39,058 INFO L87 Difference]: Start difference. First operand 7284 states and 12238 transitions. cyclomatic complexity: 4960 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:39,168 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:39,171 INFO L93 Difference]: Finished difference Result 10167 states and 17005 transitions. [2025-02-06 19:50:39,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10167 states and 17005 transitions. [2025-02-06 19:50:39,226 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6272 [2025-02-06 19:50:39,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10167 states to 10167 states and 17005 transitions. [2025-02-06 19:50:39,325 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6861 [2025-02-06 19:50:39,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6861 [2025-02-06 19:50:39,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10167 states and 17005 transitions. [2025-02-06 19:50:39,330 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:39,330 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10167 states and 17005 transitions. [2025-02-06 19:50:39,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10167 states and 17005 transitions. [2025-02-06 19:50:39,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10167 to 10125. [2025-02-06 19:50:39,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10125 states, 10125 states have (on average 1.675358024691358) internal successors, (16963), 10124 states have internal predecessors, (16963), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:39,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10125 states to 10125 states and 16963 transitions. [2025-02-06 19:50:39,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10125 states and 16963 transitions. [2025-02-06 19:50:39,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:39,437 INFO L432 stractBuchiCegarLoop]: Abstraction has 10125 states and 16963 transitions. [2025-02-06 19:50:39,438 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:50:39,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10125 states and 16963 transitions. [2025-02-06 19:50:39,461 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6248 [2025-02-06 19:50:39,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:39,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:39,462 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:39,462 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:39,462 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:39,462 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-02-06 19:50:39,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:39,463 INFO L85 PathProgramCache]: Analyzing trace with hash -1063766375, now seen corresponding path program 1 times [2025-02-06 19:50:39,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:39,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1236360292] [2025-02-06 19:50:39,463 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:39,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:39,466 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:39,468 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:39,468 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:39,469 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:39,509 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:39,510 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:39,510 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1236360292] [2025-02-06 19:50:39,510 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1236360292] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:39,510 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:39,510 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:39,510 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2059667929] [2025-02-06 19:50:39,510 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:39,510 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:39,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:39,510 INFO L85 PathProgramCache]: Analyzing trace with hash -1520730431, now seen corresponding path program 1 times [2025-02-06 19:50:39,514 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:39,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090954374] [2025-02-06 19:50:39,515 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:39,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:39,519 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 47 statements into 1 equivalence classes. [2025-02-06 19:50:39,525 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 47 of 47 statements. [2025-02-06 19:50:39,525 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:39,525 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:39,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:39,547 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:39,547 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2090954374] [2025-02-06 19:50:39,547 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2090954374] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:39,547 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:39,547 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:39,547 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [769710744] [2025-02-06 19:50:39,547 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:39,548 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:39,548 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:39,548 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:39,548 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:39,548 INFO L87 Difference]: Start difference. First operand 10125 states and 16963 transitions. cyclomatic complexity: 6848 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:39,674 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:39,675 INFO L93 Difference]: Finished difference Result 11157 states and 18351 transitions. [2025-02-06 19:50:39,675 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11157 states and 18351 transitions. [2025-02-06 19:50:39,734 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7224 [2025-02-06 19:50:39,764 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11157 states to 11157 states and 18351 transitions. [2025-02-06 19:50:39,764 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7384 [2025-02-06 19:50:39,771 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7384 [2025-02-06 19:50:39,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11157 states and 18351 transitions. [2025-02-06 19:50:39,772 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:39,772 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11157 states and 18351 transitions. [2025-02-06 19:50:39,781 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11157 states and 18351 transitions. [2025-02-06 19:50:39,859 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11157 to 11157. [2025-02-06 19:50:39,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11157 states, 11157 states have (on average 1.644796988437752) internal successors, (18351), 11156 states have internal predecessors, (18351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:39,898 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11157 states to 11157 states and 18351 transitions. [2025-02-06 19:50:39,898 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11157 states and 18351 transitions. [2025-02-06 19:50:39,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:39,899 INFO L432 stractBuchiCegarLoop]: Abstraction has 11157 states and 18351 transitions. [2025-02-06 19:50:39,899 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:50:39,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11157 states and 18351 transitions. [2025-02-06 19:50:39,925 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7224 [2025-02-06 19:50:39,925 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:39,925 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:39,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:39,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:39,928 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:39,928 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume true;" [2025-02-06 19:50:39,928 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:39,929 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 2 times [2025-02-06 19:50:39,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:39,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2052663867] [2025-02-06 19:50:39,929 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:39,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:39,933 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:39,938 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:39,940 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:39,941 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:39,941 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:39,943 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:39,945 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:39,946 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:39,946 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:39,953 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:39,954 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:39,954 INFO L85 PathProgramCache]: Analyzing trace with hash -619825120, now seen corresponding path program 1 times [2025-02-06 19:50:39,954 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:39,954 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [427444002] [2025-02-06 19:50:39,954 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:39,954 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:39,958 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-02-06 19:50:39,960 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-02-06 19:50:39,960 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:39,960 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:39,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:39,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:39,977 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [427444002] [2025-02-06 19:50:39,977 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [427444002] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:39,977 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:39,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:39,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [371527447] [2025-02-06 19:50:39,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:39,977 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:39,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:39,978 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:39,978 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:39,978 INFO L87 Difference]: Start difference. First operand 11157 states and 18351 transitions. cyclomatic complexity: 7206 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:40,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:40,115 INFO L93 Difference]: Finished difference Result 15193 states and 24905 transitions. [2025-02-06 19:50:40,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15193 states and 24905 transitions. [2025-02-06 19:50:40,160 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 9797 [2025-02-06 19:50:40,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15193 states to 15193 states and 24905 transitions. [2025-02-06 19:50:40,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10059 [2025-02-06 19:50:40,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10059 [2025-02-06 19:50:40,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15193 states and 24905 transitions. [2025-02-06 19:50:40,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:40,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15193 states and 24905 transitions. [2025-02-06 19:50:40,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15193 states and 24905 transitions. [2025-02-06 19:50:40,323 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15193 to 15118. [2025-02-06 19:50:40,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15118 states, 15118 states have (on average 1.6424130175949199) internal successors, (24830), 15117 states have internal predecessors, (24830), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:40,366 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15118 states to 15118 states and 24830 transitions. [2025-02-06 19:50:40,366 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15118 states and 24830 transitions. [2025-02-06 19:50:40,366 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:40,367 INFO L432 stractBuchiCegarLoop]: Abstraction has 15118 states and 24830 transitions. [2025-02-06 19:50:40,367 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:50:40,367 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15118 states and 24830 transitions. [2025-02-06 19:50:40,398 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 9749 [2025-02-06 19:50:40,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:40,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:40,398 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:40,398 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:40,399 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:40,399 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume true;" [2025-02-06 19:50:40,399 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:40,399 INFO L85 PathProgramCache]: Analyzing trace with hash -724282565, now seen corresponding path program 1 times [2025-02-06 19:50:40,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:40,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1673442591] [2025-02-06 19:50:40,399 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:40,399 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:40,403 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:40,405 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:40,405 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:40,405 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:40,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:40,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:40,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1673442591] [2025-02-06 19:50:40,429 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1673442591] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:40,429 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:40,429 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:40,429 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301495210] [2025-02-06 19:50:40,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:40,429 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:40,429 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:40,430 INFO L85 PathProgramCache]: Analyzing trace with hash -895078250, now seen corresponding path program 1 times [2025-02-06 19:50:40,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:40,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1550346965] [2025-02-06 19:50:40,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:40,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:40,433 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-02-06 19:50:40,434 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-02-06 19:50:40,434 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:40,434 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:40,445 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:40,445 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:40,445 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1550346965] [2025-02-06 19:50:40,445 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1550346965] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:40,445 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:40,445 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:40,445 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1221907363] [2025-02-06 19:50:40,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:40,446 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:40,446 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:40,446 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:40,446 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:40,446 INFO L87 Difference]: Start difference. First operand 15118 states and 24830 transitions. cyclomatic complexity: 9726 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:40,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:40,511 INFO L93 Difference]: Finished difference Result 12598 states and 20382 transitions. [2025-02-06 19:50:40,511 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12598 states and 20382 transitions. [2025-02-06 19:50:40,550 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8166 [2025-02-06 19:50:40,579 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12598 states to 12598 states and 20382 transitions. [2025-02-06 19:50:40,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8339 [2025-02-06 19:50:40,585 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8339 [2025-02-06 19:50:40,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12598 states and 20382 transitions. [2025-02-06 19:50:40,586 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:40,586 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12598 states and 20382 transitions. [2025-02-06 19:50:40,591 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12598 states and 20382 transitions. [2025-02-06 19:50:40,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12598 to 12598. [2025-02-06 19:50:40,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12598 states, 12598 states have (on average 1.6178758533100492) internal successors, (20382), 12597 states have internal predecessors, (20382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:40,849 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12598 states to 12598 states and 20382 transitions. [2025-02-06 19:50:40,849 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12598 states and 20382 transitions. [2025-02-06 19:50:40,849 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:40,850 INFO L432 stractBuchiCegarLoop]: Abstraction has 12598 states and 20382 transitions. [2025-02-06 19:50:40,850 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:50:40,850 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12598 states and 20382 transitions. [2025-02-06 19:50:40,880 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8166 [2025-02-06 19:50:40,880 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:40,880 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:40,881 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:40,881 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:40,881 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:40,881 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume 0 == ~S2_presdbl_st~0;" "assume true;" [2025-02-06 19:50:40,882 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:40,882 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 3 times [2025-02-06 19:50:40,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:40,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [428648900] [2025-02-06 19:50:40,882 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:40,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:40,887 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:40,890 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:40,890 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:40,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:40,890 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:40,895 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:40,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:40,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:40,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:40,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:40,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:40,904 INFO L85 PathProgramCache]: Analyzing trace with hash -2034712390, now seen corresponding path program 1 times [2025-02-06 19:50:40,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:40,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [160711590] [2025-02-06 19:50:40,904 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:40,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:40,907 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-02-06 19:50:40,909 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-02-06 19:50:40,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:40,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:40,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:40,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:40,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [160711590] [2025-02-06 19:50:40,924 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [160711590] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:40,924 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:40,924 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:40,924 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1265046608] [2025-02-06 19:50:40,924 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:40,924 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:40,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:40,924 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:40,924 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:40,925 INFO L87 Difference]: Start difference. First operand 12598 states and 20382 transitions. cyclomatic complexity: 7796 Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:41,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:41,041 INFO L93 Difference]: Finished difference Result 17248 states and 27759 transitions. [2025-02-06 19:50:41,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17248 states and 27759 transitions. [2025-02-06 19:50:41,121 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 11150 [2025-02-06 19:50:41,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17248 states to 17248 states and 27759 transitions. [2025-02-06 19:50:41,181 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11423 [2025-02-06 19:50:41,189 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11423 [2025-02-06 19:50:41,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17248 states and 27759 transitions. [2025-02-06 19:50:41,190 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:41,190 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17248 states and 27759 transitions. [2025-02-06 19:50:41,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17248 states and 27759 transitions. [2025-02-06 19:50:41,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17248 to 17123. [2025-02-06 19:50:41,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17123 states, 17123 states have (on average 1.6138527127255737) internal successors, (27634), 17122 states have internal predecessors, (27634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:41,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17123 states to 17123 states and 27634 transitions. [2025-02-06 19:50:41,401 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17123 states and 27634 transitions. [2025-02-06 19:50:41,402 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:41,402 INFO L432 stractBuchiCegarLoop]: Abstraction has 17123 states and 27634 transitions. [2025-02-06 19:50:41,402 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 19:50:41,402 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17123 states and 27634 transitions. [2025-02-06 19:50:41,441 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 11070 [2025-02-06 19:50:41,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:41,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:41,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:41,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:41,443 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:41,443 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume 0 == ~S2_presdbl_st~0;" "assume true;" [2025-02-06 19:50:41,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:41,443 INFO L85 PathProgramCache]: Analyzing trace with hash -1406068135, now seen corresponding path program 1 times [2025-02-06 19:50:41,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:41,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1009190212] [2025-02-06 19:50:41,443 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:41,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:41,447 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:41,449 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:41,449 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:41,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:41,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:41,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:41,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1009190212] [2025-02-06 19:50:41,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1009190212] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:41,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:41,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:41,473 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716280968] [2025-02-06 19:50:41,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:41,473 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:41,473 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:41,473 INFO L85 PathProgramCache]: Analyzing trace with hash -1133152957, now seen corresponding path program 1 times [2025-02-06 19:50:41,473 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:41,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [202134280] [2025-02-06 19:50:41,474 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:41,474 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:41,477 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-02-06 19:50:41,478 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:50:41,478 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:41,478 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:41,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:41,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:41,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [202134280] [2025-02-06 19:50:41,487 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [202134280] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:41,487 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:41,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:41,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [395324152] [2025-02-06 19:50:41,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:41,488 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:41,488 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:41,488 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:41,488 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:41,488 INFO L87 Difference]: Start difference. First operand 17123 states and 27634 transitions. cyclomatic complexity: 10525 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:41,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:41,558 INFO L93 Difference]: Finished difference Result 14698 states and 23396 transitions. [2025-02-06 19:50:41,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14698 states and 23396 transitions. [2025-02-06 19:50:41,601 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9548 [2025-02-06 19:50:41,635 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14698 states to 14698 states and 23396 transitions. [2025-02-06 19:50:41,635 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9733 [2025-02-06 19:50:41,641 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9733 [2025-02-06 19:50:41,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14698 states and 23396 transitions. [2025-02-06 19:50:41,642 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:41,642 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14698 states and 23396 transitions. [2025-02-06 19:50:41,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14698 states and 23396 transitions. [2025-02-06 19:50:41,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14698 to 14698. [2025-02-06 19:50:41,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14698 states, 14698 states have (on average 1.5917811947203702) internal successors, (23396), 14697 states have internal predecessors, (23396), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:41,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14698 states to 14698 states and 23396 transitions. [2025-02-06 19:50:41,927 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14698 states and 23396 transitions. [2025-02-06 19:50:41,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:41,928 INFO L432 stractBuchiCegarLoop]: Abstraction has 14698 states and 23396 transitions. [2025-02-06 19:50:41,928 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 19:50:41,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14698 states and 23396 transitions. [2025-02-06 19:50:41,957 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9548 [2025-02-06 19:50:41,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:41,958 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:41,959 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:41,959 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:41,959 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:41,959 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" "assume true;" [2025-02-06 19:50:41,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:41,959 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 4 times [2025-02-06 19:50:41,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:41,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [131653742] [2025-02-06 19:50:41,959 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:50:41,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:41,964 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 41 statements into 2 equivalence classes. [2025-02-06 19:50:41,966 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:41,967 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:50:41,967 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:41,967 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:41,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:41,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:41,971 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:41,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:41,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:41,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:41,975 INFO L85 PathProgramCache]: Analyzing trace with hash 1348422434, now seen corresponding path program 1 times [2025-02-06 19:50:41,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:41,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328810878] [2025-02-06 19:50:41,975 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:41,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:41,978 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 47 statements into 1 equivalence classes. [2025-02-06 19:50:41,979 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 47 of 47 statements. [2025-02-06 19:50:41,979 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:41,980 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:41,991 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:41,991 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:41,991 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328810878] [2025-02-06 19:50:41,991 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328810878] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:41,992 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:41,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:41,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052728722] [2025-02-06 19:50:41,992 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:41,992 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:41,992 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:41,992 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:41,992 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:41,992 INFO L87 Difference]: Start difference. First operand 14698 states and 23396 transitions. cyclomatic complexity: 8710 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:42,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:42,078 INFO L93 Difference]: Finished difference Result 20572 states and 32422 transitions. [2025-02-06 19:50:42,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20572 states and 32422 transitions. [2025-02-06 19:50:42,142 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 13349 [2025-02-06 19:50:42,195 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20572 states to 20572 states and 32422 transitions. [2025-02-06 19:50:42,195 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13633 [2025-02-06 19:50:42,204 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13633 [2025-02-06 19:50:42,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20572 states and 32422 transitions. [2025-02-06 19:50:42,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:42,205 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20572 states and 32422 transitions. [2025-02-06 19:50:42,218 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20572 states and 32422 transitions. [2025-02-06 19:50:42,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20572 to 20372. [2025-02-06 19:50:42,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20372 states, 20372 states have (on average 1.5816807382682112) internal successors, (32222), 20371 states have internal predecessors, (32222), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:42,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20372 states to 20372 states and 32222 transitions. [2025-02-06 19:50:42,411 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20372 states and 32222 transitions. [2025-02-06 19:50:42,412 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:42,412 INFO L432 stractBuchiCegarLoop]: Abstraction has 20372 states and 32222 transitions. [2025-02-06 19:50:42,412 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-06 19:50:42,412 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20372 states and 32222 transitions. [2025-02-06 19:50:42,459 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 13221 [2025-02-06 19:50:42,460 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:42,460 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:42,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:42,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:42,461 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:42,461 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" "assume true;" [2025-02-06 19:50:42,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:42,461 INFO L85 PathProgramCache]: Analyzing trace with hash -458229893, now seen corresponding path program 1 times [2025-02-06 19:50:42,461 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:42,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624950736] [2025-02-06 19:50:42,461 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:42,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:42,465 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:42,468 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:42,469 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:42,469 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:42,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:42,493 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:42,494 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [624950736] [2025-02-06 19:50:42,494 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [624950736] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:42,494 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:42,494 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:42,494 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [498787309] [2025-02-06 19:50:42,494 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:42,494 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:42,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:42,494 INFO L85 PathProgramCache]: Analyzing trace with hash 1270050074, now seen corresponding path program 1 times [2025-02-06 19:50:42,494 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:42,494 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2042697072] [2025-02-06 19:50:42,494 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:42,494 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:42,499 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-02-06 19:50:42,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-02-06 19:50:42,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:42,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:42,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:42,513 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:42,513 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2042697072] [2025-02-06 19:50:42,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2042697072] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:42,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:42,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:42,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [326718721] [2025-02-06 19:50:42,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:42,513 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:42,514 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:42,514 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:42,514 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:42,514 INFO L87 Difference]: Start difference. First operand 20372 states and 32222 transitions. cyclomatic complexity: 11864 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:42,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:42,593 INFO L93 Difference]: Finished difference Result 18042 states and 28194 transitions. [2025-02-06 19:50:42,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18042 states and 28194 transitions. [2025-02-06 19:50:42,647 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11760 [2025-02-06 19:50:42,891 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18042 states to 18042 states and 28194 transitions. [2025-02-06 19:50:42,892 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11956 [2025-02-06 19:50:42,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11956 [2025-02-06 19:50:42,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18042 states and 28194 transitions. [2025-02-06 19:50:42,898 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:42,898 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18042 states and 28194 transitions. [2025-02-06 19:50:42,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18042 states and 28194 transitions. [2025-02-06 19:50:43,012 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18042 to 18042. [2025-02-06 19:50:43,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18042 states, 18042 states have (on average 1.5626870635184569) internal successors, (28194), 18041 states have internal predecessors, (28194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:43,219 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18042 states to 18042 states and 28194 transitions. [2025-02-06 19:50:43,220 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18042 states and 28194 transitions. [2025-02-06 19:50:43,220 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:43,220 INFO L432 stractBuchiCegarLoop]: Abstraction has 18042 states and 28194 transitions. [2025-02-06 19:50:43,220 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-06 19:50:43,220 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18042 states and 28194 transitions. [2025-02-06 19:50:43,251 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11760 [2025-02-06 19:50:43,252 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:43,252 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:43,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:43,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:43,253 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:43,253 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" "assume true;" [2025-02-06 19:50:43,253 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:43,253 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 5 times [2025-02-06 19:50:43,253 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:43,253 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1420816041] [2025-02-06 19:50:43,254 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:50:43,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:43,259 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:43,261 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:43,261 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:43,262 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:43,262 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:43,263 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:43,266 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:43,266 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:43,266 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:43,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:43,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:43,274 INFO L85 PathProgramCache]: Analyzing trace with hash -1148580484, now seen corresponding path program 1 times [2025-02-06 19:50:43,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:43,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [460333301] [2025-02-06 19:50:43,275 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:43,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:43,279 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-02-06 19:50:43,280 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-02-06 19:50:43,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:43,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:43,292 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:43,292 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:43,292 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [460333301] [2025-02-06 19:50:43,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [460333301] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:43,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:43,293 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:43,293 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1426450359] [2025-02-06 19:50:43,293 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:43,293 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:43,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:43,293 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:43,293 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:43,293 INFO L87 Difference]: Start difference. First operand 18042 states and 28194 transitions. cyclomatic complexity: 10164 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:43,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:43,384 INFO L93 Difference]: Finished difference Result 25357 states and 38867 transitions. [2025-02-06 19:50:43,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25357 states and 38867 transitions. [2025-02-06 19:50:43,469 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 15966 [2025-02-06 19:50:43,533 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25357 states to 25357 states and 38867 transitions. [2025-02-06 19:50:43,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16819 [2025-02-06 19:50:43,547 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16819 [2025-02-06 19:50:43,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25357 states and 38867 transitions. [2025-02-06 19:50:43,550 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:43,550 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25357 states and 38867 transitions. [2025-02-06 19:50:43,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25357 states and 38867 transitions. [2025-02-06 19:50:43,931 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25357 to 25057. [2025-02-06 19:50:43,954 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25057 states, 25057 states have (on average 1.5391706908249192) internal successors, (38567), 25056 states have internal predecessors, (38567), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:44,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25057 states to 25057 states and 38567 transitions. [2025-02-06 19:50:44,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25057 states and 38567 transitions. [2025-02-06 19:50:44,144 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:44,144 INFO L432 stractBuchiCegarLoop]: Abstraction has 25057 states and 38567 transitions. [2025-02-06 19:50:44,145 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-06 19:50:44,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25057 states and 38567 transitions. [2025-02-06 19:50:44,194 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 15774 [2025-02-06 19:50:44,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:44,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:44,195 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:44,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:44,195 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:44,195 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" "assume true;" [2025-02-06 19:50:44,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:44,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1674580455, now seen corresponding path program 1 times [2025-02-06 19:50:44,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:44,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020280863] [2025-02-06 19:50:44,197 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:44,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:44,202 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:50:44,206 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:50:44,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:44,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:44,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:44,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:44,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020280863] [2025-02-06 19:50:44,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020280863] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:44,232 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:44,232 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:44,232 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [41728599] [2025-02-06 19:50:44,232 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:44,233 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:44,233 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:44,233 INFO L85 PathProgramCache]: Analyzing trace with hash 716843652, now seen corresponding path program 1 times [2025-02-06 19:50:44,233 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:44,233 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [651797701] [2025-02-06 19:50:44,233 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:44,233 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:44,237 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-02-06 19:50:44,239 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-02-06 19:50:44,239 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:44,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:44,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:44,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:44,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [651797701] [2025-02-06 19:50:44,250 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [651797701] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:44,250 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:44,250 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:44,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1552501575] [2025-02-06 19:50:44,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:44,251 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:44,251 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:44,251 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:44,251 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:44,251 INFO L87 Difference]: Start difference. First operand 25057 states and 38567 transitions. cyclomatic complexity: 13524 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:44,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:44,330 INFO L93 Difference]: Finished difference Result 22822 states and 34749 transitions. [2025-02-06 19:50:44,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22822 states and 34749 transitions. [2025-02-06 19:50:44,544 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14374 [2025-02-06 19:50:44,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22822 states to 22822 states and 34749 transitions. [2025-02-06 19:50:44,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15138 [2025-02-06 19:50:44,620 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15138 [2025-02-06 19:50:44,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22822 states and 34749 transitions. [2025-02-06 19:50:44,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:44,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22822 states and 34749 transitions. [2025-02-06 19:50:44,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22822 states and 34749 transitions. [2025-02-06 19:50:44,827 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22822 to 22822. [2025-02-06 19:50:44,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22822 states, 22822 states have (on average 1.522609762509859) internal successors, (34749), 22821 states have internal predecessors, (34749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:44,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22822 states to 22822 states and 34749 transitions. [2025-02-06 19:50:44,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22822 states and 34749 transitions. [2025-02-06 19:50:44,872 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:44,873 INFO L432 stractBuchiCegarLoop]: Abstraction has 22822 states and 34749 transitions. [2025-02-06 19:50:44,873 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-06 19:50:44,873 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22822 states and 34749 transitions. [2025-02-06 19:50:44,919 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14374 [2025-02-06 19:50:44,920 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:44,920 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:44,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:44,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:44,921 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:50:44,921 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-02-06 19:50:44,922 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:44,922 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 1 times [2025-02-06 19:50:44,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:44,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197362472] [2025-02-06 19:50:44,922 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:44,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:44,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:44,930 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:44,930 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:44,930 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:44,930 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:44,933 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:44,934 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:44,934 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:44,934 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:44,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:44,938 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:44,939 INFO L85 PathProgramCache]: Analyzing trace with hash -244030365, now seen corresponding path program 1 times [2025-02-06 19:50:44,939 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:44,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1129791771] [2025-02-06 19:50:44,939 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:44,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:44,942 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-02-06 19:50:44,943 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-02-06 19:50:44,946 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:44,946 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:44,960 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:44,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:44,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1129791771] [2025-02-06 19:50:44,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1129791771] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:44,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:44,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:44,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1651270428] [2025-02-06 19:50:44,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:44,961 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:44,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:44,961 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:44,961 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:44,961 INFO L87 Difference]: Start difference. First operand 22822 states and 34749 transitions. cyclomatic complexity: 11939 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:45,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:45,046 INFO L93 Difference]: Finished difference Result 22822 states and 34627 transitions. [2025-02-06 19:50:45,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22822 states and 34627 transitions. [2025-02-06 19:50:45,120 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14374 [2025-02-06 19:50:45,168 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22822 states to 22822 states and 34627 transitions. [2025-02-06 19:50:45,168 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15138 [2025-02-06 19:50:45,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15138 [2025-02-06 19:50:45,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22822 states and 34627 transitions. [2025-02-06 19:50:45,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:45,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22822 states and 34627 transitions. [2025-02-06 19:50:45,226 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22822 states and 34627 transitions. [2025-02-06 19:50:45,588 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22822 to 22822. [2025-02-06 19:50:45,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22822 states, 22822 states have (on average 1.5172640434668303) internal successors, (34627), 22821 states have internal predecessors, (34627), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:45,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22822 states to 22822 states and 34627 transitions. [2025-02-06 19:50:45,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22822 states and 34627 transitions. [2025-02-06 19:50:45,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:45,647 INFO L432 stractBuchiCegarLoop]: Abstraction has 22822 states and 34627 transitions. [2025-02-06 19:50:45,647 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-06 19:50:45,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22822 states and 34627 transitions. [2025-02-06 19:50:45,712 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 14374 [2025-02-06 19:50:45,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:45,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:45,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:45,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:45,714 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:50:45,714 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-02-06 19:50:45,714 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:45,714 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 2 times [2025-02-06 19:50:45,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:45,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608448727] [2025-02-06 19:50:45,715 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:45,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:45,721 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:45,725 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:45,725 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:45,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:45,725 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:45,728 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:45,730 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:45,731 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:45,731 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:45,735 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:45,736 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:45,736 INFO L85 PathProgramCache]: Analyzing trace with hash 972320197, now seen corresponding path program 1 times [2025-02-06 19:50:45,736 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:45,736 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [965708372] [2025-02-06 19:50:45,736 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:45,736 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:45,740 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-02-06 19:50:45,742 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-02-06 19:50:45,742 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:45,742 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:45,753 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:45,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:45,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [965708372] [2025-02-06 19:50:45,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [965708372] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:45,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:45,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:45,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1556347899] [2025-02-06 19:50:45,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:45,754 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:45,754 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:45,755 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:45,755 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:45,755 INFO L87 Difference]: Start difference. First operand 22822 states and 34627 transitions. cyclomatic complexity: 11817 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:45,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:45,881 INFO L93 Difference]: Finished difference Result 17505 states and 26075 transitions. [2025-02-06 19:50:45,881 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17505 states and 26075 transitions. [2025-02-06 19:50:45,940 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11098 [2025-02-06 19:50:45,983 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17505 states to 17505 states and 26075 transitions. [2025-02-06 19:50:45,983 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11640 [2025-02-06 19:50:45,992 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11640 [2025-02-06 19:50:45,993 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17505 states and 26075 transitions. [2025-02-06 19:50:45,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:45,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17505 states and 26075 transitions. [2025-02-06 19:50:46,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17505 states and 26075 transitions. [2025-02-06 19:50:46,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17505 to 17505. [2025-02-06 19:50:46,315 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17505 states, 17505 states have (on average 1.4895744073121966) internal successors, (26075), 17504 states have internal predecessors, (26075), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:46,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17505 states to 17505 states and 26075 transitions. [2025-02-06 19:50:46,336 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17505 states and 26075 transitions. [2025-02-06 19:50:46,336 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:46,336 INFO L432 stractBuchiCegarLoop]: Abstraction has 17505 states and 26075 transitions. [2025-02-06 19:50:46,336 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-06 19:50:46,337 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17505 states and 26075 transitions. [2025-02-06 19:50:46,375 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11098 [2025-02-06 19:50:46,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:46,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:46,376 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:46,376 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:46,376 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:50:46,376 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-02-06 19:50:46,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:46,377 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 3 times [2025-02-06 19:50:46,377 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:46,377 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1771686410] [2025-02-06 19:50:46,377 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:46,377 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:46,380 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:46,383 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:46,383 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:46,383 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:46,383 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:46,385 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:50:46,387 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:50:46,387 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:46,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:46,391 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:46,392 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:46,392 INFO L85 PathProgramCache]: Analyzing trace with hash 10706180, now seen corresponding path program 1 times [2025-02-06 19:50:46,392 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:46,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1800602765] [2025-02-06 19:50:46,392 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:46,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:46,395 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-02-06 19:50:46,397 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-02-06 19:50:46,397 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:46,397 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:46,408 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:46,408 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:46,408 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1800602765] [2025-02-06 19:50:46,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1800602765] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:46,409 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:46,409 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:46,409 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [908280114] [2025-02-06 19:50:46,409 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:46,409 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:46,409 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:46,409 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:46,409 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:46,409 INFO L87 Difference]: Start difference. First operand 17505 states and 26075 transitions. cyclomatic complexity: 8582 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:46,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:46,473 INFO L93 Difference]: Finished difference Result 15390 states and 22250 transitions. [2025-02-06 19:50:46,473 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15390 states and 22250 transitions. [2025-02-06 19:50:46,517 INFO L131 ngComponentsAnalysis]: Automaton has 102 accepting balls. 9134 [2025-02-06 19:50:46,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15390 states to 15390 states and 22250 transitions. [2025-02-06 19:50:46,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10230 [2025-02-06 19:50:46,554 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10230 [2025-02-06 19:50:46,555 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15390 states and 22250 transitions. [2025-02-06 19:50:46,555 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:46,555 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15390 states and 22250 transitions. [2025-02-06 19:50:46,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15390 states and 22250 transitions. [2025-02-06 19:50:46,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15390 to 13196. [2025-02-06 19:50:46,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13196 states, 13196 states have (on average 1.4489996968778418) internal successors, (19121), 13195 states have internal predecessors, (19121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:46,669 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13196 states to 13196 states and 19121 transitions. [2025-02-06 19:50:46,669 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13196 states and 19121 transitions. [2025-02-06 19:50:46,670 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:46,670 INFO L432 stractBuchiCegarLoop]: Abstraction has 13196 states and 19121 transitions. [2025-02-06 19:50:46,670 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-02-06 19:50:46,670 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13196 states and 19121 transitions. [2025-02-06 19:50:46,698 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 8174 [2025-02-06 19:50:46,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:46,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:46,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:46,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:46,700 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-02-06 19:50:46,700 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume 0 != eval_~tmp~0#1;~N_generate_st~0 := 1;assume { :begin_inline_N_generate } true;havoc N_generate_~a~0#1, N_generate_~b~0#1;havoc N_generate_~a~0#1;havoc N_generate_~b~0#1;~main_in1_val_t~0 := N_generate_~a~0#1;~main_in1_req_up~0 := 1;~main_in2_val_t~0 := N_generate_~b~0#1;~main_in2_req_up~0 := 1;" "havoc N_generate_~a~0#1, N_generate_~b~0#1;assume { :end_inline_N_generate } true;" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-02-06 19:50:46,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:46,700 INFO L85 PathProgramCache]: Analyzing trace with hash -2062638999, now seen corresponding path program 1 times [2025-02-06 19:50:46,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:46,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718811336] [2025-02-06 19:50:46,700 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:46,701 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:46,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:50:46,710 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:50:46,710 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:46,710 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:46,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:46,740 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:46,740 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718811336] [2025-02-06 19:50:46,740 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718811336] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:46,740 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:46,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:46,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [485360743] [2025-02-06 19:50:46,741 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:46,741 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:46,742 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:46,742 INFO L85 PathProgramCache]: Analyzing trace with hash -1087832447, now seen corresponding path program 1 times [2025-02-06 19:50:46,742 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:46,742 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [297288010] [2025-02-06 19:50:46,742 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:46,742 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:46,746 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-02-06 19:50:46,748 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-02-06 19:50:46,748 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:46,748 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:46,758 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:46,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:46,758 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [297288010] [2025-02-06 19:50:46,758 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [297288010] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:46,758 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:46,758 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:46,758 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1301950615] [2025-02-06 19:50:46,758 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:46,759 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:46,759 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:46,759 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:46,759 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:46,759 INFO L87 Difference]: Start difference. First operand 13196 states and 19121 transitions. cyclomatic complexity: 5934 Second operand has 4 states, 4 states have (on average 11.0) internal successors, (44), 4 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:46,808 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:46,808 INFO L93 Difference]: Finished difference Result 8622 states and 12403 transitions. [2025-02-06 19:50:46,808 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8622 states and 12403 transitions. [2025-02-06 19:50:46,831 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-02-06 19:50:46,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8622 states to 8622 states and 12403 transitions. [2025-02-06 19:50:46,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5722 [2025-02-06 19:50:46,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5722 [2025-02-06 19:50:46,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8622 states and 12403 transitions. [2025-02-06 19:50:46,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:46,849 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8622 states and 12403 transitions. [2025-02-06 19:50:47,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8622 states and 12403 transitions. [2025-02-06 19:50:47,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8622 to 8616. [2025-02-06 19:50:47,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8616 states, 8616 states have (on average 1.4388347260909935) internal successors, (12397), 8615 states have internal predecessors, (12397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8616 states to 8616 states and 12397 transitions. [2025-02-06 19:50:47,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12397 transitions. [2025-02-06 19:50:47,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:47,078 INFO L432 stractBuchiCegarLoop]: Abstraction has 8616 states and 12397 transitions. [2025-02-06 19:50:47,078 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-02-06 19:50:47,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8616 states and 12397 transitions. [2025-02-06 19:50:47,098 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-02-06 19:50:47,098 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:47,098 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:47,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,100 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,100 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,101 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,101 INFO L85 PathProgramCache]: Analyzing trace with hash 1245953054, now seen corresponding path program 1 times [2025-02-06 19:50:47,101 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,101 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734336907] [2025-02-06 19:50:47,101 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:47,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,106 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:47,108 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:47,109 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,109 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:47,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:47,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:47,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734336907] [2025-02-06 19:50:47,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734336907] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:47,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:47,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:47,150 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904954478] [2025-02-06 19:50:47,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:47,151 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:47,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,151 INFO L85 PathProgramCache]: Analyzing trace with hash 1482777633, now seen corresponding path program 1 times [2025-02-06 19:50:47,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617399438] [2025-02-06 19:50:47,152 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:47,152 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,158 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 178 statements into 1 equivalence classes. [2025-02-06 19:50:47,159 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-02-06 19:50:47,160 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,160 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:47,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:47,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:47,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617399438] [2025-02-06 19:50:47,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617399438] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:47,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:47,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:47,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1240847380] [2025-02-06 19:50:47,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:47,184 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:47,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:47,185 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:47,185 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:47,185 INFO L87 Difference]: Start difference. First operand 8616 states and 12397 transitions. cyclomatic complexity: 3787 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,276 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:47,276 INFO L93 Difference]: Finished difference Result 9482 states and 13607 transitions. [2025-02-06 19:50:47,276 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9482 states and 13607 transitions. [2025-02-06 19:50:47,299 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6032 [2025-02-06 19:50:47,313 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9482 states to 9482 states and 13607 transitions. [2025-02-06 19:50:47,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6282 [2025-02-06 19:50:47,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6282 [2025-02-06 19:50:47,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9482 states and 13607 transitions. [2025-02-06 19:50:47,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:47,316 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9482 states and 13607 transitions. [2025-02-06 19:50:47,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9482 states and 13607 transitions. [2025-02-06 19:50:47,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9482 to 8616. [2025-02-06 19:50:47,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8616 states, 8616 states have (on average 1.432799442896936) internal successors, (12345), 8615 states have internal predecessors, (12345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,380 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8616 states to 8616 states and 12345 transitions. [2025-02-06 19:50:47,380 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12345 transitions. [2025-02-06 19:50:47,380 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:47,380 INFO L432 stractBuchiCegarLoop]: Abstraction has 8616 states and 12345 transitions. [2025-02-06 19:50:47,381 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-02-06 19:50:47,381 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8616 states and 12345 transitions. [2025-02-06 19:50:47,398 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-02-06 19:50:47,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:47,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:47,399 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,400 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,400 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,401 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 1 times [2025-02-06 19:50:47,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,401 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982343595] [2025-02-06 19:50:47,401 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:47,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,406 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:47,409 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:47,409 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,409 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:47,409 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:47,412 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:47,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:47,415 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,415 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:47,425 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:47,425 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,425 INFO L85 PathProgramCache]: Analyzing trace with hash -1525146528, now seen corresponding path program 1 times [2025-02-06 19:50:47,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435803484] [2025-02-06 19:50:47,426 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:47,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,433 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 178 statements into 1 equivalence classes. [2025-02-06 19:50:47,435 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-02-06 19:50:47,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:47,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:47,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:47,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435803484] [2025-02-06 19:50:47,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435803484] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:47,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:47,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:47,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [406792778] [2025-02-06 19:50:47,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:47,455 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:47,455 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:47,456 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:47,456 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:47,456 INFO L87 Difference]: Start difference. First operand 8616 states and 12345 transitions. cyclomatic complexity: 3735 Second operand has 3 states, 3 states have (on average 59.333333333333336) internal successors, (178), 3 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:47,483 INFO L93 Difference]: Finished difference Result 8616 states and 12327 transitions. [2025-02-06 19:50:47,483 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8616 states and 12327 transitions. [2025-02-06 19:50:47,502 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-02-06 19:50:47,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8616 states to 8616 states and 12327 transitions. [2025-02-06 19:50:47,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5718 [2025-02-06 19:50:47,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5718 [2025-02-06 19:50:47,517 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8616 states and 12327 transitions. [2025-02-06 19:50:47,517 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:47,517 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12327 transitions. [2025-02-06 19:50:47,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8616 states and 12327 transitions. [2025-02-06 19:50:47,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8616 to 8616. [2025-02-06 19:50:47,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8616 states, 8616 states have (on average 1.4307103064066853) internal successors, (12327), 8615 states have internal predecessors, (12327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,685 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8616 states to 8616 states and 12327 transitions. [2025-02-06 19:50:47,685 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12327 transitions. [2025-02-06 19:50:47,686 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:47,686 INFO L432 stractBuchiCegarLoop]: Abstraction has 8616 states and 12327 transitions. [2025-02-06 19:50:47,686 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-02-06 19:50:47,686 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8616 states and 12327 transitions. [2025-02-06 19:50:47,700 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-02-06 19:50:47,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:47,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:47,701 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,701 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:47,701 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,702 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:47,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 2 times [2025-02-06 19:50:47,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [953932651] [2025-02-06 19:50:47,704 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:47,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,709 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:47,713 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:47,713 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:47,714 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:47,714 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:47,717 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:47,719 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:47,719 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,719 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:47,730 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:47,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:47,730 INFO L85 PathProgramCache]: Analyzing trace with hash -1786134912, now seen corresponding path program 1 times [2025-02-06 19:50:47,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:47,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [833228679] [2025-02-06 19:50:47,731 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:47,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:47,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:47,739 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:47,739 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:47,739 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:47,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:47,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:47,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [833228679] [2025-02-06 19:50:47,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [833228679] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:47,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:47,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:47,800 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009252414] [2025-02-06 19:50:47,800 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:47,801 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:47,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:47,802 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:47,802 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:47,802 INFO L87 Difference]: Start difference. First operand 8616 states and 12327 transitions. cyclomatic complexity: 3717 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:47,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:47,876 INFO L93 Difference]: Finished difference Result 17227 states and 24483 transitions. [2025-02-06 19:50:47,876 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17227 states and 24483 transitions. [2025-02-06 19:50:47,925 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11136 [2025-02-06 19:50:47,958 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17227 states to 17227 states and 24483 transitions. [2025-02-06 19:50:47,958 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11431 [2025-02-06 19:50:47,965 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11431 [2025-02-06 19:50:47,966 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17227 states and 24483 transitions. [2025-02-06 19:50:47,966 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:47,966 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17227 states and 24483 transitions. [2025-02-06 19:50:47,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17227 states and 24483 transitions. [2025-02-06 19:50:48,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17227 to 17227. [2025-02-06 19:50:48,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17227 states, 17227 states have (on average 1.4211992801996864) internal successors, (24483), 17226 states have internal predecessors, (24483), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:48,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17227 states to 17227 states and 24483 transitions. [2025-02-06 19:50:48,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17227 states and 24483 transitions. [2025-02-06 19:50:48,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:48,106 INFO L432 stractBuchiCegarLoop]: Abstraction has 17227 states and 24483 transitions. [2025-02-06 19:50:48,106 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-02-06 19:50:48,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17227 states and 24483 transitions. [2025-02-06 19:50:48,142 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 11136 [2025-02-06 19:50:48,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:48,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:48,144 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:48,144 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:48,144 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:48,144 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:48,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:48,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 3 times [2025-02-06 19:50:48,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:48,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1925273485] [2025-02-06 19:50:48,145 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:50:48,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:48,150 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:48,152 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:48,152 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:50:48,152 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:48,152 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:48,155 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:48,157 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:48,157 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:48,158 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:48,166 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:48,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:48,167 INFO L85 PathProgramCache]: Analyzing trace with hash 404569728, now seen corresponding path program 1 times [2025-02-06 19:50:48,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:48,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052832503] [2025-02-06 19:50:48,168 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:48,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:48,175 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:48,177 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:48,177 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:48,178 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:48,303 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:48,303 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:48,303 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052832503] [2025-02-06 19:50:48,303 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052832503] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:48,303 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:48,303 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:48,303 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [34744914] [2025-02-06 19:50:48,303 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:48,304 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:48,304 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:48,304 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:48,304 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:48,304 INFO L87 Difference]: Start difference. First operand 17227 states and 24483 transitions. cyclomatic complexity: 7262 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:48,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:48,419 INFO L93 Difference]: Finished difference Result 34443 states and 48621 transitions. [2025-02-06 19:50:48,419 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34443 states and 48621 transitions. [2025-02-06 19:50:48,555 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 22272 [2025-02-06 19:50:48,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34443 states to 34443 states and 48621 transitions. [2025-02-06 19:50:48,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22851 [2025-02-06 19:50:48,661 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22851 [2025-02-06 19:50:48,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34443 states and 48621 transitions. [2025-02-06 19:50:48,662 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:48,662 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34443 states and 48621 transitions. [2025-02-06 19:50:48,682 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34443 states and 48621 transitions. [2025-02-06 19:50:48,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34443 to 34443. [2025-02-06 19:50:48,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34443 states, 34443 states have (on average 1.4116366170194234) internal successors, (48621), 34442 states have internal predecessors, (48621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:49,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34443 states to 34443 states and 48621 transitions. [2025-02-06 19:50:49,026 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34443 states and 48621 transitions. [2025-02-06 19:50:49,026 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:49,026 INFO L432 stractBuchiCegarLoop]: Abstraction has 34443 states and 48621 transitions. [2025-02-06 19:50:49,027 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-02-06 19:50:49,027 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34443 states and 48621 transitions. [2025-02-06 19:50:49,121 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 22272 [2025-02-06 19:50:49,122 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:49,122 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:49,124 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:49,124 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:49,124 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:49,124 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:49,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:49,125 INFO L85 PathProgramCache]: Analyzing trace with hash 1147926494, now seen corresponding path program 1 times [2025-02-06 19:50:49,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:49,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [314888204] [2025-02-06 19:50:49,125 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:49,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:49,131 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:49,134 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:49,134 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:49,134 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:49,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:49,171 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:49,171 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [314888204] [2025-02-06 19:50:49,171 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [314888204] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:49,171 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:49,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:49,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [202960981] [2025-02-06 19:50:49,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:49,171 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:49,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:49,172 INFO L85 PathProgramCache]: Analyzing trace with hash 890879616, now seen corresponding path program 1 times [2025-02-06 19:50:49,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:49,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198399337] [2025-02-06 19:50:49,172 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:49,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:49,179 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:49,182 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:49,182 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:49,182 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:49,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:49,317 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:49,317 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198399337] [2025-02-06 19:50:49,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198399337] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:49,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:49,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:49,317 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1921908496] [2025-02-06 19:50:49,317 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:49,318 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:49,318 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:49,318 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:49,318 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:49,318 INFO L87 Difference]: Start difference. First operand 34443 states and 48621 transitions. cyclomatic complexity: 14184 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:49,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:49,493 INFO L93 Difference]: Finished difference Result 48167 states and 67157 transitions. [2025-02-06 19:50:49,493 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48167 states and 67157 transitions. [2025-02-06 19:50:49,643 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 29576 [2025-02-06 19:50:49,746 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48167 states to 48167 states and 67157 transitions. [2025-02-06 19:50:49,746 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30539 [2025-02-06 19:50:49,767 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30539 [2025-02-06 19:50:49,767 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48167 states and 67157 transitions. [2025-02-06 19:50:49,768 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:49,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48167 states and 67157 transitions. [2025-02-06 19:50:49,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48167 states and 67157 transitions. [2025-02-06 19:50:50,019 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48167 to 35767. [2025-02-06 19:50:50,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 35767 states, 35767 states have (on average 1.3980764391757765) internal successors, (50005), 35766 states have internal predecessors, (50005), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:50,310 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 35767 states to 35767 states and 50005 transitions. [2025-02-06 19:50:50,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 35767 states and 50005 transitions. [2025-02-06 19:50:50,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:50:50,311 INFO L432 stractBuchiCegarLoop]: Abstraction has 35767 states and 50005 transitions. [2025-02-06 19:50:50,311 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-02-06 19:50:50,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 35767 states and 50005 transitions. [2025-02-06 19:50:50,381 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 23656 [2025-02-06 19:50:50,382 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:50,382 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:50,383 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:50,383 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:50,383 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:50,383 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:50,384 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:50,384 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 4 times [2025-02-06 19:50:50,384 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:50,384 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [779767191] [2025-02-06 19:50:50,384 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:50:50,384 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:50,388 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 89 statements into 2 equivalence classes. [2025-02-06 19:50:50,394 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:50,394 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:50:50,394 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:50,394 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:50,396 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:50,399 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:50,399 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:50,399 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:50,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:50,407 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:50,407 INFO L85 PathProgramCache]: Analyzing trace with hash 890879616, now seen corresponding path program 2 times [2025-02-06 19:50:50,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:50,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [293844488] [2025-02-06 19:50:50,407 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:50,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:50,414 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:50,417 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:50,417 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:50,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:50,446 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:50,447 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:50,447 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [293844488] [2025-02-06 19:50:50,447 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [293844488] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:50,447 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:50,447 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:50,447 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2138385316] [2025-02-06 19:50:50,447 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:50,447 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:50,447 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:50,448 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:50,448 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:50,448 INFO L87 Difference]: Start difference. First operand 35767 states and 50005 transitions. cyclomatic complexity: 14244 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:50,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:50,617 INFO L93 Difference]: Finished difference Result 71511 states and 99193 transitions. [2025-02-06 19:50:50,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71511 states and 99193 transitions. [2025-02-06 19:50:50,872 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 47312 [2025-02-06 19:50:51,026 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71511 states to 71511 states and 99193 transitions. [2025-02-06 19:50:51,026 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48575 [2025-02-06 19:50:51,058 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48575 [2025-02-06 19:50:51,059 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71511 states and 99193 transitions. [2025-02-06 19:50:51,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-02-06 19:50:51,076 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71511 states and 99193 transitions. [2025-02-06 19:50:51,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71511 states and 99193 transitions. [2025-02-06 19:50:51,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71511 to 71511. [2025-02-06 19:50:51,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 71511 states, 71511 states have (on average 1.387101285116975) internal successors, (99193), 71510 states have internal predecessors, (99193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:51,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 71511 states to 71511 states and 99193 transitions. [2025-02-06 19:50:51,907 INFO L240 hiAutomatonCegarLoop]: Abstraction has 71511 states and 99193 transitions. [2025-02-06 19:50:51,907 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:51,908 INFO L432 stractBuchiCegarLoop]: Abstraction has 71511 states and 99193 transitions. [2025-02-06 19:50:51,908 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-02-06 19:50:51,908 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 71511 states and 99193 transitions. [2025-02-06 19:50:52,298 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 47312 [2025-02-06 19:50:52,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:52,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:52,301 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:52,301 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:52,301 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:52,302 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:52,302 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:52,302 INFO L85 PathProgramCache]: Analyzing trace with hash -1319069636, now seen corresponding path program 1 times [2025-02-06 19:50:52,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:52,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1200966895] [2025-02-06 19:50:52,302 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:52,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:52,308 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:52,311 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:52,312 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:52,312 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:52,352 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:52,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:52,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1200966895] [2025-02-06 19:50:52,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1200966895] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:52,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:52,353 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:50:52,353 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851631203] [2025-02-06 19:50:52,353 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:52,353 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:50:52,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:52,354 INFO L85 PathProgramCache]: Analyzing trace with hash 1183661696, now seen corresponding path program 1 times [2025-02-06 19:50:52,354 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:52,354 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447534953] [2025-02-06 19:50:52,354 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:52,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:52,361 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:52,363 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:52,363 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:52,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:52,398 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:52,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:52,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447534953] [2025-02-06 19:50:52,399 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447534953] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:52,399 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:52,399 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:52,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1678713391] [2025-02-06 19:50:52,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:52,399 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:52,399 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:52,400 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:50:52,400 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:50:52,400 INFO L87 Difference]: Start difference. First operand 71511 states and 99193 transitions. cyclomatic complexity: 27688 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:52,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:52,791 INFO L93 Difference]: Finished difference Result 79711 states and 109213 transitions. [2025-02-06 19:50:52,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79711 states and 109213 transitions. [2025-02-06 19:50:53,123 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 52448 [2025-02-06 19:50:53,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79711 states to 54607 states and 74877 transitions. [2025-02-06 19:50:53,288 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 54607 [2025-02-06 19:50:53,329 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 54607 [2025-02-06 19:50:53,329 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54607 states and 74877 transitions. [2025-02-06 19:50:53,391 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:53,392 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54607 states and 74877 transitions. [2025-02-06 19:50:53,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54607 states and 74877 transitions. [2025-02-06 19:50:54,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54607 to 29623. [2025-02-06 19:50:54,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29623 states, 29623 states have (on average 1.370725449819397) internal successors, (40605), 29622 states have internal predecessors, (40605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:54,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29623 states to 29623 states and 40605 transitions. [2025-02-06 19:50:54,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29623 states and 40605 transitions. [2025-02-06 19:50:54,055 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:50:54,056 INFO L432 stractBuchiCegarLoop]: Abstraction has 29623 states and 40605 transitions. [2025-02-06 19:50:54,056 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-02-06 19:50:54,056 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29623 states and 40605 transitions. [2025-02-06 19:50:54,142 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28320 [2025-02-06 19:50:54,143 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:54,143 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:54,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:54,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:54,146 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:54,146 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:54,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:54,147 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 5 times [2025-02-06 19:50:54,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:54,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619929975] [2025-02-06 19:50:54,147 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:50:54,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:54,152 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:54,154 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:54,155 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:54,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:54,155 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:54,157 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:54,159 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:54,159 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:54,159 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:54,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:54,168 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:54,168 INFO L85 PathProgramCache]: Analyzing trace with hash 1183661696, now seen corresponding path program 2 times [2025-02-06 19:50:54,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:54,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325765398] [2025-02-06 19:50:54,169 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:50:54,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:54,175 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:54,177 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:54,177 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:50:54,177 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:54,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:54,202 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:54,202 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325765398] [2025-02-06 19:50:54,202 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325765398] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:54,202 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:54,202 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:54,202 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139312040] [2025-02-06 19:50:54,202 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:54,202 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:54,202 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:54,203 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:54,203 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:54,203 INFO L87 Difference]: Start difference. First operand 29623 states and 40605 transitions. cyclomatic complexity: 10984 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:54,348 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:54,348 INFO L93 Difference]: Finished difference Result 59199 states and 80237 transitions. [2025-02-06 19:50:54,348 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59199 states and 80237 transitions. [2025-02-06 19:50:54,585 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640 [2025-02-06 19:50:54,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59199 states to 59199 states and 80237 transitions. [2025-02-06 19:50:54,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59199 [2025-02-06 19:50:54,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59199 [2025-02-06 19:50:54,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59199 states and 80237 transitions. [2025-02-06 19:50:55,135 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:55,135 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-02-06 19:50:55,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59199 states and 80237 transitions. [2025-02-06 19:50:55,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59199 to 59199. [2025-02-06 19:50:55,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59199 states, 59199 states have (on average 1.3553776246220375) internal successors, (80237), 59198 states have internal predecessors, (80237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:55,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59199 states to 59199 states and 80237 transitions. [2025-02-06 19:50:55,556 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-02-06 19:50:55,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:55,556 INFO L432 stractBuchiCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-02-06 19:50:55,557 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-02-06 19:50:55,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59199 states and 80237 transitions. [2025-02-06 19:50:55,716 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640 [2025-02-06 19:50:55,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:55,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:55,721 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:55,721 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:55,721 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:55,722 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:55,722 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:55,722 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 6 times [2025-02-06 19:50:55,722 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:55,722 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2139449084] [2025-02-06 19:50:55,722 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:50:55,723 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:55,727 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:55,729 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:55,730 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:50:55,730 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:55,730 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:55,731 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:55,733 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:55,733 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:55,733 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:55,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:55,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:55,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1322455679, now seen corresponding path program 1 times [2025-02-06 19:50:55,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:55,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136022056] [2025-02-06 19:50:55,740 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:55,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:55,745 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:55,746 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:55,746 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:55,746 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:55,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:55,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:55,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136022056] [2025-02-06 19:50:55,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136022056] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:55,765 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:55,765 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:55,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1647534745] [2025-02-06 19:50:55,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:55,766 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:55,766 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:55,766 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:55,766 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:55,766 INFO L87 Difference]: Start difference. First operand 59199 states and 80237 transitions. cyclomatic complexity: 21040 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:56,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:56,296 INFO L93 Difference]: Finished difference Result 118207 states and 158749 transitions. [2025-02-06 19:50:56,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118207 states and 158749 transitions. [2025-02-06 19:50:56,782 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 113280 [2025-02-06 19:50:57,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118207 states to 118207 states and 158749 transitions. [2025-02-06 19:50:57,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118207 [2025-02-06 19:50:57,143 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118207 [2025-02-06 19:50:57,143 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118207 states and 158749 transitions. [2025-02-06 19:50:57,541 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:50:57,541 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-02-06 19:50:57,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118207 states and 158749 transitions. [2025-02-06 19:50:58,484 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118207 to 118207. [2025-02-06 19:50:58,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118207 states, 118207 states have (on average 1.342974612332603) internal successors, (158749), 118206 states have internal predecessors, (158749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:59,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118207 states to 118207 states and 158749 transitions. [2025-02-06 19:50:59,080 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-02-06 19:50:59,080 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:50:59,080 INFO L432 stractBuchiCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-02-06 19:50:59,080 INFO L338 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2025-02-06 19:50:59,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118207 states and 158749 transitions. [2025-02-06 19:50:59,401 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 113280 [2025-02-06 19:50:59,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:50:59,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:50:59,412 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:59,413 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:50:59,413 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:59,413 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:50:59,413 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:59,413 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 7 times [2025-02-06 19:50:59,414 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:59,414 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1735769095] [2025-02-06 19:50:59,414 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:50:59,414 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:59,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:59,419 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:59,420 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:59,420 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:59,420 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:50:59,421 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:50:59,423 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:50:59,423 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:59,423 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:50:59,429 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:50:59,430 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:50:59,430 INFO L85 PathProgramCache]: Analyzing trace with hash 1578078847, now seen corresponding path program 1 times [2025-02-06 19:50:59,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:50:59,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698445960] [2025-02-06 19:50:59,430 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:50:59,430 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:50:59,435 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:50:59,437 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:50:59,437 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:50:59,437 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:50:59,455 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:50:59,455 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:50:59,455 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698445960] [2025-02-06 19:50:59,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698445960] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:50:59,455 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:50:59,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:50:59,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [117966332] [2025-02-06 19:50:59,455 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:50:59,456 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:50:59,456 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:50:59,456 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:50:59,456 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:50:59,456 INFO L87 Difference]: Start difference. First operand 118207 states and 158749 transitions. cyclomatic complexity: 40544 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:50:59,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:50:59,855 INFO L93 Difference]: Finished difference Result 209343 states and 282429 transitions. [2025-02-06 19:50:59,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 209343 states and 282429 transitions. [2025-02-06 19:51:01,012 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204416 [2025-02-06 19:51:01,817 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 209343 states to 209343 states and 282429 transitions. [2025-02-06 19:51:01,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209343 [2025-02-06 19:51:01,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209343 [2025-02-06 19:51:01,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209343 states and 282429 transitions. [2025-02-06 19:51:01,957 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:51:01,957 INFO L218 hiAutomatonCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-02-06 19:51:02,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209343 states and 282429 transitions. [2025-02-06 19:51:03,451 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209343 to 209343. [2025-02-06 19:51:03,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209343 states, 209343 states have (on average 1.3491208208538141) internal successors, (282429), 209342 states have internal predecessors, (282429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:04,441 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209343 states to 209343 states and 282429 transitions. [2025-02-06 19:51:04,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-02-06 19:51:04,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:51:04,441 INFO L432 stractBuchiCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-02-06 19:51:04,442 INFO L338 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2025-02-06 19:51:04,442 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209343 states and 282429 transitions. [2025-02-06 19:51:04,980 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204416 [2025-02-06 19:51:04,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:51:04,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:51:04,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:04,997 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:04,997 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:04,997 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:04,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:04,998 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 8 times [2025-02-06 19:51:04,998 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:04,998 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672187236] [2025-02-06 19:51:04,998 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:51:04,998 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:05,002 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:51:05,004 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:05,004 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:51:05,004 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:05,004 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:51:05,006 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:51:05,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:05,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:05,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:05,014 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:51:05,015 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:05,015 INFO L85 PathProgramCache]: Analyzing trace with hash 1701820031, now seen corresponding path program 1 times [2025-02-06 19:51:05,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:05,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1767380577] [2025-02-06 19:51:05,015 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:51:05,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:05,020 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-02-06 19:51:05,022 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-02-06 19:51:05,022 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:05,022 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:51:05,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:51:05,059 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:51:05,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1767380577] [2025-02-06 19:51:05,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1767380577] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:51:05,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:51:05,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:51:05,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634215404] [2025-02-06 19:51:05,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:51:05,059 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:51:05,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:51:05,060 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:51:05,060 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:51:05,060 INFO L87 Difference]: Start difference. First operand 209343 states and 282429 transitions. cyclomatic complexity: 73088 Second operand has 5 states, 5 states have (on average 36.4) internal successors, (182), 5 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:05,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:51:05,950 INFO L93 Difference]: Finished difference Result 216511 states and 293485 transitions. [2025-02-06 19:51:05,950 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216511 states and 293485 transitions. [2025-02-06 19:51:06,728 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 211584 [2025-02-06 19:51:07,601 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216511 states to 216511 states and 293485 transitions. [2025-02-06 19:51:07,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216511 [2025-02-06 19:51:07,698 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216511 [2025-02-06 19:51:07,698 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216511 states and 293485 transitions. [2025-02-06 19:51:07,779 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:51:07,779 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216511 states and 293485 transitions. [2025-02-06 19:51:07,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216511 states and 293485 transitions. [2025-02-06 19:51:09,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216511 to 195487. [2025-02-06 19:51:09,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 195487 states, 195487 states have (on average 1.3523405648457443) internal successors, (264365), 195486 states have internal predecessors, (264365), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:09,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195487 states to 195487 states and 264365 transitions. [2025-02-06 19:51:09,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 195487 states and 264365 transitions. [2025-02-06 19:51:09,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-06 19:51:09,628 INFO L432 stractBuchiCegarLoop]: Abstraction has 195487 states and 264365 transitions. [2025-02-06 19:51:09,628 INFO L338 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2025-02-06 19:51:09,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 195487 states and 264365 transitions. [2025-02-06 19:51:10,700 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190560 [2025-02-06 19:51:10,700 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:51:10,700 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:51:10,714 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:10,714 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:10,715 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:10,715 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume !(1 == ~main_clk_val~0);~main_clk_neg_edge~0 := 0;~main_clk_pos_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:10,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:10,715 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 9 times [2025-02-06 19:51:10,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:10,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053645232] [2025-02-06 19:51:10,715 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:51:10,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:10,720 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:51:10,722 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:10,722 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:51:10,722 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:10,722 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:51:10,723 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:51:10,725 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:10,725 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:10,725 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:10,731 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:51:10,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:10,732 INFO L85 PathProgramCache]: Analyzing trace with hash 1917271841, now seen corresponding path program 1 times [2025-02-06 19:51:10,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:10,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71797534] [2025-02-06 19:51:10,732 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:51:10,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:10,737 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 183 statements into 1 equivalence classes. [2025-02-06 19:51:10,739 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 183 of 183 statements. [2025-02-06 19:51:10,739 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:10,739 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:51:10,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:51:10,752 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:51:10,752 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [71797534] [2025-02-06 19:51:10,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [71797534] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:51:10,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:51:10,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:51:10,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266457030] [2025-02-06 19:51:10,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:51:10,753 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:51:10,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:51:10,753 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:51:10,754 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:51:10,754 INFO L87 Difference]: Start difference. First operand 195487 states and 264365 transitions. cyclomatic complexity: 68880 Second operand has 3 states, 3 states have (on average 61.0) internal successors, (183), 3 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:10,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:51:10,988 INFO L93 Difference]: Finished difference Result 117247 states and 156589 transitions. [2025-02-06 19:51:10,988 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 117247 states and 156589 transitions. [2025-02-06 19:51:11,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 112320 [2025-02-06 19:51:12,123 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 117247 states to 117247 states and 156589 transitions. [2025-02-06 19:51:12,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 117247 [2025-02-06 19:51:12,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 117247 [2025-02-06 19:51:12,159 INFO L73 IsDeterministic]: Start isDeterministic. Operand 117247 states and 156589 transitions. [2025-02-06 19:51:12,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:51:12,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 117247 states and 156589 transitions. [2025-02-06 19:51:12,238 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117247 states and 156589 transitions. [2025-02-06 19:51:12,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117247 to 117247. [2025-02-06 19:51:12,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117247 states, 117247 states have (on average 1.3355480310796866) internal successors, (156589), 117246 states have internal predecessors, (156589), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:13,534 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117247 states to 117247 states and 156589 transitions. [2025-02-06 19:51:13,534 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117247 states and 156589 transitions. [2025-02-06 19:51:13,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:51:13,535 INFO L432 stractBuchiCegarLoop]: Abstraction has 117247 states and 156589 transitions. [2025-02-06 19:51:13,535 INFO L338 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2025-02-06 19:51:13,535 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117247 states and 156589 transitions. [2025-02-06 19:51:13,816 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 112320 [2025-02-06 19:51:13,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:51:13,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:51:13,825 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:13,825 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:51:13,825 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:13,826 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume !(1 == ~main_clk_val~0);~main_clk_neg_edge~0 := 0;~main_clk_pos_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-02-06 19:51:13,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:13,826 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 10 times [2025-02-06 19:51:13,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:13,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552877310] [2025-02-06 19:51:13,826 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:51:13,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:13,831 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 89 statements into 2 equivalence classes. [2025-02-06 19:51:13,833 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:13,833 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:51:13,833 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:13,833 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:51:13,835 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:51:13,837 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:51:13,838 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:13,838 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:51:13,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:51:13,845 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:51:13,846 INFO L85 PathProgramCache]: Analyzing trace with hash 404500963, now seen corresponding path program 1 times [2025-02-06 19:51:13,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:51:13,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1596041113] [2025-02-06 19:51:13,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:51:13,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:51:13,851 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 183 statements into 1 equivalence classes. [2025-02-06 19:51:13,853 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 183 of 183 statements. [2025-02-06 19:51:13,853 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:51:13,853 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:51:13,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:51:13,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:51:13,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1596041113] [2025-02-06 19:51:13,867 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1596041113] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:51:13,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:51:13,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:51:13,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1606969516] [2025-02-06 19:51:13,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:51:13,868 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:51:13,868 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:51:13,868 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:51:13,868 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:51:13,868 INFO L87 Difference]: Start difference. First operand 117247 states and 156589 transitions. cyclomatic complexity: 39344 Second operand has 3 states, 3 states have (on average 61.0) internal successors, (183), 3 states have internal predecessors, (183), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:51:14,110 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:51:14,111 INFO L93 Difference]: Finished difference Result 111679 states and 149325 transitions. [2025-02-06 19:51:14,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111679 states and 149325 transitions. [2025-02-06 19:51:14,563 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 106752 [2025-02-06 19:51:15,288 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111679 states to 111679 states and 149325 transitions. [2025-02-06 19:51:15,289 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111679 [2025-02-06 19:51:15,339 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111679 [2025-02-06 19:51:15,339 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111679 states and 149325 transitions. [2025-02-06 19:51:15,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:51:15,394 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111679 states and 149325 transitions. [2025-02-06 19:51:15,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111679 states and 149325 transitions.