./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:09:01,349 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:09:01,392 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:09:01,395 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:09:01,395 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:09:01,395 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:09:01,409 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:09:01,410 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:09:01,410 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:09:01,410 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:09:01,410 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:09:01,410 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:09:01,411 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:09:01,411 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:09:01,411 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:09:01,412 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:09:01,412 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:09:01,414 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:09:01,414 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2025-02-06 19:09:01,645 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:09:01,650 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:09:01,651 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:09:01,652 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:09:01,652 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:09:01,653 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-02-06 19:09:02,838 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/0760906af/2aca61ac6cbf405cb20f1e9ecdc1dd79/FLAGc63a0c9f8 [2025-02-06 19:09:03,103 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:09:03,120 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-02-06 19:09:03,132 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/0760906af/2aca61ac6cbf405cb20f1e9ecdc1dd79/FLAGc63a0c9f8 [2025-02-06 19:09:03,419 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/0760906af/2aca61ac6cbf405cb20f1e9ecdc1dd79 [2025-02-06 19:09:03,425 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:09:03,426 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:09:03,426 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:09:03,426 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:09:03,433 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:09:03,433 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,434 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d25dcd5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03, skipping insertion in model container [2025-02-06 19:09:03,437 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,454 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:09:03,574 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:09:03,581 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:09:03,593 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:09:03,603 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:09:03,603 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03 WrapperNode [2025-02-06 19:09:03,604 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:09:03,608 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:09:03,608 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:09:03,608 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:09:03,616 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,620 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,630 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 69 [2025-02-06 19:09:03,630 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:09:03,631 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:09:03,631 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:09:03,631 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:09:03,636 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,636 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,637 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,644 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2025-02-06 19:09:03,644 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,645 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,648 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,652 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,653 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,653 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,654 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:09:03,658 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:09:03,658 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:09:03,658 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:09:03,658 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (1/1) ... [2025-02-06 19:09:03,664 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:03,672 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:03,686 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:03,688 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-02-06 19:09:03,705 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-02-06 19:09:03,706 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:09:03,706 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:09:03,707 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-02-06 19:09:03,707 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-02-06 19:09:03,707 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-02-06 19:09:03,758 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:09:03,760 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:09:03,891 INFO L1309 $ProcedureCfgBuilder]: dead code at ProgramPoint L23: call ULTIMATE.dealloc(main_~#array~0#1.base, main_~#array~0#1.offset);havoc main_~#array~0#1.base, main_~#array~0#1.offset; [2025-02-06 19:09:03,900 INFO L? ?]: Removed 16 outVars from TransFormulas that were not future-live. [2025-02-06 19:09:03,900 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:09:03,909 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:09:03,910 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:09:03,910 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:09:03 BoogieIcfgContainer [2025-02-06 19:09:03,910 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:09:03,911 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:09:03,911 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:09:03,915 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:09:03,915 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:09:03,916 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:09:03" (1/3) ... [2025-02-06 19:09:03,916 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ad3f0bf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:09:03, skipping insertion in model container [2025-02-06 19:09:03,917 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:09:03,917 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:09:03" (2/3) ... [2025-02-06 19:09:03,917 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5ad3f0bf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:09:03, skipping insertion in model container [2025-02-06 19:09:03,917 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:09:03,917 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:09:03" (3/3) ... [2025-02-06 19:09:03,918 INFO L363 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2025-02-06 19:09:03,954 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:09:03,955 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:09:03,956 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:09:03,956 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:09:03,956 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:09:03,956 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:09:03,956 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:09:03,956 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:09:03,961 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:03,973 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-02-06 19:09:03,973 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:03,973 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:03,976 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:09:03,976 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-02-06 19:09:03,976 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:09:03,976 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:03,978 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 19 [2025-02-06 19:09:03,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:03,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:03,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:09:03,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-02-06 19:09:03,983 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" [2025-02-06 19:09:03,983 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" [2025-02-06 19:09:03,988 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:03,989 INFO L85 PathProgramCache]: Analyzing trace with hash 1984, now seen corresponding path program 1 times [2025-02-06 19:09:03,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:03,993 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92073126] [2025-02-06 19:09:03,993 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:03,993 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:04,037 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:09:04,047 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:09:04,047 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,048 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,048 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:04,050 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:09:04,052 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:09:04,052 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,052 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,064 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:04,071 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:04,071 INFO L85 PathProgramCache]: Analyzing trace with hash 61, now seen corresponding path program 1 times [2025-02-06 19:09:04,072 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:04,072 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136389285] [2025-02-06 19:09:04,072 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:04,072 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:04,081 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-06 19:09:04,088 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-06 19:09:04,091 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,091 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,092 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:04,093 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-06 19:09:04,099 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-06 19:09:04,099 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:04,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:04,103 INFO L85 PathProgramCache]: Analyzing trace with hash 61534, now seen corresponding path program 1 times [2025-02-06 19:09:04,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:04,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550471594] [2025-02-06 19:09:04,104 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:04,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:04,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:04,117 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:04,117 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,117 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,117 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:04,119 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:04,123 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:04,123 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:04,123 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:04,125 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:04,385 INFO L204 LassoAnalysis]: Preferences: [2025-02-06 19:09:04,385 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-06 19:09:04,385 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-06 19:09:04,386 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-06 19:09:04,386 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-02-06 19:09:04,386 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,386 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-06 19:09:04,386 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-06 19:09:04,386 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2025-02-06 19:09:04,386 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-06 19:09:04,386 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-06 19:09:04,395 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,413 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,419 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-06 19:09:04,696 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-06 19:09:04,698 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-02-06 19:09:04,699 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,699 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,701 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,703 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-02-06 19:09:04,704 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,715 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,715 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,715 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,716 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,716 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,718 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,718 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,720 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,726 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,726 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,727 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,730 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,731 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-02-06 19:09:04,731 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,741 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,741 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,741 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,741 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,744 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:04,744 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:04,747 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,753 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-02-06 19:09:04,753 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,753 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,755 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,757 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-02-06 19:09:04,758 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,768 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,768 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,768 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,768 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,770 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:04,770 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:04,773 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,778 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,779 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,779 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,784 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,785 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-02-06 19:09:04,786 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,796 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,796 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,796 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,796 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,796 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,797 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,797 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,798 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,803 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,804 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,804 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,805 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,806 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-02-06 19:09:04,811 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,821 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,822 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,822 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,822 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,822 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,822 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,822 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,824 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,829 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-02-06 19:09:04,829 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,829 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,831 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,834 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-02-06 19:09:04,834 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,844 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,845 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,845 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,845 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,845 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,845 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,845 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,846 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,856 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-02-06 19:09:04,856 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,856 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,858 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,859 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-02-06 19:09:04,860 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,870 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,870 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,871 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,871 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,871 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,871 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,872 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,878 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,879 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,884 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,886 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-02-06 19:09:04,886 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,896 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,897 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,897 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,897 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,899 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:04,899 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:04,902 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,909 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,909 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,915 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,916 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-02-06 19:09:04,917 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,927 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,928 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-06 19:09:04,928 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,928 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,928 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,928 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-06 19:09:04,928 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-06 19:09:04,932 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,937 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,938 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,938 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,940 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,942 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,942 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-02-06 19:09:04,952 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,952 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,952 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,952 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,954 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:04,954 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:04,957 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,963 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,963 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,963 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,966 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,967 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-02-06 19:09:04,968 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:04,978 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:04,979 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:04,979 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:04,979 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:04,981 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:04,981 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:04,983 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:04,989 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:04,990 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:04,990 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:04,992 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:04,992 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-02-06 19:09:04,994 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:05,004 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:05,004 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:05,005 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:05,005 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:05,006 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:05,006 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:05,009 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:05,016 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:05,016 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:05,016 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,018 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,019 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-02-06 19:09:05,021 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:05,031 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:05,031 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:05,031 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:05,031 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:05,033 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:05,033 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:05,036 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:05,042 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Forceful destruction successful, exit code 0 [2025-02-06 19:09:05,042 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:05,042 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,045 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,046 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-02-06 19:09:05,047 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:05,057 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:05,057 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:05,057 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:05,057 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:05,059 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:05,059 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:05,061 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-06 19:09:05,070 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-02-06 19:09:05,070 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:05,071 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,072 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,076 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2025-02-06 19:09:05,076 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-06 19:09:05,086 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-06 19:09:05,086 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-06 19:09:05,087 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-06 19:09:05,087 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-06 19:09:05,095 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-06 19:09:05,095 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-06 19:09:05,111 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-02-06 19:09:05,157 INFO L443 ModelExtractionUtils]: Simplification made 14 calls to the SMT solver. [2025-02-06 19:09:05,159 INFO L444 ModelExtractionUtils]: 6 out of 16 variables were initially zero. Simplification set additionally 6 variables to zero. [2025-02-06 19:09:05,160 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:09:05,160 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,168 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,169 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2025-02-06 19:09:05,170 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-02-06 19:09:05,182 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-02-06 19:09:05,182 INFO L474 LassoAnalysis]: Proved termination. [2025-02-06 19:09:05,183 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~#array~0#1.offset, v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = -1*ULTIMATE.start_main_~#array~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2025-02-06 19:09:05,198 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2025-02-06 19:09:05,207 INFO L156 tatePredicateManager]: 4 out of 4 supporting invariants were superfluous and have been removed [2025-02-06 19:09:05,211 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-02-06 19:09:05,211 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-02-06 19:09:05,212 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~#array~0!offset [2025-02-06 19:09:05,224 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,231 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:09:05,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:09:05,235 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,236 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-02-06 19:09:05,236 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:05,244 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-06 19:09:05,245 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-06 19:09:05,246 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,246 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,246 INFO L256 TraceCheckSpWp]: Trace formula consists of 13 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-02-06 19:09:05,246 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:05,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,265 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2025-02-06 19:09:05,267 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,286 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 24 states, 23 states have (on average 1.391304347826087) internal successors, (32), 23 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 26 states and 36 transitions. Complement of second has 3 states. [2025-02-06 19:09:05,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2025-02-06 19:09:05,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 1.5) internal successors, (3), 2 states have internal predecessors, (3), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 3 transitions. [2025-02-06 19:09:05,294 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 1 letters. [2025-02-06 19:09:05,294 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:09:05,294 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 3 letters. Loop has 1 letters. [2025-02-06 19:09:05,294 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:09:05,294 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 3 transitions. Stem has 2 letters. Loop has 2 letters. [2025-02-06 19:09:05,294 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-06 19:09:05,295 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26 states and 36 transitions. [2025-02-06 19:09:05,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-02-06 19:09:05,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26 states to 23 states and 33 transitions. [2025-02-06 19:09:05,298 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21 [2025-02-06 19:09:05,298 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2025-02-06 19:09:05,298 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 33 transitions. [2025-02-06 19:09:05,298 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:05,298 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 33 transitions. [2025-02-06 19:09:05,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 33 transitions. [2025-02-06 19:09:05,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 22. [2025-02-06 19:09:05,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2025-02-06 19:09:05,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-02-06 19:09:05,313 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-02-06 19:09:05,313 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:09:05,313 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2025-02-06 19:09:05,314 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18 [2025-02-06 19:09:05,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:05,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:05,314 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1] [2025-02-06 19:09:05,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:05,314 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" [2025-02-06 19:09:05,314 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" [2025-02-06 19:09:05,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,315 INFO L85 PathProgramCache]: Analyzing trace with hash 61533, now seen corresponding path program 1 times [2025-02-06 19:09:05,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894074010] [2025-02-06 19:09:05,320 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,320 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,323 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,326 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,326 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,329 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,330 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,330 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,330 INFO L85 PathProgramCache]: Analyzing trace with hash 57553, now seen corresponding path program 1 times [2025-02-06 19:09:05,330 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664264246] [2025-02-06 19:09:05,331 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,331 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,336 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,336 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,336 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,337 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,338 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,341 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,341 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,342 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,342 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,342 INFO L85 PathProgramCache]: Analyzing trace with hash 1833157365, now seen corresponding path program 1 times [2025-02-06 19:09:05,342 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,342 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514042075] [2025-02-06 19:09:05,343 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,343 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,345 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-02-06 19:09:05,354 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-02-06 19:09:05,354 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,354 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:05,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514042075] [2025-02-06 19:09:05,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514042075] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:09:05,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:09:05,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:09:05,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [360052362] [2025-02-06 19:09:05,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:09:05,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:05,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:09:05,451 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:09:05,452 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.5) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:05,487 INFO L93 Difference]: Finished difference Result 38 states and 45 transitions. [2025-02-06 19:09:05,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 45 transitions. [2025-02-06 19:09:05,488 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:05,490 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 28 states and 34 transitions. [2025-02-06 19:09:05,491 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 27 [2025-02-06 19:09:05,492 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-02-06 19:09:05,492 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28 states and 34 transitions. [2025-02-06 19:09:05,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:05,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28 states and 34 transitions. [2025-02-06 19:09:05,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states and 34 transitions. [2025-02-06 19:09:05,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 17. [2025-02-06 19:09:05,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.2352941176470589) internal successors, (21), 16 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,493 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 21 transitions. [2025-02-06 19:09:05,493 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-02-06 19:09:05,494 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:09:05,495 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 21 transitions. [2025-02-06 19:09:05,495 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:09:05,495 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 21 transitions. [2025-02-06 19:09:05,495 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:05,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:05,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:05,498 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-02-06 19:09:05,498 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:05,498 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:05,498 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:05,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,498 INFO L85 PathProgramCache]: Analyzing trace with hash 59135101, now seen corresponding path program 1 times [2025-02-06 19:09:05,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124578014] [2025-02-06 19:09:05,498 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,503 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-02-06 19:09:05,514 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-02-06 19:09:05,515 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,515 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,515 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,516 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-02-06 19:09:05,521 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-02-06 19:09:05,521 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,522 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,523 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 2 times [2025-02-06 19:09:05,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1343255615] [2025-02-06 19:09:05,523 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:05,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,525 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,557 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,557 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:05,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,557 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,558 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,563 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,563 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,563 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,565 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,565 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2025-02-06 19:09:05,565 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,566 INFO L85 PathProgramCache]: Analyzing trace with hash 757229033, now seen corresponding path program 1 times [2025-02-06 19:09:05,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [658385646] [2025-02-06 19:09:05,566 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,569 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:09:05,574 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:09:05,574 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,575 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,633 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,633 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:05,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [658385646] [2025-02-06 19:09:05,633 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [658385646] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:05,633 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [588480621] [2025-02-06 19:09:05,634 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:09:05,634 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:05,634 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,636 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,637 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-02-06 19:09:05,662 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:09:05,670 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:09:05,670 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,670 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,671 INFO L256 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-02-06 19:09:05,672 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:05,706 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,707 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:05,730 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,731 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [588480621] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:05,731 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:05,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5] total 9 [2025-02-06 19:09:05,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578112772] [2025-02-06 19:09:05,731 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:05,768 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:05,768 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-06 19:09:05,768 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2025-02-06 19:09:05,769 INFO L87 Difference]: Start difference. First operand 17 states and 21 transitions. cyclomatic complexity: 7 Second operand has 10 states, 9 states have (on average 2.111111111111111) internal successors, (19), 10 states have internal predecessors, (19), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:05,831 INFO L93 Difference]: Finished difference Result 55 states and 66 transitions. [2025-02-06 19:09:05,832 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 55 states and 66 transitions. [2025-02-06 19:09:05,833 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:05,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 55 states to 41 states and 49 transitions. [2025-02-06 19:09:05,833 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39 [2025-02-06 19:09:05,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39 [2025-02-06 19:09:05,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41 states and 49 transitions. [2025-02-06 19:09:05,833 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:05,833 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41 states and 49 transitions. [2025-02-06 19:09:05,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41 states and 49 transitions. [2025-02-06 19:09:05,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41 to 24. [2025-02-06 19:09:05,835 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24 states, 24 states have (on average 1.2083333333333333) internal successors, (29), 23 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:05,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 29 transitions. [2025-02-06 19:09:05,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-02-06 19:09:05,836 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-06 19:09:05,836 INFO L432 stractBuchiCegarLoop]: Abstraction has 24 states and 29 transitions. [2025-02-06 19:09:05,836 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:09:05,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24 states and 29 transitions. [2025-02-06 19:09:05,837 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:05,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:05,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:05,837 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1] [2025-02-06 19:09:05,837 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:05,837 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:05,837 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:05,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,838 INFO L85 PathProgramCache]: Analyzing trace with hash 2028855303, now seen corresponding path program 2 times [2025-02-06 19:09:05,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678955944] [2025-02-06 19:09:05,838 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:05,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,843 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 9 statements into 2 equivalence classes. [2025-02-06 19:09:05,852 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:09:05,852 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:05,852 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,852 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,854 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:09:05,860 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:09:05,860 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,860 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,862 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,863 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 3 times [2025-02-06 19:09:05,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875512467] [2025-02-06 19:09:05,863 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:05,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,865 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,867 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,867 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:09:05,867 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,867 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:05,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:05,869 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:05,870 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:05,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:05,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:05,871 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:05,871 INFO L85 PathProgramCache]: Analyzing trace with hash -1446398433, now seen corresponding path program 3 times [2025-02-06 19:09:05,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:05,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254593605] [2025-02-06 19:09:05,871 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:05,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:05,875 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-02-06 19:09:05,882 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-02-06 19:09:05,882 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-02-06 19:09:05,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:05,958 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:05,958 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:05,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254593605] [2025-02-06 19:09:05,958 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254593605] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:05,958 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2012285315] [2025-02-06 19:09:05,958 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:05,959 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:05,959 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:05,960 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:05,964 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-02-06 19:09:05,989 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 12 statements into 3 equivalence classes. [2025-02-06 19:09:05,999 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 12 of 12 statements. [2025-02-06 19:09:05,999 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-02-06 19:09:05,999 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:06,000 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-02-06 19:09:06,000 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:06,052 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,052 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:06,087 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2012285315] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:06,088 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:06,088 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7] total 12 [2025-02-06 19:09:06,088 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [852330205] [2025-02-06 19:09:06,088 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:06,149 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:06,149 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-06 19:09:06,149 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2025-02-06 19:09:06,150 INFO L87 Difference]: Start difference. First operand 24 states and 29 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.1666666666666665) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:06,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:06,234 INFO L93 Difference]: Finished difference Result 80 states and 95 transitions. [2025-02-06 19:09:06,234 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80 states and 95 transitions. [2025-02-06 19:09:06,235 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:06,235 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80 states to 54 states and 64 transitions. [2025-02-06 19:09:06,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51 [2025-02-06 19:09:06,236 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51 [2025-02-06 19:09:06,236 INFO L73 IsDeterministic]: Start isDeterministic. Operand 54 states and 64 transitions. [2025-02-06 19:09:06,236 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:06,236 INFO L218 hiAutomatonCegarLoop]: Abstraction has 54 states and 64 transitions. [2025-02-06 19:09:06,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states and 64 transitions. [2025-02-06 19:09:06,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 31. [2025-02-06 19:09:06,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31 states, 31 states have (on average 1.1935483870967742) internal successors, (37), 30 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:06,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31 states to 31 states and 37 transitions. [2025-02-06 19:09:06,238 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-02-06 19:09:06,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-02-06 19:09:06,239 INFO L432 stractBuchiCegarLoop]: Abstraction has 31 states and 37 transitions. [2025-02-06 19:09:06,239 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:09:06,239 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31 states and 37 transitions. [2025-02-06 19:09:06,239 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:06,239 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:06,239 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:06,240 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1] [2025-02-06 19:09:06,240 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:06,240 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:06,240 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:06,240 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,240 INFO L85 PathProgramCache]: Analyzing trace with hash -789647043, now seen corresponding path program 4 times [2025-02-06 19:09:06,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467156174] [2025-02-06 19:09:06,241 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:06,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,246 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 13 statements into 2 equivalence classes. [2025-02-06 19:09:06,256 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 13 of 13 statements. [2025-02-06 19:09:06,256 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:06,256 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,256 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:06,258 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-02-06 19:09:06,270 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-02-06 19:09:06,270 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,270 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,273 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:06,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,273 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 4 times [2025-02-06 19:09:06,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527284204] [2025-02-06 19:09:06,273 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:06,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,275 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-06 19:09:06,277 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:06,277 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:06,277 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,277 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:06,278 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:06,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:06,279 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,279 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,280 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:06,280 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,280 INFO L85 PathProgramCache]: Analyzing trace with hash -839151319, now seen corresponding path program 5 times [2025-02-06 19:09:06,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [681742777] [2025-02-06 19:09:06,280 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:06,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,285 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-02-06 19:09:06,293 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-02-06 19:09:06,293 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-02-06 19:09:06,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:06,393 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,393 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:06,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [681742777] [2025-02-06 19:09:06,393 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [681742777] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:06,393 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1813754805] [2025-02-06 19:09:06,393 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:06,393 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:06,393 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:06,398 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:06,399 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-02-06 19:09:06,426 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 16 statements into 4 equivalence classes. [2025-02-06 19:09:06,438 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-02-06 19:09:06,438 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-02-06 19:09:06,438 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:06,439 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-02-06 19:09:06,440 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:06,506 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,507 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:06,550 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1813754805] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:06,551 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:06,551 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9] total 13 [2025-02-06 19:09:06,551 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1893401175] [2025-02-06 19:09:06,551 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:06,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:06,585 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-02-06 19:09:06,586 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2025-02-06 19:09:06,586 INFO L87 Difference]: Start difference. First operand 31 states and 37 transitions. cyclomatic complexity: 9 Second operand has 14 states, 13 states have (on average 2.076923076923077) internal successors, (27), 14 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:06,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:06,692 INFO L93 Difference]: Finished difference Result 105 states and 124 transitions. [2025-02-06 19:09:06,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 105 states and 124 transitions. [2025-02-06 19:09:06,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:06,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 105 states to 67 states and 79 transitions. [2025-02-06 19:09:06,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 63 [2025-02-06 19:09:06,694 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 63 [2025-02-06 19:09:06,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 79 transitions. [2025-02-06 19:09:06,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:06,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 79 transitions. [2025-02-06 19:09:06,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 79 transitions. [2025-02-06 19:09:06,696 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 38. [2025-02-06 19:09:06,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.1842105263157894) internal successors, (45), 37 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:06,697 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 45 transitions. [2025-02-06 19:09:06,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-02-06 19:09:06,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 19:09:06,698 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 45 transitions. [2025-02-06 19:09:06,698 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:09:06,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 45 transitions. [2025-02-06 19:09:06,698 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:06,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:06,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:06,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 1, 1, 1] [2025-02-06 19:09:06,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:06,699 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:06,699 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:06,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,699 INFO L85 PathProgramCache]: Analyzing trace with hash 464653639, now seen corresponding path program 6 times [2025-02-06 19:09:06,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097634274] [2025-02-06 19:09:06,700 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:06,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,705 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 17 statements into 4 equivalence classes. [2025-02-06 19:09:06,753 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 17 of 17 statements. [2025-02-06 19:09:06,753 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-02-06 19:09:06,754 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,754 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:06,755 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 17 statements into 1 equivalence classes. [2025-02-06 19:09:06,763 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 17 of 17 statements. [2025-02-06 19:09:06,763 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,763 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,766 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:06,766 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,766 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 5 times [2025-02-06 19:09:06,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319001875] [2025-02-06 19:09:06,767 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:06,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,768 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:06,770 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:06,770 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:06,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,770 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:06,770 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:06,771 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:06,771 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,771 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:06,772 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:06,772 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:06,773 INFO L85 PathProgramCache]: Analyzing trace with hash -183009057, now seen corresponding path program 7 times [2025-02-06 19:09:06,773 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:06,773 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1485979199] [2025-02-06 19:09:06,773 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:06,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:06,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-02-06 19:09:06,782 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-02-06 19:09:06,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:06,908 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 12 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:06,908 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:06,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1485979199] [2025-02-06 19:09:06,908 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1485979199] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:06,908 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [361545638] [2025-02-06 19:09:06,908 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:06,909 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:06,909 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:06,912 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:06,913 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-02-06 19:09:06,955 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-02-06 19:09:06,966 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-02-06 19:09:06,966 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:06,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:06,967 INFO L256 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-02-06 19:09:06,968 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:07,059 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:07,060 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:07,121 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:07,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [361545638] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:07,121 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:07,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 18 [2025-02-06 19:09:07,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1370542175] [2025-02-06 19:09:07,122 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:07,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:07,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-02-06 19:09:07,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2025-02-06 19:09:07,155 INFO L87 Difference]: Start difference. First operand 38 states and 45 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.2222222222222223) internal successors, (40), 19 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:07,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:07,330 INFO L93 Difference]: Finished difference Result 130 states and 153 transitions. [2025-02-06 19:09:07,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 153 transitions. [2025-02-06 19:09:07,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:07,332 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 80 states and 94 transitions. [2025-02-06 19:09:07,332 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 75 [2025-02-06 19:09:07,332 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 75 [2025-02-06 19:09:07,332 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80 states and 94 transitions. [2025-02-06 19:09:07,333 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:07,333 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80 states and 94 transitions. [2025-02-06 19:09:07,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states and 94 transitions. [2025-02-06 19:09:07,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 45. [2025-02-06 19:09:07,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 45 states, 45 states have (on average 1.1777777777777778) internal successors, (53), 44 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:07,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 53 transitions. [2025-02-06 19:09:07,339 INFO L240 hiAutomatonCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-02-06 19:09:07,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2025-02-06 19:09:07,341 INFO L432 stractBuchiCegarLoop]: Abstraction has 45 states and 53 transitions. [2025-02-06 19:09:07,341 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:09:07,341 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 45 states and 53 transitions. [2025-02-06 19:09:07,342 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:07,342 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:07,342 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:07,342 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 1, 1, 1] [2025-02-06 19:09:07,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:07,342 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:07,342 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:07,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:07,345 INFO L85 PathProgramCache]: Analyzing trace with hash 1289141757, now seen corresponding path program 8 times [2025-02-06 19:09:07,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:07,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [565261376] [2025-02-06 19:09:07,345 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:07,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:07,351 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 21 statements into 2 equivalence classes. [2025-02-06 19:09:07,377 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 21 of 21 statements. [2025-02-06 19:09:07,377 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:07,377 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:07,377 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:07,380 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-02-06 19:09:07,396 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-02-06 19:09:07,396 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:07,396 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:07,402 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:07,402 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:07,402 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 6 times [2025-02-06 19:09:07,403 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:07,403 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [676636376] [2025-02-06 19:09:07,403 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:07,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:07,408 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:07,409 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:07,409 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:09:07,409 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:07,409 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:07,410 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:07,410 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:07,410 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:07,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:07,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:07,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:07,416 INFO L85 PathProgramCache]: Analyzing trace with hash -775451543, now seen corresponding path program 9 times [2025-02-06 19:09:07,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:07,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460310327] [2025-02-06 19:09:07,416 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:07,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:07,428 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-02-06 19:09:07,472 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:09:07,472 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-02-06 19:09:07,472 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:07,679 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 22 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:07,679 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:07,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460310327] [2025-02-06 19:09:07,679 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460310327] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:07,679 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1407235612] [2025-02-06 19:09:07,679 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:07,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:07,680 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:07,684 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:07,691 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-02-06 19:09:07,748 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 24 statements into 6 equivalence classes. [2025-02-06 19:09:07,773 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:09:07,773 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-02-06 19:09:07,773 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:07,774 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-02-06 19:09:07,775 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:07,910 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:07,910 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:08,002 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:08,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1407235612] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:08,003 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:08,003 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13] total 21 [2025-02-06 19:09:08,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2045793582] [2025-02-06 19:09:08,003 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:08,078 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:08,078 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-02-06 19:09:08,078 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=340, Unknown=0, NotChecked=0, Total=462 [2025-02-06 19:09:08,078 INFO L87 Difference]: Start difference. First operand 45 states and 53 transitions. cyclomatic complexity: 11 Second operand has 22 states, 21 states have (on average 2.238095238095238) internal successors, (47), 22 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:08,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:08,538 INFO L93 Difference]: Finished difference Result 155 states and 182 transitions. [2025-02-06 19:09:08,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155 states and 182 transitions. [2025-02-06 19:09:08,539 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:08,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155 states to 93 states and 109 transitions. [2025-02-06 19:09:08,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 87 [2025-02-06 19:09:08,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 87 [2025-02-06 19:09:08,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 93 states and 109 transitions. [2025-02-06 19:09:08,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:08,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 93 states and 109 transitions. [2025-02-06 19:09:08,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states and 109 transitions. [2025-02-06 19:09:08,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 52. [2025-02-06 19:09:08,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 52 states, 52 states have (on average 1.1730769230769231) internal successors, (61), 51 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:08,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 61 transitions. [2025-02-06 19:09:08,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-02-06 19:09:08,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-02-06 19:09:08,548 INFO L432 stractBuchiCegarLoop]: Abstraction has 52 states and 61 transitions. [2025-02-06 19:09:08,548 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:09:08,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 52 states and 61 transitions. [2025-02-06 19:09:08,548 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:08,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:08,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:08,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 1, 1, 1] [2025-02-06 19:09:08,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:08,549 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:08,549 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:08,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:08,549 INFO L85 PathProgramCache]: Analyzing trace with hash -1891169657, now seen corresponding path program 10 times [2025-02-06 19:09:08,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:08,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541433990] [2025-02-06 19:09:08,549 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:08,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:08,570 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 25 statements into 2 equivalence classes. [2025-02-06 19:09:08,609 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 25 of 25 statements. [2025-02-06 19:09:08,609 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:08,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:08,609 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:08,616 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-02-06 19:09:08,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-02-06 19:09:08,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:08,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:08,643 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:08,647 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:08,647 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 7 times [2025-02-06 19:09:08,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:08,647 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038547885] [2025-02-06 19:09:08,647 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:08,647 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:08,649 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:08,653 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:08,653 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:08,654 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:08,654 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:08,654 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:08,655 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:08,655 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:08,655 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:08,656 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:08,660 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:08,660 INFO L85 PathProgramCache]: Analyzing trace with hash 1545763743, now seen corresponding path program 11 times [2025-02-06 19:09:08,660 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:08,660 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505964062] [2025-02-06 19:09:08,660 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:08,660 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:08,665 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-02-06 19:09:08,692 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:09:08,692 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-02-06 19:09:08,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:09,032 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:09,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:09,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [505964062] [2025-02-06 19:09:09,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [505964062] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:09,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1009804084] [2025-02-06 19:09:09,033 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:09,033 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:09,033 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:09,036 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:09,037 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-02-06 19:09:09,085 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 28 statements into 7 equivalence classes. [2025-02-06 19:09:09,138 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:09:09,140 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-02-06 19:09:09,140 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:09,141 INFO L256 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 17 conjuncts are in the unsatisfiable core [2025-02-06 19:09:09,144 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:09,436 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:09,436 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:09,632 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 45 proven. 27 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:09,632 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1009804084] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:09,632 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:09,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 16, 16] total 38 [2025-02-06 19:09:09,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1400187561] [2025-02-06 19:09:09,632 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:09,665 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:09,666 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2025-02-06 19:09:09,666 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=1217, Unknown=0, NotChecked=0, Total=1482 [2025-02-06 19:09:09,667 INFO L87 Difference]: Start difference. First operand 52 states and 61 transitions. cyclomatic complexity: 12 Second operand has 39 states, 38 states have (on average 1.6842105263157894) internal successors, (64), 39 states have internal predecessors, (64), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:10,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:10,063 INFO L93 Difference]: Finished difference Result 217 states and 253 transitions. [2025-02-06 19:09:10,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 217 states and 253 transitions. [2025-02-06 19:09:10,065 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:10,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 217 states to 106 states and 124 transitions. [2025-02-06 19:09:10,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99 [2025-02-06 19:09:10,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99 [2025-02-06 19:09:10,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 106 states and 124 transitions. [2025-02-06 19:09:10,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:10,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 106 states and 124 transitions. [2025-02-06 19:09:10,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states and 124 transitions. [2025-02-06 19:09:10,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 59. [2025-02-06 19:09:10,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59 states, 59 states have (on average 1.1694915254237288) internal successors, (69), 58 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:10,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 69 transitions. [2025-02-06 19:09:10,070 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-02-06 19:09:10,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-02-06 19:09:10,073 INFO L432 stractBuchiCegarLoop]: Abstraction has 59 states and 69 transitions. [2025-02-06 19:09:10,073 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:09:10,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59 states and 69 transitions. [2025-02-06 19:09:10,075 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:10,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:10,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:10,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 1, 1, 1] [2025-02-06 19:09:10,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:10,076 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:10,076 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:10,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:10,076 INFO L85 PathProgramCache]: Analyzing trace with hash 861518525, now seen corresponding path program 12 times [2025-02-06 19:09:10,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:10,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [64081890] [2025-02-06 19:09:10,076 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:10,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:10,083 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 29 statements into 7 equivalence classes. [2025-02-06 19:09:10,134 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:09:10,134 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2025-02-06 19:09:10,134 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:10,134 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:10,137 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:09:10,147 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:09:10,147 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:10,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:10,149 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:10,150 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:10,150 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 8 times [2025-02-06 19:09:10,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:10,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [816107630] [2025-02-06 19:09:10,150 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:10,150 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:10,151 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:10,152 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:10,152 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:10,152 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:10,152 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:10,152 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:10,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:10,153 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:10,153 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:10,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:10,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:10,154 INFO L85 PathProgramCache]: Analyzing trace with hash -1226156119, now seen corresponding path program 13 times [2025-02-06 19:09:10,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:10,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1197341891] [2025-02-06 19:09:10,154 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:10,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:10,161 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-02-06 19:09:10,173 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-02-06 19:09:10,173 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:10,173 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:10,473 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 51 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:10,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:10,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1197341891] [2025-02-06 19:09:10,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1197341891] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:10,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1104302224] [2025-02-06 19:09:10,474 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:10,474 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:10,474 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:10,480 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:10,484 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-02-06 19:09:10,521 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-02-06 19:09:10,538 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-02-06 19:09:10,539 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:10,539 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:10,540 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-02-06 19:09:10,541 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:10,709 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:10,710 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:10,842 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:10,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1104302224] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:10,842 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:10,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 27 [2025-02-06 19:09:10,842 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1559682545] [2025-02-06 19:09:10,842 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:10,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:10,877 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-02-06 19:09:10,878 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=564, Unknown=0, NotChecked=0, Total=756 [2025-02-06 19:09:10,878 INFO L87 Difference]: Start difference. First operand 59 states and 69 transitions. cyclomatic complexity: 13 Second operand has 28 states, 27 states have (on average 2.259259259259259) internal successors, (61), 28 states have internal predecessors, (61), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:11,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:11,105 INFO L93 Difference]: Finished difference Result 205 states and 240 transitions. [2025-02-06 19:09:11,105 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 205 states and 240 transitions. [2025-02-06 19:09:11,107 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:11,110 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 205 states to 119 states and 139 transitions. [2025-02-06 19:09:11,110 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111 [2025-02-06 19:09:11,110 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111 [2025-02-06 19:09:11,110 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119 states and 139 transitions. [2025-02-06 19:09:11,111 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:11,111 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119 states and 139 transitions. [2025-02-06 19:09:11,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states and 139 transitions. [2025-02-06 19:09:11,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 66. [2025-02-06 19:09:11,112 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66 states, 66 states have (on average 1.1666666666666667) internal successors, (77), 65 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:11,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 77 transitions. [2025-02-06 19:09:11,113 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-02-06 19:09:11,115 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-02-06 19:09:11,116 INFO L432 stractBuchiCegarLoop]: Abstraction has 66 states and 77 transitions. [2025-02-06 19:09:11,116 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:09:11,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66 states and 77 transitions. [2025-02-06 19:09:11,116 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:11,116 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:11,116 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:11,117 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 1, 1, 1] [2025-02-06 19:09:11,117 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:11,117 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:11,117 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:11,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:11,118 INFO L85 PathProgramCache]: Analyzing trace with hash -1810835513, now seen corresponding path program 14 times [2025-02-06 19:09:11,118 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:11,118 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267599919] [2025-02-06 19:09:11,118 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:11,118 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:11,124 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-02-06 19:09:11,157 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-02-06 19:09:11,157 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:11,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:11,157 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:11,161 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-02-06 19:09:11,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-02-06 19:09:11,190 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:11,190 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:11,197 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:11,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:11,198 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 9 times [2025-02-06 19:09:11,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:11,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631699826] [2025-02-06 19:09:11,198 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:11,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:11,201 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:11,202 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:11,203 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:09:11,203 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:11,203 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:11,203 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:11,204 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:11,204 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:11,204 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:11,205 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:11,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:11,206 INFO L85 PathProgramCache]: Analyzing trace with hash -1811503521, now seen corresponding path program 15 times [2025-02-06 19:09:11,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:11,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425160757] [2025-02-06 19:09:11,206 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:11,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:11,214 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-02-06 19:09:11,293 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:09:11,295 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-02-06 19:09:11,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:11,738 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 70 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:11,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:11,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [425160757] [2025-02-06 19:09:11,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [425160757] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:11,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [276551773] [2025-02-06 19:09:11,739 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:11,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:11,739 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:11,741 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:11,742 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2025-02-06 19:09:11,783 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 9 equivalence classes. [2025-02-06 19:09:11,827 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:09:11,827 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-02-06 19:09:11,827 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:11,828 INFO L256 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-02-06 19:09:11,829 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:12,129 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:12,129 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:12,276 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:12,276 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [276551773] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:12,276 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:12,276 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19] total 30 [2025-02-06 19:09:12,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [851725611] [2025-02-06 19:09:12,277 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:12,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:12,311 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-02-06 19:09:12,312 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=697, Unknown=0, NotChecked=0, Total=930 [2025-02-06 19:09:12,312 INFO L87 Difference]: Start difference. First operand 66 states and 77 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.2666666666666666) internal successors, (68), 31 states have internal predecessors, (68), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:12,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:12,571 INFO L93 Difference]: Finished difference Result 230 states and 269 transitions. [2025-02-06 19:09:12,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 230 states and 269 transitions. [2025-02-06 19:09:12,573 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:12,573 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 230 states to 132 states and 154 transitions. [2025-02-06 19:09:12,573 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123 [2025-02-06 19:09:12,573 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123 [2025-02-06 19:09:12,573 INFO L73 IsDeterministic]: Start isDeterministic. Operand 132 states and 154 transitions. [2025-02-06 19:09:12,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:12,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 132 states and 154 transitions. [2025-02-06 19:09:12,574 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states and 154 transitions. [2025-02-06 19:09:12,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 73. [2025-02-06 19:09:12,575 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73 states, 73 states have (on average 1.1643835616438356) internal successors, (85), 72 states have internal predecessors, (85), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:12,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 85 transitions. [2025-02-06 19:09:12,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-02-06 19:09:12,576 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-02-06 19:09:12,576 INFO L432 stractBuchiCegarLoop]: Abstraction has 73 states and 85 transitions. [2025-02-06 19:09:12,576 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:09:12,576 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73 states and 85 transitions. [2025-02-06 19:09:12,577 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:12,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:12,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:12,577 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 1, 1, 1] [2025-02-06 19:09:12,577 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:12,577 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:12,578 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:12,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:12,579 INFO L85 PathProgramCache]: Analyzing trace with hash 2073290621, now seen corresponding path program 16 times [2025-02-06 19:09:12,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:12,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092155422] [2025-02-06 19:09:12,579 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:12,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:12,585 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 37 statements into 2 equivalence classes. [2025-02-06 19:09:12,603 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:09:12,603 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:12,603 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:12,603 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:12,606 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:09:12,622 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:09:12,623 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:12,623 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:12,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:12,627 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:12,627 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 10 times [2025-02-06 19:09:12,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:12,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631683241] [2025-02-06 19:09:12,627 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:12,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:12,629 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-06 19:09:12,630 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:12,630 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:12,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:12,630 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:12,630 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:12,631 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:12,631 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:12,631 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:12,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:12,632 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:12,632 INFO L85 PathProgramCache]: Analyzing trace with hash -523767063, now seen corresponding path program 17 times [2025-02-06 19:09:12,632 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:12,632 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1473942444] [2025-02-06 19:09:12,632 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:12,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:12,638 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-02-06 19:09:12,654 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:09:12,654 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-02-06 19:09:12,654 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:12,977 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 108 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:12,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:12,977 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1473942444] [2025-02-06 19:09:12,977 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1473942444] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:12,977 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [261594671] [2025-02-06 19:09:12,977 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:12,978 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:12,978 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:12,980 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:12,981 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2025-02-06 19:09:13,026 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 40 statements into 10 equivalence classes. [2025-02-06 19:09:13,081 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-02-06 19:09:13,081 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-02-06 19:09:13,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:13,083 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-02-06 19:09:13,084 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:13,590 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:13,590 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:13,823 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:13,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [261594671] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:13,824 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:13,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21] total 42 [2025-02-06 19:09:13,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597522167] [2025-02-06 19:09:13,824 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:13,874 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:13,874 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2025-02-06 19:09:13,875 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2025-02-06 19:09:13,875 INFO L87 Difference]: Start difference. First operand 73 states and 85 transitions. cyclomatic complexity: 15 Second operand has 43 states, 42 states have (on average 1.9285714285714286) internal successors, (81), 43 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:14,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:14,778 INFO L93 Difference]: Finished difference Result 310 states and 361 transitions. [2025-02-06 19:09:14,778 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 310 states and 361 transitions. [2025-02-06 19:09:14,780 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:14,781 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 310 states to 145 states and 169 transitions. [2025-02-06 19:09:14,781 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 135 [2025-02-06 19:09:14,781 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 135 [2025-02-06 19:09:14,781 INFO L73 IsDeterministic]: Start isDeterministic. Operand 145 states and 169 transitions. [2025-02-06 19:09:14,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:14,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 145 states and 169 transitions. [2025-02-06 19:09:14,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states and 169 transitions. [2025-02-06 19:09:14,783 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 80. [2025-02-06 19:09:14,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.1625) internal successors, (93), 79 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:14,784 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 93 transitions. [2025-02-06 19:09:14,784 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-02-06 19:09:14,784 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2025-02-06 19:09:14,785 INFO L432 stractBuchiCegarLoop]: Abstraction has 80 states and 93 transitions. [2025-02-06 19:09:14,785 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:09:14,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 93 transitions. [2025-02-06 19:09:14,785 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:14,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:14,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:14,786 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 1, 1, 1] [2025-02-06 19:09:14,786 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:14,786 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:14,786 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:14,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:14,787 INFO L85 PathProgramCache]: Analyzing trace with hash -814516985, now seen corresponding path program 18 times [2025-02-06 19:09:14,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:14,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1819134937] [2025-02-06 19:09:14,787 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:14,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:14,793 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 41 statements into 10 equivalence classes. [2025-02-06 19:09:14,873 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:09:14,873 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2025-02-06 19:09:14,873 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:14,873 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:14,876 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:09:14,899 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:09:14,900 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:14,900 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:14,903 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:14,904 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:14,904 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 11 times [2025-02-06 19:09:14,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:14,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188691119] [2025-02-06 19:09:14,904 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:14,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:14,906 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:14,906 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:14,906 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:14,906 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:14,907 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:14,907 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:14,907 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:14,907 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:14,907 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:14,908 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:14,909 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:14,909 INFO L85 PathProgramCache]: Analyzing trace with hash 1289748767, now seen corresponding path program 19 times [2025-02-06 19:09:14,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:14,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197496517] [2025-02-06 19:09:14,909 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:14,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:14,922 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:09:14,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:09:14,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:14,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:15,360 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 117 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:15,360 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:15,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [197496517] [2025-02-06 19:09:15,360 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [197496517] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:15,360 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [724323736] [2025-02-06 19:09:15,360 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:15,360 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:15,360 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:15,362 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:15,363 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2025-02-06 19:09:15,411 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-06 19:09:15,432 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-06 19:09:15,432 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:15,432 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:15,437 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-02-06 19:09:15,438 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:15,791 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:15,791 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:15,976 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:15,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [724323736] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:15,976 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:15,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23] total 36 [2025-02-06 19:09:15,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1180985052] [2025-02-06 19:09:15,977 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:16,016 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:16,017 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-02-06 19:09:16,017 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2025-02-06 19:09:16,017 INFO L87 Difference]: Start difference. First operand 80 states and 93 transitions. cyclomatic complexity: 16 Second operand has 37 states, 36 states have (on average 2.2777777777777777) internal successors, (82), 37 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:16,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:16,377 INFO L93 Difference]: Finished difference Result 280 states and 327 transitions. [2025-02-06 19:09:16,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 280 states and 327 transitions. [2025-02-06 19:09:16,379 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:16,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 280 states to 158 states and 184 transitions. [2025-02-06 19:09:16,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147 [2025-02-06 19:09:16,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147 [2025-02-06 19:09:16,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 158 states and 184 transitions. [2025-02-06 19:09:16,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:16,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 158 states and 184 transitions. [2025-02-06 19:09:16,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 158 states and 184 transitions. [2025-02-06 19:09:16,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 158 to 87. [2025-02-06 19:09:16,382 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 87 states, 87 states have (on average 1.160919540229885) internal successors, (101), 86 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:16,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 101 transitions. [2025-02-06 19:09:16,383 INFO L240 hiAutomatonCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-02-06 19:09:16,383 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-02-06 19:09:16,384 INFO L432 stractBuchiCegarLoop]: Abstraction has 87 states and 101 transitions. [2025-02-06 19:09:16,384 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:09:16,384 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 87 states and 101 transitions. [2025-02-06 19:09:16,384 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:16,384 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:16,385 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:16,385 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 1, 1, 1] [2025-02-06 19:09:16,385 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:16,385 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:16,385 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:16,386 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:16,386 INFO L85 PathProgramCache]: Analyzing trace with hash 396444733, now seen corresponding path program 20 times [2025-02-06 19:09:16,386 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:16,386 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [258847493] [2025-02-06 19:09:16,386 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:16,386 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:16,395 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 45 statements into 2 equivalence classes. [2025-02-06 19:09:16,424 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 45 of 45 statements. [2025-02-06 19:09:16,424 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:16,424 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:16,424 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:16,427 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-02-06 19:09:16,443 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-02-06 19:09:16,443 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:16,443 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:16,447 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:16,448 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:16,448 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 12 times [2025-02-06 19:09:16,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:16,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541423246] [2025-02-06 19:09:16,448 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:16,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:16,450 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:16,451 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:16,451 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:09:16,451 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:16,451 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:16,451 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:16,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:16,452 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:16,452 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:16,453 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:16,453 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:16,453 INFO L85 PathProgramCache]: Analyzing trace with hash -674996695, now seen corresponding path program 21 times [2025-02-06 19:09:16,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:16,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547757308] [2025-02-06 19:09:16,454 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:16,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:16,460 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-02-06 19:09:16,525 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-02-06 19:09:16,525 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-02-06 19:09:16,525 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:16,881 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 145 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:16,881 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:16,881 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547757308] [2025-02-06 19:09:16,881 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1547757308] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:16,881 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1311497600] [2025-02-06 19:09:16,881 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:16,882 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:16,882 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:16,884 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:16,885 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2025-02-06 19:09:16,932 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 48 statements into 12 equivalence classes. [2025-02-06 19:09:17,112 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 48 of 48 statements. [2025-02-06 19:09:17,113 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-02-06 19:09:17,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:17,115 INFO L256 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-02-06 19:09:17,116 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:17,401 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:17,401 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:17,611 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:17,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1311497600] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:17,611 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:17,611 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25] total 39 [2025-02-06 19:09:17,611 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020455646] [2025-02-06 19:09:17,611 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:17,652 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:17,652 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-02-06 19:09:17,653 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1180, Unknown=0, NotChecked=0, Total=1560 [2025-02-06 19:09:17,653 INFO L87 Difference]: Start difference. First operand 87 states and 101 transitions. cyclomatic complexity: 17 Second operand has 40 states, 39 states have (on average 2.282051282051282) internal successors, (89), 40 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:18,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:18,036 INFO L93 Difference]: Finished difference Result 305 states and 356 transitions. [2025-02-06 19:09:18,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 305 states and 356 transitions. [2025-02-06 19:09:18,038 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:18,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 305 states to 171 states and 199 transitions. [2025-02-06 19:09:18,042 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 159 [2025-02-06 19:09:18,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 159 [2025-02-06 19:09:18,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171 states and 199 transitions. [2025-02-06 19:09:18,043 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:18,043 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171 states and 199 transitions. [2025-02-06 19:09:18,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171 states and 199 transitions. [2025-02-06 19:09:18,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171 to 94. [2025-02-06 19:09:18,049 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 94 states, 94 states have (on average 1.1595744680851063) internal successors, (109), 93 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:18,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 94 states to 94 states and 109 transitions. [2025-02-06 19:09:18,049 INFO L240 hiAutomatonCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-02-06 19:09:18,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2025-02-06 19:09:18,051 INFO L432 stractBuchiCegarLoop]: Abstraction has 94 states and 109 transitions. [2025-02-06 19:09:18,051 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 19:09:18,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 94 states and 109 transitions. [2025-02-06 19:09:18,052 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:18,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:18,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:18,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 1, 1, 1] [2025-02-06 19:09:18,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:18,053 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:18,053 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:18,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:18,054 INFO L85 PathProgramCache]: Analyzing trace with hash 198369863, now seen corresponding path program 22 times [2025-02-06 19:09:18,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:18,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746977049] [2025-02-06 19:09:18,054 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:18,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:18,062 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 49 statements into 2 equivalence classes. [2025-02-06 19:09:18,091 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:09:18,091 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:18,091 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:18,091 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:18,094 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-02-06 19:09:18,118 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-02-06 19:09:18,118 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:18,118 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:18,123 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:18,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:18,124 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 13 times [2025-02-06 19:09:18,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:18,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871954272] [2025-02-06 19:09:18,124 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:18,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:18,126 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:18,127 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:18,127 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:18,127 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:18,127 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:18,127 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:18,128 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:18,128 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:18,128 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:18,129 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:18,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:18,129 INFO L85 PathProgramCache]: Analyzing trace with hash -238384161, now seen corresponding path program 23 times [2025-02-06 19:09:18,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:18,130 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978358771] [2025-02-06 19:09:18,130 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:18,130 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:18,140 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-02-06 19:09:18,162 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-02-06 19:09:18,162 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-02-06 19:09:18,162 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:18,595 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:18,595 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:18,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978358771] [2025-02-06 19:09:18,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978358771] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:18,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1385384489] [2025-02-06 19:09:18,596 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:18,596 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:18,596 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:18,598 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:18,605 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2025-02-06 19:09:18,660 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 52 statements into 13 equivalence classes. [2025-02-06 19:09:18,742 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-02-06 19:09:18,742 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-02-06 19:09:18,742 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:18,744 INFO L256 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-02-06 19:09:18,745 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:19,126 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:19,127 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:19,373 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:19,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1385384489] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:19,374 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:19,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27] total 40 [2025-02-06 19:09:19,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377870183] [2025-02-06 19:09:19,374 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:19,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:19,405 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2025-02-06 19:09:19,405 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1236, Unknown=0, NotChecked=0, Total=1640 [2025-02-06 19:09:19,405 INFO L87 Difference]: Start difference. First operand 94 states and 109 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.25) internal successors, (90), 41 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:19,774 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:19,775 INFO L93 Difference]: Finished difference Result 330 states and 385 transitions. [2025-02-06 19:09:19,775 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 330 states and 385 transitions. [2025-02-06 19:09:19,777 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:19,777 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 330 states to 184 states and 214 transitions. [2025-02-06 19:09:19,778 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171 [2025-02-06 19:09:19,778 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171 [2025-02-06 19:09:19,778 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 214 transitions. [2025-02-06 19:09:19,778 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:19,778 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 214 transitions. [2025-02-06 19:09:19,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 214 transitions. [2025-02-06 19:09:19,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 101. [2025-02-06 19:09:19,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.1584158415841583) internal successors, (117), 100 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:19,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 117 transitions. [2025-02-06 19:09:19,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-02-06 19:09:19,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-02-06 19:09:19,781 INFO L432 stractBuchiCegarLoop]: Abstraction has 101 states and 117 transitions. [2025-02-06 19:09:19,781 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 19:09:19,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 117 transitions. [2025-02-06 19:09:19,781 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:19,782 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:19,782 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:19,782 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 1, 1, 1] [2025-02-06 19:09:19,782 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:19,782 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:19,782 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:19,783 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:19,783 INFO L85 PathProgramCache]: Analyzing trace with hash -1264725763, now seen corresponding path program 24 times [2025-02-06 19:09:19,783 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:19,783 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438991624] [2025-02-06 19:09:19,783 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:19,783 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:19,790 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 53 statements into 13 equivalence classes. [2025-02-06 19:09:19,854 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) and asserted 53 of 53 statements. [2025-02-06 19:09:19,854 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2025-02-06 19:09:19,854 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:19,854 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:19,858 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 53 statements into 1 equivalence classes. [2025-02-06 19:09:19,899 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 53 of 53 statements. [2025-02-06 19:09:19,900 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:19,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:19,905 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:19,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:19,906 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 14 times [2025-02-06 19:09:19,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:19,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2146297755] [2025-02-06 19:09:19,906 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:19,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:19,908 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:19,909 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:19,909 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:19,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:19,909 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:19,909 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:19,910 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:19,910 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:19,910 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:19,911 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:19,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:19,911 INFO L85 PathProgramCache]: Analyzing trace with hash -1992058519, now seen corresponding path program 25 times [2025-02-06 19:09:19,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:19,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1638565545] [2025-02-06 19:09:19,912 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:19,912 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:19,921 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-02-06 19:09:19,927 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-02-06 19:09:19,928 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:19,928 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:20,598 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 210 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:20,598 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:20,598 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1638565545] [2025-02-06 19:09:20,598 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1638565545] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:20,599 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [384955306] [2025-02-06 19:09:20,599 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:20,599 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:20,599 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:20,601 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:20,609 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-02-06 19:09:20,674 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-02-06 19:09:20,701 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-02-06 19:09:20,701 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:20,701 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:20,703 INFO L256 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-02-06 19:09:20,704 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:21,193 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:21,194 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:21,504 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:21,504 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [384955306] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:21,504 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:21,505 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29] total 45 [2025-02-06 19:09:21,505 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249516141] [2025-02-06 19:09:21,505 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:21,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:21,537 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2025-02-06 19:09:21,537 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=1572, Unknown=0, NotChecked=0, Total=2070 [2025-02-06 19:09:21,538 INFO L87 Difference]: Start difference. First operand 101 states and 117 transitions. cyclomatic complexity: 19 Second operand has 46 states, 45 states have (on average 2.2888888888888888) internal successors, (103), 46 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:22,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:22,005 INFO L93 Difference]: Finished difference Result 355 states and 414 transitions. [2025-02-06 19:09:22,005 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 355 states and 414 transitions. [2025-02-06 19:09:22,007 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:22,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 355 states to 197 states and 229 transitions. [2025-02-06 19:09:22,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 183 [2025-02-06 19:09:22,008 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 183 [2025-02-06 19:09:22,008 INFO L73 IsDeterministic]: Start isDeterministic. Operand 197 states and 229 transitions. [2025-02-06 19:09:22,008 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:22,008 INFO L218 hiAutomatonCegarLoop]: Abstraction has 197 states and 229 transitions. [2025-02-06 19:09:22,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states and 229 transitions. [2025-02-06 19:09:22,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 108. [2025-02-06 19:09:22,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 108 states, 108 states have (on average 1.1574074074074074) internal successors, (125), 107 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:22,017 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 125 transitions. [2025-02-06 19:09:22,017 INFO L240 hiAutomatonCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-02-06 19:09:22,020 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-02-06 19:09:22,020 INFO L432 stractBuchiCegarLoop]: Abstraction has 108 states and 125 transitions. [2025-02-06 19:09:22,020 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-06 19:09:22,020 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 108 states and 125 transitions. [2025-02-06 19:09:22,021 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:22,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:22,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:22,021 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 1, 1, 1] [2025-02-06 19:09:22,021 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:22,021 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:22,023 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:22,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:22,024 INFO L85 PathProgramCache]: Analyzing trace with hash 2022907783, now seen corresponding path program 26 times [2025-02-06 19:09:22,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:22,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401936939] [2025-02-06 19:09:22,024 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:22,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:22,033 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 57 statements into 2 equivalence classes. [2025-02-06 19:09:22,059 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 57 of 57 statements. [2025-02-06 19:09:22,059 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:22,059 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:22,059 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:22,062 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 57 statements into 1 equivalence classes. [2025-02-06 19:09:22,089 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 57 of 57 statements. [2025-02-06 19:09:22,089 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:22,089 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:22,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:22,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:22,096 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 15 times [2025-02-06 19:09:22,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:22,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1539291458] [2025-02-06 19:09:22,096 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:22,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:22,098 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:22,099 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:22,099 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:09:22,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:22,099 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:22,099 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:22,100 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:22,100 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:22,100 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:22,101 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:22,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:22,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1759659679, now seen corresponding path program 27 times [2025-02-06 19:09:22,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:22,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1125633893] [2025-02-06 19:09:22,102 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:22,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:22,112 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-02-06 19:09:22,249 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-02-06 19:09:22,250 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-02-06 19:09:22,250 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:22,765 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 247 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:22,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:22,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1125633893] [2025-02-06 19:09:22,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1125633893] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:22,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1338169405] [2025-02-06 19:09:22,765 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:22,765 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:22,766 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:22,769 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:22,774 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-02-06 19:09:22,840 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 60 statements into 15 equivalence classes. [2025-02-06 19:09:23,273 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 60 of 60 statements. [2025-02-06 19:09:23,273 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-02-06 19:09:23,273 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:23,276 INFO L256 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-02-06 19:09:23,277 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:23,687 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:23,687 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:23,990 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:23,990 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1338169405] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:23,991 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:23,991 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31] total 48 [2025-02-06 19:09:23,991 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056867385] [2025-02-06 19:09:23,991 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:24,022 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:24,022 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2025-02-06 19:09:24,023 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=1789, Unknown=0, NotChecked=0, Total=2352 [2025-02-06 19:09:24,023 INFO L87 Difference]: Start difference. First operand 108 states and 125 transitions. cyclomatic complexity: 20 Second operand has 49 states, 48 states have (on average 2.2916666666666665) internal successors, (110), 49 states have internal predecessors, (110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:24,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:24,538 INFO L93 Difference]: Finished difference Result 380 states and 443 transitions. [2025-02-06 19:09:24,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 380 states and 443 transitions. [2025-02-06 19:09:24,540 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:24,541 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 380 states to 210 states and 244 transitions. [2025-02-06 19:09:24,541 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 195 [2025-02-06 19:09:24,541 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 195 [2025-02-06 19:09:24,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210 states and 244 transitions. [2025-02-06 19:09:24,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:24,542 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210 states and 244 transitions. [2025-02-06 19:09:24,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states and 244 transitions. [2025-02-06 19:09:24,544 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 115. [2025-02-06 19:09:24,544 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.1565217391304348) internal successors, (133), 114 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:24,544 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 133 transitions. [2025-02-06 19:09:24,544 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-02-06 19:09:24,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-02-06 19:09:24,545 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 133 transitions. [2025-02-06 19:09:24,545 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-06 19:09:24,545 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 133 transitions. [2025-02-06 19:09:24,546 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:24,546 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:24,546 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:24,546 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 14, 14, 1, 1, 1] [2025-02-06 19:09:24,546 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:24,547 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:24,547 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:24,547 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:24,547 INFO L85 PathProgramCache]: Analyzing trace with hash 2057670077, now seen corresponding path program 28 times [2025-02-06 19:09:24,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:24,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [591618663] [2025-02-06 19:09:24,547 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:24,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:24,557 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 61 statements into 2 equivalence classes. [2025-02-06 19:09:24,600 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 61 of 61 statements. [2025-02-06 19:09:24,601 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:24,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:24,601 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:24,605 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 61 statements into 1 equivalence classes. [2025-02-06 19:09:24,636 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 61 of 61 statements. [2025-02-06 19:09:24,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:24,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:24,642 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:24,643 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:24,643 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 16 times [2025-02-06 19:09:24,643 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:24,643 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623213348] [2025-02-06 19:09:24,643 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:24,643 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:24,646 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-06 19:09:24,646 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:24,647 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:24,647 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:24,647 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:24,647 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:24,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:24,648 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:24,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:24,649 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:24,649 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:24,649 INFO L85 PathProgramCache]: Analyzing trace with hash -2018925399, now seen corresponding path program 29 times [2025-02-06 19:09:24,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:24,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139545740] [2025-02-06 19:09:24,650 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:24,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:24,660 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-02-06 19:09:24,696 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-02-06 19:09:24,696 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-02-06 19:09:24,696 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:25,231 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:25,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:25,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139545740] [2025-02-06 19:09:25,232 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139545740] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:25,232 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1835417789] [2025-02-06 19:09:25,232 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:25,232 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:25,232 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:25,238 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:25,239 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-02-06 19:09:25,306 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 64 statements into 16 equivalence classes. [2025-02-06 19:09:25,448 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-02-06 19:09:25,448 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-02-06 19:09:25,448 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:25,451 INFO L256 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-02-06 19:09:25,452 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:25,902 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:25,903 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:26,233 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:26,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1835417789] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:26,233 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:26,234 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33] total 49 [2025-02-06 19:09:26,234 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [530551440] [2025-02-06 19:09:26,234 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:26,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:26,264 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2025-02-06 19:09:26,265 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2025-02-06 19:09:26,265 INFO L87 Difference]: Start difference. First operand 115 states and 133 transitions. cyclomatic complexity: 21 Second operand has 50 states, 49 states have (on average 2.2653061224489797) internal successors, (111), 50 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:26,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:26,788 INFO L93 Difference]: Finished difference Result 405 states and 472 transitions. [2025-02-06 19:09:26,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 405 states and 472 transitions. [2025-02-06 19:09:26,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:26,791 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 405 states to 223 states and 259 transitions. [2025-02-06 19:09:26,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 207 [2025-02-06 19:09:26,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 207 [2025-02-06 19:09:26,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 223 states and 259 transitions. [2025-02-06 19:09:26,791 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:26,791 INFO L218 hiAutomatonCegarLoop]: Abstraction has 223 states and 259 transitions. [2025-02-06 19:09:26,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states and 259 transitions. [2025-02-06 19:09:26,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 122. [2025-02-06 19:09:26,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.1557377049180328) internal successors, (141), 121 states have internal predecessors, (141), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:26,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 141 transitions. [2025-02-06 19:09:26,793 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-02-06 19:09:26,822 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2025-02-06 19:09:26,822 INFO L432 stractBuchiCegarLoop]: Abstraction has 122 states and 141 transitions. [2025-02-06 19:09:26,822 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-06 19:09:26,822 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 141 transitions. [2025-02-06 19:09:26,823 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:26,823 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:26,823 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:26,824 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 15, 15, 1, 1, 1] [2025-02-06 19:09:26,824 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:26,824 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:26,824 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:26,824 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:26,825 INFO L85 PathProgramCache]: Analyzing trace with hash -367514425, now seen corresponding path program 30 times [2025-02-06 19:09:26,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:26,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1076054646] [2025-02-06 19:09:26,825 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:26,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:26,832 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 65 statements into 16 equivalence classes. [2025-02-06 19:09:26,933 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) and asserted 65 of 65 statements. [2025-02-06 19:09:26,933 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2025-02-06 19:09:26,933 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:26,933 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:26,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 65 statements into 1 equivalence classes. [2025-02-06 19:09:26,964 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 65 of 65 statements. [2025-02-06 19:09:26,965 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:26,965 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:26,969 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:26,970 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:26,970 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 17 times [2025-02-06 19:09:26,970 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:26,970 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147769159] [2025-02-06 19:09:26,970 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:26,970 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:26,972 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:26,973 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:26,973 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:26,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:26,973 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:26,973 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:26,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:26,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:26,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:26,975 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:26,975 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:26,975 INFO L85 PathProgramCache]: Analyzing trace with hash -750571169, now seen corresponding path program 31 times [2025-02-06 19:09:26,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:26,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1179295421] [2025-02-06 19:09:26,975 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:26,975 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:26,986 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-02-06 19:09:26,993 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-02-06 19:09:26,993 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:26,993 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:27,580 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 330 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:27,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:27,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1179295421] [2025-02-06 19:09:27,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1179295421] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:27,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1778836199] [2025-02-06 19:09:27,582 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:27,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:27,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:27,587 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:27,588 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2025-02-06 19:09:27,663 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-02-06 19:09:27,694 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-02-06 19:09:27,694 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:27,694 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:27,699 INFO L256 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-02-06 19:09:27,700 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:28,203 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:28,203 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:28,543 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:28,543 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1778836199] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:28,544 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:28,544 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35] total 54 [2025-02-06 19:09:28,544 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333851863] [2025-02-06 19:09:28,544 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:28,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:28,579 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2025-02-06 19:09:28,580 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=2265, Unknown=0, NotChecked=0, Total=2970 [2025-02-06 19:09:28,580 INFO L87 Difference]: Start difference. First operand 122 states and 141 transitions. cyclomatic complexity: 22 Second operand has 55 states, 54 states have (on average 2.2962962962962963) internal successors, (124), 55 states have internal predecessors, (124), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:29,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:29,184 INFO L93 Difference]: Finished difference Result 430 states and 501 transitions. [2025-02-06 19:09:29,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 430 states and 501 transitions. [2025-02-06 19:09:29,186 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:29,187 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 430 states to 236 states and 274 transitions. [2025-02-06 19:09:29,187 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 219 [2025-02-06 19:09:29,187 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 219 [2025-02-06 19:09:29,187 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236 states and 274 transitions. [2025-02-06 19:09:29,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:29,187 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236 states and 274 transitions. [2025-02-06 19:09:29,187 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states and 274 transitions. [2025-02-06 19:09:29,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 129. [2025-02-06 19:09:29,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129 states, 129 states have (on average 1.1550387596899225) internal successors, (149), 128 states have internal predecessors, (149), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:29,189 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 149 transitions. [2025-02-06 19:09:29,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-02-06 19:09:29,190 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2025-02-06 19:09:29,190 INFO L432 stractBuchiCegarLoop]: Abstraction has 129 states and 149 transitions. [2025-02-06 19:09:29,190 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-06 19:09:29,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129 states and 149 transitions. [2025-02-06 19:09:29,191 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:29,191 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:29,191 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:29,191 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 16, 16, 1, 1, 1] [2025-02-06 19:09:29,191 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:29,192 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:29,192 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:29,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:29,192 INFO L85 PathProgramCache]: Analyzing trace with hash -858490243, now seen corresponding path program 32 times [2025-02-06 19:09:29,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:29,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1319822742] [2025-02-06 19:09:29,192 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:29,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:29,201 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 69 statements into 2 equivalence classes. [2025-02-06 19:09:29,233 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 69 of 69 statements. [2025-02-06 19:09:29,233 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:29,233 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:29,233 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:29,237 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 69 statements into 1 equivalence classes. [2025-02-06 19:09:29,265 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 69 of 69 statements. [2025-02-06 19:09:29,265 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:29,266 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:29,272 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:29,272 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:29,273 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 18 times [2025-02-06 19:09:29,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:29,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170366871] [2025-02-06 19:09:29,273 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:29,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:29,276 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:29,276 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:29,276 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:09:29,276 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:29,276 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:29,277 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:29,277 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:29,277 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:29,277 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:29,279 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:29,279 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:29,279 INFO L85 PathProgramCache]: Analyzing trace with hash 1247444969, now seen corresponding path program 33 times [2025-02-06 19:09:29,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:29,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [88848751] [2025-02-06 19:09:29,279 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:29,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:29,296 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-02-06 19:09:29,551 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-02-06 19:09:29,551 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-02-06 19:09:29,552 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:30,226 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 376 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:30,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:30,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [88848751] [2025-02-06 19:09:30,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [88848751] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:30,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [213551154] [2025-02-06 19:09:30,226 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:30,226 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:30,226 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:30,229 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:30,231 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2025-02-06 19:09:30,320 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 72 statements into 18 equivalence classes. [2025-02-06 19:09:30,758 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 72 of 72 statements. [2025-02-06 19:09:30,758 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-02-06 19:09:30,758 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:30,761 INFO L256 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-02-06 19:09:30,763 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:31,352 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:31,353 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:31,804 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:31,804 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [213551154] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:31,804 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:31,804 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37] total 57 [2025-02-06 19:09:31,804 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1174146292] [2025-02-06 19:09:31,804 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:31,842 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:31,842 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2025-02-06 19:09:31,843 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=2524, Unknown=0, NotChecked=0, Total=3306 [2025-02-06 19:09:31,843 INFO L87 Difference]: Start difference. First operand 129 states and 149 transitions. cyclomatic complexity: 23 Second operand has 58 states, 57 states have (on average 2.2982456140350878) internal successors, (131), 58 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:32,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:32,498 INFO L93 Difference]: Finished difference Result 455 states and 530 transitions. [2025-02-06 19:09:32,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 455 states and 530 transitions. [2025-02-06 19:09:32,500 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:32,501 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 455 states to 249 states and 289 transitions. [2025-02-06 19:09:32,501 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 231 [2025-02-06 19:09:32,501 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 231 [2025-02-06 19:09:32,501 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249 states and 289 transitions. [2025-02-06 19:09:32,501 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:32,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249 states and 289 transitions. [2025-02-06 19:09:32,502 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states and 289 transitions. [2025-02-06 19:09:32,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 136. [2025-02-06 19:09:32,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.1544117647058822) internal successors, (157), 135 states have internal predecessors, (157), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:32,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 157 transitions. [2025-02-06 19:09:32,504 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-02-06 19:09:32,504 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2025-02-06 19:09:32,505 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 157 transitions. [2025-02-06 19:09:32,505 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-06 19:09:32,505 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 157 transitions. [2025-02-06 19:09:32,505 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:32,505 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:32,505 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:32,506 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 17, 17, 1, 1, 1] [2025-02-06 19:09:32,506 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:32,506 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:32,506 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:32,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:32,506 INFO L85 PathProgramCache]: Analyzing trace with hash 432409095, now seen corresponding path program 34 times [2025-02-06 19:09:32,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:32,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [501213025] [2025-02-06 19:09:32,506 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:32,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:32,516 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 73 statements into 2 equivalence classes. [2025-02-06 19:09:32,556 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 73 of 73 statements. [2025-02-06 19:09:32,556 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:32,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:32,556 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:32,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 73 statements into 1 equivalence classes. [2025-02-06 19:09:32,591 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 73 of 73 statements. [2025-02-06 19:09:32,591 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:32,591 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:32,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:32,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:32,597 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 19 times [2025-02-06 19:09:32,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:32,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378699465] [2025-02-06 19:09:32,597 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:32,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:32,599 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:32,600 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:32,600 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:32,600 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:32,600 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:32,600 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:32,601 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:32,601 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:32,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:32,602 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:32,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:32,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1292454943, now seen corresponding path program 35 times [2025-02-06 19:09:32,603 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:32,603 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1690207448] [2025-02-06 19:09:32,603 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:32,603 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:32,613 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-02-06 19:09:32,670 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-02-06 19:09:32,670 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-02-06 19:09:32,670 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:33,243 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:33,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:33,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1690207448] [2025-02-06 19:09:33,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1690207448] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:33,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1813487681] [2025-02-06 19:09:33,243 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:33,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:33,243 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:33,246 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:33,248 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2025-02-06 19:09:33,338 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 76 statements into 19 equivalence classes. [2025-02-06 19:09:33,673 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-02-06 19:09:33,673 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-02-06 19:09:33,673 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:33,677 INFO L256 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-02-06 19:09:33,678 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:34,385 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:34,386 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:34,784 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:34,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1813487681] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:34,784 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:34,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39] total 58 [2025-02-06 19:09:34,785 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1504770753] [2025-02-06 19:09:34,785 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:34,809 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:34,810 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2025-02-06 19:09:34,810 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2025-02-06 19:09:34,810 INFO L87 Difference]: Start difference. First operand 136 states and 157 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2758620689655173) internal successors, (132), 59 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:35,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:35,452 INFO L93 Difference]: Finished difference Result 480 states and 559 transitions. [2025-02-06 19:09:35,452 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 559 transitions. [2025-02-06 19:09:35,454 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:35,455 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 262 states and 304 transitions. [2025-02-06 19:09:35,455 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 243 [2025-02-06 19:09:35,455 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 243 [2025-02-06 19:09:35,455 INFO L73 IsDeterministic]: Start isDeterministic. Operand 262 states and 304 transitions. [2025-02-06 19:09:35,456 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:35,456 INFO L218 hiAutomatonCegarLoop]: Abstraction has 262 states and 304 transitions. [2025-02-06 19:09:35,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 262 states and 304 transitions. [2025-02-06 19:09:35,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 262 to 143. [2025-02-06 19:09:35,459 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 143 states, 143 states have (on average 1.1538461538461537) internal successors, (165), 142 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:35,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 165 transitions. [2025-02-06 19:09:35,459 INFO L240 hiAutomatonCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-02-06 19:09:35,464 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-02-06 19:09:35,464 INFO L432 stractBuchiCegarLoop]: Abstraction has 143 states and 165 transitions. [2025-02-06 19:09:35,464 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-06 19:09:35,464 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 143 states and 165 transitions. [2025-02-06 19:09:35,465 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:35,465 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:35,465 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:35,465 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 18, 18, 1, 1, 1] [2025-02-06 19:09:35,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:35,465 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:35,465 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:35,466 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:35,466 INFO L85 PathProgramCache]: Analyzing trace with hash 155621181, now seen corresponding path program 36 times [2025-02-06 19:09:35,466 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:35,466 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150227998] [2025-02-06 19:09:35,466 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:35,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:35,480 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 77 statements into 19 equivalence classes. [2025-02-06 19:09:35,589 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) and asserted 77 of 77 statements. [2025-02-06 19:09:35,589 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2025-02-06 19:09:35,589 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:35,589 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:35,594 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-02-06 19:09:35,622 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-02-06 19:09:35,622 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:35,623 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:35,628 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:35,629 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:35,629 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 20 times [2025-02-06 19:09:35,629 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:35,629 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862178698] [2025-02-06 19:09:35,629 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:35,629 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:35,631 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:35,632 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:35,632 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:35,632 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:35,632 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:35,633 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:35,633 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:35,633 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:35,633 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:35,635 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:35,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:35,635 INFO L85 PathProgramCache]: Analyzing trace with hash 1840917289, now seen corresponding path program 37 times [2025-02-06 19:09:35,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:35,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155497140] [2025-02-06 19:09:35,635 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:35,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:35,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 19:09:35,653 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 19:09:35,653 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:35,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:36,418 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 477 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:36,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:36,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155497140] [2025-02-06 19:09:36,419 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [155497140] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:36,419 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2050066286] [2025-02-06 19:09:36,419 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:36,419 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:36,419 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:36,422 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:36,423 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2025-02-06 19:09:36,519 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 19:09:36,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 19:09:36,556 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:36,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:36,558 INFO L256 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2025-02-06 19:09:36,560 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:37,373 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:37,373 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:37,991 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:37,992 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2050066286] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:37,992 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:37,992 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41] total 63 [2025-02-06 19:09:37,992 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [934744728] [2025-02-06 19:09:37,992 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:38,033 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:38,034 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2025-02-06 19:09:38,035 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=3084, Unknown=0, NotChecked=0, Total=4032 [2025-02-06 19:09:38,035 INFO L87 Difference]: Start difference. First operand 143 states and 165 transitions. cyclomatic complexity: 25 Second operand has 64 states, 63 states have (on average 2.3015873015873014) internal successors, (145), 64 states have internal predecessors, (145), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:38,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:38,841 INFO L93 Difference]: Finished difference Result 505 states and 588 transitions. [2025-02-06 19:09:38,841 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 505 states and 588 transitions. [2025-02-06 19:09:38,845 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:38,846 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 505 states to 275 states and 319 transitions. [2025-02-06 19:09:38,846 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 255 [2025-02-06 19:09:38,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 255 [2025-02-06 19:09:38,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 275 states and 319 transitions. [2025-02-06 19:09:38,846 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:38,846 INFO L218 hiAutomatonCegarLoop]: Abstraction has 275 states and 319 transitions. [2025-02-06 19:09:38,847 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 275 states and 319 transitions. [2025-02-06 19:09:38,848 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 275 to 150. [2025-02-06 19:09:38,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 150 states, 150 states have (on average 1.1533333333333333) internal successors, (173), 149 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:38,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 173 transitions. [2025-02-06 19:09:38,852 INFO L240 hiAutomatonCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-02-06 19:09:38,852 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-02-06 19:09:38,852 INFO L432 stractBuchiCegarLoop]: Abstraction has 150 states and 173 transitions. [2025-02-06 19:09:38,852 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-02-06 19:09:38,853 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 150 states and 173 transitions. [2025-02-06 19:09:38,853 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:38,853 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:38,853 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:38,854 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 19, 19, 1, 1, 1] [2025-02-06 19:09:38,854 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:38,854 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:38,854 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:38,855 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:38,856 INFO L85 PathProgramCache]: Analyzing trace with hash -436160697, now seen corresponding path program 38 times [2025-02-06 19:09:38,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:38,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1103882743] [2025-02-06 19:09:38,857 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:38,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:38,878 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 81 statements into 2 equivalence classes. [2025-02-06 19:09:38,913 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 81 of 81 statements. [2025-02-06 19:09:38,913 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:38,914 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:38,914 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:38,918 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-02-06 19:09:38,959 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-02-06 19:09:38,959 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:38,959 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:38,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:38,966 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:38,966 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 21 times [2025-02-06 19:09:38,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:38,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [113710103] [2025-02-06 19:09:38,966 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:38,966 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:38,969 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:38,969 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:38,969 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:09:38,969 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:38,969 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:38,970 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:38,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:38,970 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:38,970 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:38,972 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:38,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:38,972 INFO L85 PathProgramCache]: Analyzing trace with hash -1387227425, now seen corresponding path program 39 times [2025-02-06 19:09:38,972 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:38,972 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [954005635] [2025-02-06 19:09:38,973 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:38,973 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:38,982 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-02-06 19:09:39,280 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-02-06 19:09:39,280 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-02-06 19:09:39,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:40,060 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 532 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:40,060 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:40,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [954005635] [2025-02-06 19:09:40,061 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [954005635] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:40,061 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [836191906] [2025-02-06 19:09:40,061 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:40,061 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:40,061 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:40,063 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:40,064 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2025-02-06 19:09:40,159 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 84 statements into 21 equivalence classes. [2025-02-06 19:09:41,080 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 84 of 84 statements. [2025-02-06 19:09:41,080 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-02-06 19:09:41,080 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:41,086 INFO L256 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2025-02-06 19:09:41,087 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:41,825 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:41,825 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:42,354 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:42,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [836191906] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:42,354 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:42,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43] total 66 [2025-02-06 19:09:42,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [249134365] [2025-02-06 19:09:42,354 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:42,384 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:42,385 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-02-06 19:09:42,386 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1037, Invalid=3385, Unknown=0, NotChecked=0, Total=4422 [2025-02-06 19:09:42,386 INFO L87 Difference]: Start difference. First operand 150 states and 173 transitions. cyclomatic complexity: 26 Second operand has 67 states, 66 states have (on average 2.303030303030303) internal successors, (152), 67 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:43,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:43,188 INFO L93 Difference]: Finished difference Result 530 states and 617 transitions. [2025-02-06 19:09:43,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 530 states and 617 transitions. [2025-02-06 19:09:43,190 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:43,191 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 530 states to 288 states and 334 transitions. [2025-02-06 19:09:43,191 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 267 [2025-02-06 19:09:43,191 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 267 [2025-02-06 19:09:43,191 INFO L73 IsDeterministic]: Start isDeterministic. Operand 288 states and 334 transitions. [2025-02-06 19:09:43,196 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:43,196 INFO L218 hiAutomatonCegarLoop]: Abstraction has 288 states and 334 transitions. [2025-02-06 19:09:43,196 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 288 states and 334 transitions. [2025-02-06 19:09:43,197 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 288 to 157. [2025-02-06 19:09:43,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157 states, 157 states have (on average 1.1528662420382165) internal successors, (181), 156 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:43,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 181 transitions. [2025-02-06 19:09:43,198 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-02-06 19:09:43,201 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-02-06 19:09:43,202 INFO L432 stractBuchiCegarLoop]: Abstraction has 157 states and 181 transitions. [2025-02-06 19:09:43,202 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-02-06 19:09:43,202 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157 states and 181 transitions. [2025-02-06 19:09:43,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:43,203 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:43,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:43,203 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 20, 20, 1, 1, 1] [2025-02-06 19:09:43,203 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:43,203 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:43,204 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:43,204 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:43,204 INFO L85 PathProgramCache]: Analyzing trace with hash 1226302461, now seen corresponding path program 40 times [2025-02-06 19:09:43,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:43,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87087154] [2025-02-06 19:09:43,204 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:43,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:43,226 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 85 statements into 2 equivalence classes. [2025-02-06 19:09:43,273 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 85 of 85 statements. [2025-02-06 19:09:43,273 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:43,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:43,274 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:43,280 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 85 statements into 1 equivalence classes. [2025-02-06 19:09:43,315 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 85 of 85 statements. [2025-02-06 19:09:43,315 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:43,315 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:43,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:43,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:43,325 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 22 times [2025-02-06 19:09:43,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:43,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824578566] [2025-02-06 19:09:43,325 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:43,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:43,327 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-06 19:09:43,328 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:43,328 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:43,328 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:43,328 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:43,329 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:43,329 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:43,329 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:43,329 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:43,331 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:43,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:43,331 INFO L85 PathProgramCache]: Analyzing trace with hash -215177623, now seen corresponding path program 41 times [2025-02-06 19:09:43,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:43,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [170760917] [2025-02-06 19:09:43,332 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:43,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:43,345 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-02-06 19:09:43,382 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-02-06 19:09:43,382 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-02-06 19:09:43,382 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:44,273 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:44,273 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:44,273 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [170760917] [2025-02-06 19:09:44,274 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [170760917] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:44,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1874794787] [2025-02-06 19:09:44,274 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:44,274 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:44,274 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:44,277 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:44,278 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2025-02-06 19:09:44,385 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 88 statements into 22 equivalence classes. [2025-02-06 19:09:45,470 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-02-06 19:09:45,470 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-02-06 19:09:45,470 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:45,475 INFO L256 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2025-02-06 19:09:45,477 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:46,248 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:46,248 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:46,848 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:46,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1874794787] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:46,848 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:46,848 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45] total 67 [2025-02-06 19:09:46,848 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1083126654] [2025-02-06 19:09:46,848 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:46,881 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:46,882 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2025-02-06 19:09:46,882 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2025-02-06 19:09:46,883 INFO L87 Difference]: Start difference. First operand 157 states and 181 transitions. cyclomatic complexity: 27 Second operand has 68 states, 67 states have (on average 2.283582089552239) internal successors, (153), 68 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:47,749 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:47,749 INFO L93 Difference]: Finished difference Result 555 states and 646 transitions. [2025-02-06 19:09:47,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 555 states and 646 transitions. [2025-02-06 19:09:47,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:47,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 555 states to 301 states and 349 transitions. [2025-02-06 19:09:47,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 279 [2025-02-06 19:09:47,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 279 [2025-02-06 19:09:47,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 301 states and 349 transitions. [2025-02-06 19:09:47,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:47,758 INFO L218 hiAutomatonCegarLoop]: Abstraction has 301 states and 349 transitions. [2025-02-06 19:09:47,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states and 349 transitions. [2025-02-06 19:09:47,761 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 164. [2025-02-06 19:09:47,765 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1524390243902438) internal successors, (189), 163 states have internal predecessors, (189), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:47,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 189 transitions. [2025-02-06 19:09:47,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-02-06 19:09:47,770 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-02-06 19:09:47,770 INFO L432 stractBuchiCegarLoop]: Abstraction has 164 states and 189 transitions. [2025-02-06 19:09:47,770 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-02-06 19:09:47,773 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 189 transitions. [2025-02-06 19:09:47,773 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:47,774 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:47,774 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:47,774 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 21, 21, 1, 1, 1] [2025-02-06 19:09:47,774 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:47,774 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:47,775 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:47,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:47,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1842596729, now seen corresponding path program 42 times [2025-02-06 19:09:47,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:47,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466846285] [2025-02-06 19:09:47,775 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:47,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:47,789 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 22 equivalence classes. [2025-02-06 19:09:47,973 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:09:47,973 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2025-02-06 19:09:47,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:47,973 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:47,978 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-02-06 19:09:48,028 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-02-06 19:09:48,028 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:48,028 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:48,035 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:48,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:48,036 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 23 times [2025-02-06 19:09:48,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:48,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [188334910] [2025-02-06 19:09:48,036 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:48,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:48,038 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:48,039 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:48,039 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:09:48,039 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:48,039 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:48,039 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:48,040 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:48,040 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:48,040 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:48,042 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:48,042 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:48,043 INFO L85 PathProgramCache]: Analyzing trace with hash 1177883039, now seen corresponding path program 43 times [2025-02-06 19:09:48,043 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:48,043 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [727746234] [2025-02-06 19:09:48,043 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:48,043 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:48,053 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-02-06 19:09:48,062 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-02-06 19:09:48,062 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:48,062 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:49,001 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 651 proven. 317 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:49,001 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:49,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [727746234] [2025-02-06 19:09:49,002 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [727746234] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:49,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1879463348] [2025-02-06 19:09:49,002 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:49,002 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:49,002 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:49,004 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:49,006 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2025-02-06 19:09:49,113 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-02-06 19:09:49,155 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-02-06 19:09:49,155 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:49,155 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:49,157 INFO L256 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-02-06 19:09:49,159 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:49,964 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:49,964 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:50,558 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:50,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1879463348] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:50,559 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:50,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47] total 72 [2025-02-06 19:09:50,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1401204447] [2025-02-06 19:09:50,559 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:50,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:50,585 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2025-02-06 19:09:50,586 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=4029, Unknown=0, NotChecked=0, Total=5256 [2025-02-06 19:09:50,587 INFO L87 Difference]: Start difference. First operand 164 states and 189 transitions. cyclomatic complexity: 28 Second operand has 73 states, 72 states have (on average 2.3055555555555554) internal successors, (166), 73 states have internal predecessors, (166), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:51,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:51,350 INFO L93 Difference]: Finished difference Result 580 states and 675 transitions. [2025-02-06 19:09:51,350 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 580 states and 675 transitions. [2025-02-06 19:09:51,352 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:51,353 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 580 states to 314 states and 364 transitions. [2025-02-06 19:09:51,353 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 291 [2025-02-06 19:09:51,353 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 291 [2025-02-06 19:09:51,353 INFO L73 IsDeterministic]: Start isDeterministic. Operand 314 states and 364 transitions. [2025-02-06 19:09:51,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:51,353 INFO L218 hiAutomatonCegarLoop]: Abstraction has 314 states and 364 transitions. [2025-02-06 19:09:51,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states and 364 transitions. [2025-02-06 19:09:51,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 171. [2025-02-06 19:09:51,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 171 states, 171 states have (on average 1.152046783625731) internal successors, (197), 170 states have internal predecessors, (197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:51,356 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 197 transitions. [2025-02-06 19:09:51,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-02-06 19:09:51,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2025-02-06 19:09:51,359 INFO L432 stractBuchiCegarLoop]: Abstraction has 171 states and 197 transitions. [2025-02-06 19:09:51,359 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-02-06 19:09:51,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 171 states and 197 transitions. [2025-02-06 19:09:51,360 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:51,360 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:51,360 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:51,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 22, 22, 1, 1, 1] [2025-02-06 19:09:51,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:51,362 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:51,362 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:51,362 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:51,362 INFO L85 PathProgramCache]: Analyzing trace with hash 543449277, now seen corresponding path program 44 times [2025-02-06 19:09:51,362 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:51,362 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292420334] [2025-02-06 19:09:51,363 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:09:51,363 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:51,374 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 93 statements into 2 equivalence classes. [2025-02-06 19:09:51,416 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 93 of 93 statements. [2025-02-06 19:09:51,417 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:09:51,417 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:51,417 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:51,421 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-02-06 19:09:51,474 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-02-06 19:09:51,474 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:51,474 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:51,484 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:51,485 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:51,485 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 24 times [2025-02-06 19:09:51,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:51,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011193720] [2025-02-06 19:09:51,485 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:09:51,485 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:51,487 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:51,488 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:51,488 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:09:51,488 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:51,488 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:51,489 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:51,489 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:51,489 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:51,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:51,491 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:51,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:51,491 INFO L85 PathProgramCache]: Analyzing trace with hash -2129268311, now seen corresponding path program 45 times [2025-02-06 19:09:51,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:51,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1143400480] [2025-02-06 19:09:51,491 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:51,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:51,502 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-02-06 19:09:51,780 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-02-06 19:09:51,780 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-02-06 19:09:51,781 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:52,783 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 715 proven. 343 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:52,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:52,783 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1143400480] [2025-02-06 19:09:52,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1143400480] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:52,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [903367057] [2025-02-06 19:09:52,784 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:09:52,784 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:52,784 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:52,786 INFO L229 MonitoredProcess]: Starting monitored process 40 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:52,788 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (40)] Waiting until timeout for monitored process [2025-02-06 19:09:52,906 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 96 statements into 24 equivalence classes. [2025-02-06 19:09:55,274 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 96 of 96 statements. [2025-02-06 19:09:55,274 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-02-06 19:09:55,274 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:55,280 INFO L256 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-02-06 19:09:55,282 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:09:56,173 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:56,173 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:09:56,845 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:56,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [903367057] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:09:56,846 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:09:56,846 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49] total 75 [2025-02-06 19:09:56,846 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1877299896] [2025-02-06 19:09:56,846 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:09:56,876 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:09:56,877 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2025-02-06 19:09:56,878 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=4372, Unknown=0, NotChecked=0, Total=5700 [2025-02-06 19:09:56,878 INFO L87 Difference]: Start difference. First operand 171 states and 197 transitions. cyclomatic complexity: 29 Second operand has 76 states, 75 states have (on average 2.3066666666666666) internal successors, (173), 76 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:57,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:09:57,711 INFO L93 Difference]: Finished difference Result 605 states and 704 transitions. [2025-02-06 19:09:57,711 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 605 states and 704 transitions. [2025-02-06 19:09:57,714 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:57,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 605 states to 327 states and 379 transitions. [2025-02-06 19:09:57,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 303 [2025-02-06 19:09:57,715 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 303 [2025-02-06 19:09:57,715 INFO L73 IsDeterministic]: Start isDeterministic. Operand 327 states and 379 transitions. [2025-02-06 19:09:57,715 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:09:57,716 INFO L218 hiAutomatonCegarLoop]: Abstraction has 327 states and 379 transitions. [2025-02-06 19:09:57,716 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states and 379 transitions. [2025-02-06 19:09:57,720 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 178. [2025-02-06 19:09:57,720 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 178 states, 178 states have (on average 1.151685393258427) internal successors, (205), 177 states have internal predecessors, (205), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:09:57,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 205 transitions. [2025-02-06 19:09:57,722 INFO L240 hiAutomatonCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-02-06 19:09:57,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2025-02-06 19:09:57,722 INFO L432 stractBuchiCegarLoop]: Abstraction has 178 states and 205 transitions. [2025-02-06 19:09:57,723 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-02-06 19:09:57,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 178 states and 205 transitions. [2025-02-06 19:09:57,723 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:09:57,723 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:09:57,723 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:09:57,724 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 1, 1, 1] [2025-02-06 19:09:57,724 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:09:57,724 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:57,725 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:09:57,725 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:57,725 INFO L85 PathProgramCache]: Analyzing trace with hash 111968711, now seen corresponding path program 46 times [2025-02-06 19:09:57,725 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:57,725 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [403053076] [2025-02-06 19:09:57,725 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:09:57,725 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:57,737 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 97 statements into 2 equivalence classes. [2025-02-06 19:09:57,799 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 97 of 97 statements. [2025-02-06 19:09:57,800 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:09:57,800 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:57,800 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:57,805 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 97 statements into 1 equivalence classes. [2025-02-06 19:09:57,854 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 97 of 97 statements. [2025-02-06 19:09:57,855 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:57,855 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:57,863 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:57,864 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:57,864 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 25 times [2025-02-06 19:09:57,864 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:57,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461282484] [2025-02-06 19:09:57,864 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:09:57,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:57,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:57,867 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:57,867 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:57,867 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:57,867 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:09:57,867 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:09:57,867 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:09:57,868 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:09:57,868 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:09:57,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:09:57,873 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:09:57,873 INFO L85 PathProgramCache]: Analyzing trace with hash -1529693089, now seen corresponding path program 47 times [2025-02-06 19:09:57,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:09:57,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1541928272] [2025-02-06 19:09:57,873 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:57,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:09:57,886 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-02-06 19:09:57,925 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-02-06 19:09:57,925 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-02-06 19:09:57,925 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:09:58,997 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:09:58,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:09:58,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1541928272] [2025-02-06 19:09:58,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1541928272] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:09:58,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1214159441] [2025-02-06 19:09:58,997 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:09:58,997 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:09:58,997 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:09:59,000 INFO L229 MonitoredProcess]: Starting monitored process 41 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:09:59,001 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (41)] Waiting until timeout for monitored process [2025-02-06 19:09:59,124 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 100 statements into 25 equivalence classes. [2025-02-06 19:10:02,216 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-02-06 19:10:02,216 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-02-06 19:10:02,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:02,223 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2025-02-06 19:10:02,224 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:10:03,170 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:03,170 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:10:03,878 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:03,879 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1214159441] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:10:03,879 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:10:03,879 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51] total 76 [2025-02-06 19:10:03,879 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2015235590] [2025-02-06 19:10:03,879 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:10:03,909 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:10:03,910 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2025-02-06 19:10:03,911 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1376, Invalid=4476, Unknown=0, NotChecked=0, Total=5852 [2025-02-06 19:10:03,911 INFO L87 Difference]: Start difference. First operand 178 states and 205 transitions. cyclomatic complexity: 30 Second operand has 77 states, 76 states have (on average 2.289473684210526) internal successors, (174), 77 states have internal predecessors, (174), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:04,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:10:04,859 INFO L93 Difference]: Finished difference Result 630 states and 733 transitions. [2025-02-06 19:10:04,859 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 630 states and 733 transitions. [2025-02-06 19:10:04,861 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:04,862 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 630 states to 340 states and 394 transitions. [2025-02-06 19:10:04,862 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 315 [2025-02-06 19:10:04,862 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 315 [2025-02-06 19:10:04,862 INFO L73 IsDeterministic]: Start isDeterministic. Operand 340 states and 394 transitions. [2025-02-06 19:10:04,862 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:10:04,862 INFO L218 hiAutomatonCegarLoop]: Abstraction has 340 states and 394 transitions. [2025-02-06 19:10:04,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states and 394 transitions. [2025-02-06 19:10:04,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 185. [2025-02-06 19:10:04,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 185 states, 185 states have (on average 1.1513513513513514) internal successors, (213), 184 states have internal predecessors, (213), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:04,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 213 transitions. [2025-02-06 19:10:04,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-02-06 19:10:04,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2025-02-06 19:10:04,867 INFO L432 stractBuchiCegarLoop]: Abstraction has 185 states and 213 transitions. [2025-02-06 19:10:04,867 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-02-06 19:10:04,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 185 states and 213 transitions. [2025-02-06 19:10:04,868 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:04,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:10:04,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:10:04,868 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 1, 1, 1] [2025-02-06 19:10:04,868 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:10:04,868 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:04,868 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:04,869 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:04,869 INFO L85 PathProgramCache]: Analyzing trace with hash 1581780349, now seen corresponding path program 48 times [2025-02-06 19:10:04,869 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:04,869 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1152290630] [2025-02-06 19:10:04,869 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:10:04,869 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:04,881 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 101 statements into 25 equivalence classes. [2025-02-06 19:10:05,069 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) and asserted 101 of 101 statements. [2025-02-06 19:10:05,070 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2025-02-06 19:10:05,070 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:05,070 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:05,075 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 101 statements into 1 equivalence classes. [2025-02-06 19:10:05,129 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 101 of 101 statements. [2025-02-06 19:10:05,129 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:05,129 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:05,141 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:05,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:05,144 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 26 times [2025-02-06 19:10:05,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:05,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1366944421] [2025-02-06 19:10:05,147 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:10:05,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:05,150 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:05,151 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:05,151 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:10:05,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:05,151 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:05,151 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:05,151 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:05,151 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:05,152 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:05,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:05,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:05,153 INFO L85 PathProgramCache]: Analyzing trace with hash -1562768151, now seen corresponding path program 49 times [2025-02-06 19:10:05,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:05,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1023614934] [2025-02-06 19:10:05,153 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:10:05,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:05,169 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-02-06 19:10:05,178 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-02-06 19:10:05,179 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:05,179 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:06,351 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 852 proven. 398 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:06,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:10:06,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1023614934] [2025-02-06 19:10:06,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1023614934] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:10:06,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [715434901] [2025-02-06 19:10:06,352 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:10:06,352 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:10:06,352 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:10:06,354 INFO L229 MonitoredProcess]: Starting monitored process 42 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:10:06,356 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (42)] Waiting until timeout for monitored process [2025-02-06 19:10:06,491 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-02-06 19:10:06,537 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-02-06 19:10:06,537 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:06,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:06,540 INFO L256 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2025-02-06 19:10:06,542 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:10:07,552 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:07,552 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:10:08,349 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:08,350 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [715434901] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:10:08,350 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:10:08,350 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53] total 81 [2025-02-06 19:10:08,350 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [370505493] [2025-02-06 19:10:08,350 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:10:08,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:10:08,383 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2025-02-06 19:10:08,384 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1542, Invalid=5100, Unknown=0, NotChecked=0, Total=6642 [2025-02-06 19:10:08,384 INFO L87 Difference]: Start difference. First operand 185 states and 213 transitions. cyclomatic complexity: 31 Second operand has 82 states, 81 states have (on average 2.308641975308642) internal successors, (187), 82 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:09,441 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:10:09,441 INFO L93 Difference]: Finished difference Result 655 states and 762 transitions. [2025-02-06 19:10:09,441 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 655 states and 762 transitions. [2025-02-06 19:10:09,443 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:09,445 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 655 states to 353 states and 409 transitions. [2025-02-06 19:10:09,445 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 327 [2025-02-06 19:10:09,445 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 327 [2025-02-06 19:10:09,445 INFO L73 IsDeterministic]: Start isDeterministic. Operand 353 states and 409 transitions. [2025-02-06 19:10:09,445 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:10:09,445 INFO L218 hiAutomatonCegarLoop]: Abstraction has 353 states and 409 transitions. [2025-02-06 19:10:09,446 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 353 states and 409 transitions. [2025-02-06 19:10:09,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 353 to 192. [2025-02-06 19:10:09,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 192 states, 192 states have (on average 1.1510416666666667) internal successors, (221), 191 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:09,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 221 transitions. [2025-02-06 19:10:09,449 INFO L240 hiAutomatonCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-02-06 19:10:09,452 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2025-02-06 19:10:09,452 INFO L432 stractBuchiCegarLoop]: Abstraction has 192 states and 221 transitions. [2025-02-06 19:10:09,452 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-02-06 19:10:09,452 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 192 states and 221 transitions. [2025-02-06 19:10:09,453 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:09,453 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:10:09,453 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:10:09,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 1, 1, 1] [2025-02-06 19:10:09,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:10:09,454 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:09,454 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:09,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:09,454 INFO L85 PathProgramCache]: Analyzing trace with hash 283483911, now seen corresponding path program 50 times [2025-02-06 19:10:09,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:09,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [425889345] [2025-02-06 19:10:09,455 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:10:09,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:09,479 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 105 statements into 2 equivalence classes. [2025-02-06 19:10:09,582 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 105 of 105 statements. [2025-02-06 19:10:09,582 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:10:09,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:09,582 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:09,590 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 105 statements into 1 equivalence classes. [2025-02-06 19:10:09,692 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 105 of 105 statements. [2025-02-06 19:10:09,692 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:09,692 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:09,702 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:09,702 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:09,702 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 27 times [2025-02-06 19:10:09,702 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:09,702 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [992935605] [2025-02-06 19:10:09,702 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:10:09,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:09,705 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:09,706 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:09,706 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:10:09,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:09,706 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:09,706 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:09,707 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:09,707 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:09,707 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:09,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:09,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:09,713 INFO L85 PathProgramCache]: Analyzing trace with hash 1363515167, now seen corresponding path program 51 times [2025-02-06 19:10:09,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:09,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207037653] [2025-02-06 19:10:09,713 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:10:09,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:09,727 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-02-06 19:10:10,305 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-02-06 19:10:10,305 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-02-06 19:10:10,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:11,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 925 proven. 427 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:11,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:10:11,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1207037653] [2025-02-06 19:10:11,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1207037653] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:10:11,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [963965664] [2025-02-06 19:10:11,467 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:10:11,467 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:10:11,467 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:10:11,470 INFO L229 MonitoredProcess]: Starting monitored process 43 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:10:11,471 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (43)] Waiting until timeout for monitored process [2025-02-06 19:10:11,613 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 108 statements into 27 equivalence classes. [2025-02-06 19:10:14,870 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 108 of 108 statements. [2025-02-06 19:10:14,870 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-02-06 19:10:14,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:14,877 INFO L256 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjuncts are in the unsatisfiable core [2025-02-06 19:10:14,879 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:10:15,868 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:15,869 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:10:16,558 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:16,558 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [963965664] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:10:16,559 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:10:16,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55] total 84 [2025-02-06 19:10:16,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848003983] [2025-02-06 19:10:16,559 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:10:16,584 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:10:16,585 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2025-02-06 19:10:16,588 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1655, Invalid=5485, Unknown=0, NotChecked=0, Total=7140 [2025-02-06 19:10:16,588 INFO L87 Difference]: Start difference. First operand 192 states and 221 transitions. cyclomatic complexity: 32 Second operand has 85 states, 84 states have (on average 2.3095238095238093) internal successors, (194), 85 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:17,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:10:17,692 INFO L93 Difference]: Finished difference Result 680 states and 791 transitions. [2025-02-06 19:10:17,692 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 680 states and 791 transitions. [2025-02-06 19:10:17,694 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:17,695 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 680 states to 366 states and 424 transitions. [2025-02-06 19:10:17,695 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 339 [2025-02-06 19:10:17,695 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 339 [2025-02-06 19:10:17,695 INFO L73 IsDeterministic]: Start isDeterministic. Operand 366 states and 424 transitions. [2025-02-06 19:10:17,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:10:17,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 366 states and 424 transitions. [2025-02-06 19:10:17,696 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 366 states and 424 transitions. [2025-02-06 19:10:17,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 199. [2025-02-06 19:10:17,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 199 states, 199 states have (on average 1.150753768844221) internal successors, (229), 198 states have internal predecessors, (229), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:17,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 229 transitions. [2025-02-06 19:10:17,698 INFO L240 hiAutomatonCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-02-06 19:10:17,699 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-02-06 19:10:17,703 INFO L432 stractBuchiCegarLoop]: Abstraction has 199 states and 229 transitions. [2025-02-06 19:10:17,703 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-02-06 19:10:17,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 199 states and 229 transitions. [2025-02-06 19:10:17,704 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:17,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:10:17,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:10:17,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 1, 1, 1] [2025-02-06 19:10:17,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:10:17,704 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:17,704 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:17,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:17,705 INFO L85 PathProgramCache]: Analyzing trace with hash -857806275, now seen corresponding path program 52 times [2025-02-06 19:10:17,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:17,705 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893417305] [2025-02-06 19:10:17,705 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:10:17,705 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:17,718 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 109 statements into 2 equivalence classes. [2025-02-06 19:10:17,791 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 109 of 109 statements. [2025-02-06 19:10:17,792 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:10:17,792 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:17,792 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:17,797 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 109 statements into 1 equivalence classes. [2025-02-06 19:10:17,862 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 109 of 109 statements. [2025-02-06 19:10:17,863 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:17,863 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:17,870 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:17,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:17,870 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 28 times [2025-02-06 19:10:17,871 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:17,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [169830441] [2025-02-06 19:10:17,871 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:10:17,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:17,875 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-06 19:10:17,875 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:17,875 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:10:17,875 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:17,875 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:17,876 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:17,876 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:17,876 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:17,876 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:17,878 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:17,878 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:17,878 INFO L85 PathProgramCache]: Analyzing trace with hash 148699177, now seen corresponding path program 53 times [2025-02-06 19:10:17,878 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:17,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764151232] [2025-02-06 19:10:17,878 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:10:17,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:17,891 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-02-06 19:10:17,974 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-02-06 19:10:17,974 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-02-06 19:10:17,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:19,239 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:19,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:10:19,240 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764151232] [2025-02-06 19:10:19,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764151232] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:10:19,240 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [637026625] [2025-02-06 19:10:19,240 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:10:19,240 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:10:19,240 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:10:19,242 INFO L229 MonitoredProcess]: Starting monitored process 44 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:10:19,244 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (44)] Waiting until timeout for monitored process [2025-02-06 19:10:19,390 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 112 statements into 28 equivalence classes. [2025-02-06 19:10:20,364 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-02-06 19:10:20,364 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-02-06 19:10:20,364 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:20,374 INFO L256 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 58 conjuncts are in the unsatisfiable core [2025-02-06 19:10:20,376 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:10:21,581 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:21,581 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:10:22,455 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:22,455 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [637026625] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:10:22,455 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:10:22,455 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57] total 85 [2025-02-06 19:10:22,455 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590456554] [2025-02-06 19:10:22,455 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:10:22,486 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:10:22,486 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2025-02-06 19:10:22,487 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1709, Invalid=5601, Unknown=0, NotChecked=0, Total=7310 [2025-02-06 19:10:22,487 INFO L87 Difference]: Start difference. First operand 199 states and 229 transitions. cyclomatic complexity: 33 Second operand has 86 states, 85 states have (on average 2.2941176470588234) internal successors, (195), 86 states have internal predecessors, (195), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:23,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:10:23,583 INFO L93 Difference]: Finished difference Result 705 states and 820 transitions. [2025-02-06 19:10:23,583 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 705 states and 820 transitions. [2025-02-06 19:10:23,584 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:23,587 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 705 states to 379 states and 439 transitions. [2025-02-06 19:10:23,587 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 351 [2025-02-06 19:10:23,587 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 351 [2025-02-06 19:10:23,587 INFO L73 IsDeterministic]: Start isDeterministic. Operand 379 states and 439 transitions. [2025-02-06 19:10:23,588 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:10:23,588 INFO L218 hiAutomatonCegarLoop]: Abstraction has 379 states and 439 transitions. [2025-02-06 19:10:23,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 379 states and 439 transitions. [2025-02-06 19:10:23,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 379 to 206. [2025-02-06 19:10:23,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206 states, 206 states have (on average 1.1504854368932038) internal successors, (237), 205 states have internal predecessors, (237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:23,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 237 transitions. [2025-02-06 19:10:23,593 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-02-06 19:10:23,594 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2025-02-06 19:10:23,594 INFO L432 stractBuchiCegarLoop]: Abstraction has 206 states and 237 transitions. [2025-02-06 19:10:23,598 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-02-06 19:10:23,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206 states and 237 transitions. [2025-02-06 19:10:23,599 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:23,599 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:10:23,599 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:10:23,600 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 1, 1, 1] [2025-02-06 19:10:23,600 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:10:23,600 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:23,600 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:23,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:23,600 INFO L85 PathProgramCache]: Analyzing trace with hash -1556378553, now seen corresponding path program 54 times [2025-02-06 19:10:23,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:23,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962183227] [2025-02-06 19:10:23,601 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:10:23,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:23,614 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 113 statements into 28 equivalence classes. [2025-02-06 19:10:23,996 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) and asserted 113 of 113 statements. [2025-02-06 19:10:23,996 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2025-02-06 19:10:23,997 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:23,997 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:24,001 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 113 statements into 1 equivalence classes. [2025-02-06 19:10:24,072 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 113 of 113 statements. [2025-02-06 19:10:24,072 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:24,072 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:24,080 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:24,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:24,080 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 29 times [2025-02-06 19:10:24,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:24,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [962685310] [2025-02-06 19:10:24,080 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:10:24,081 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:24,084 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:24,084 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:24,085 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:10:24,085 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:24,085 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:24,085 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:24,086 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:24,086 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:24,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:24,087 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:24,087 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:24,087 INFO L85 PathProgramCache]: Analyzing trace with hash -1901485601, now seen corresponding path program 55 times [2025-02-06 19:10:24,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:24,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637135312] [2025-02-06 19:10:24,088 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:10:24,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:24,100 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-02-06 19:10:24,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-02-06 19:10:24,114 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:24,114 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:25,345 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1080 proven. 488 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:25,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:10:25,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637135312] [2025-02-06 19:10:25,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637135312] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:10:25,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [942329858] [2025-02-06 19:10:25,346 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:10:25,346 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:10:25,346 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:10:25,349 INFO L229 MonitoredProcess]: Starting monitored process 45 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:10:25,350 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (45)] Waiting until timeout for monitored process [2025-02-06 19:10:25,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-02-06 19:10:25,561 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-02-06 19:10:25,561 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:25,562 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:25,571 INFO L256 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjuncts are in the unsatisfiable core [2025-02-06 19:10:25,572 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-06 19:10:26,539 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:26,539 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-06 19:10:27,305 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:27,306 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [942329858] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-06 19:10:27,306 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-06 19:10:27,306 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59] total 90 [2025-02-06 19:10:27,306 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [174865448] [2025-02-06 19:10:27,306 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-06 19:10:27,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:10:27,330 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2025-02-06 19:10:27,331 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6297, Unknown=0, NotChecked=0, Total=8190 [2025-02-06 19:10:27,331 INFO L87 Difference]: Start difference. First operand 206 states and 237 transitions. cyclomatic complexity: 34 Second operand has 91 states, 90 states have (on average 2.311111111111111) internal successors, (208), 91 states have internal predecessors, (208), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:28,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:10:28,477 INFO L93 Difference]: Finished difference Result 730 states and 849 transitions. [2025-02-06 19:10:28,477 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 730 states and 849 transitions. [2025-02-06 19:10:28,479 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:28,480 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 730 states to 392 states and 454 transitions. [2025-02-06 19:10:28,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 363 [2025-02-06 19:10:28,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 363 [2025-02-06 19:10:28,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 392 states and 454 transitions. [2025-02-06 19:10:28,481 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:10:28,481 INFO L218 hiAutomatonCegarLoop]: Abstraction has 392 states and 454 transitions. [2025-02-06 19:10:28,482 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 392 states and 454 transitions. [2025-02-06 19:10:28,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 392 to 213. [2025-02-06 19:10:28,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.1502347417840375) internal successors, (245), 212 states have internal predecessors, (245), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:10:28,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 245 transitions. [2025-02-06 19:10:28,484 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-02-06 19:10:28,485 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2025-02-06 19:10:28,485 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 245 transitions. [2025-02-06 19:10:28,485 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-02-06 19:10:28,485 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 245 transitions. [2025-02-06 19:10:28,486 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 12 [2025-02-06 19:10:28,486 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:10:28,486 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:10:28,486 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 1, 1, 1] [2025-02-06 19:10:28,486 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-06 19:10:28,486 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:28,486 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-06 19:10:28,487 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:28,487 INFO L85 PathProgramCache]: Analyzing trace with hash -247138563, now seen corresponding path program 56 times [2025-02-06 19:10:28,487 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:28,487 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1688754087] [2025-02-06 19:10:28,487 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:10:28,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:28,500 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 117 statements into 2 equivalence classes. [2025-02-06 19:10:28,576 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 117 of 117 statements. [2025-02-06 19:10:28,576 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-06 19:10:28,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:28,576 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:28,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 117 statements into 1 equivalence classes. [2025-02-06 19:10:28,706 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 117 of 117 statements. [2025-02-06 19:10:28,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:28,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:28,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:28,716 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:28,716 INFO L85 PathProgramCache]: Analyzing trace with hash 56293, now seen corresponding path program 30 times [2025-02-06 19:10:28,716 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:28,716 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1803615907] [2025-02-06 19:10:28,716 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:10:28,717 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:28,720 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:28,720 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:28,720 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:10:28,720 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:28,720 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:10:28,721 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-06 19:10:28,721 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-06 19:10:28,721 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:10:28,721 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:10:28,723 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:10:28,724 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:10:28,724 INFO L85 PathProgramCache]: Analyzing trace with hash -930958487, now seen corresponding path program 57 times [2025-02-06 19:10:28,724 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:10:28,724 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702651226] [2025-02-06 19:10:28,724 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:10:28,724 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:10:28,745 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes. [2025-02-06 19:10:29,410 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 120 of 120 statements. [2025-02-06 19:10:29,410 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-02-06 19:10:29,411 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:10:30,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1162 proven. 520 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:10:30,865 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:10:30,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702651226] [2025-02-06 19:10:30,865 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702651226] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-06 19:10:30,865 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2032072981] [2025-02-06 19:10:30,865 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:10:30,865 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-06 19:10:30,865 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:10:30,868 INFO L229 MonitoredProcess]: Starting monitored process 46 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-06 19:10:30,869 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (46)] Waiting until timeout for monitored process [2025-02-06 19:10:31,051 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 120 statements into 30 equivalence classes.