./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/locks/test_locks_14-1.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/locks/test_locks_14-1.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 1e1f6c8a80d54f6d4b7b413368cc99af6eca243b930331d178961d851b56afbd --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:12:42,243 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:12:42,295 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:12:42,299 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:12:42,299 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:12:42,299 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:12:42,314 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:12:42,315 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:12:42,315 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:12:42,315 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:12:42,315 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:12:42,315 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:12:42,315 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:12:42,316 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:12:42,316 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:12:42,316 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:12:42,318 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:12:42,319 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:12:42,319 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:12:42,319 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:12:42,319 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:12:42,320 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:12:42,320 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 1e1f6c8a80d54f6d4b7b413368cc99af6eca243b930331d178961d851b56afbd [2025-02-06 19:12:42,529 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:12:42,535 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:12:42,538 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:12:42,539 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:12:42,539 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:12:42,541 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/locks/test_locks_14-1.c [2025-02-06 19:12:43,713 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/86f47314d/0a624fd667a244f08b53121326ab3784/FLAG679299855 [2025-02-06 19:12:43,983 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:12:43,984 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/locks/test_locks_14-1.c [2025-02-06 19:12:43,992 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/86f47314d/0a624fd667a244f08b53121326ab3784/FLAG679299855 [2025-02-06 19:12:44,295 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/86f47314d/0a624fd667a244f08b53121326ab3784 [2025-02-06 19:12:44,297 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:12:44,298 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:12:44,299 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:12:44,299 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:12:44,302 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:12:44,303 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,305 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1863095e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44, skipping insertion in model container [2025-02-06 19:12:44,305 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,322 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:12:44,439 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:12:44,446 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:12:44,470 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:12:44,481 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:12:44,482 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44 WrapperNode [2025-02-06 19:12:44,482 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:12:44,483 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:12:44,483 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:12:44,483 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:12:44,487 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,493 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,509 INFO L138 Inliner]: procedures = 12, calls = 8, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 179 [2025-02-06 19:12:44,509 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:12:44,510 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:12:44,510 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:12:44,510 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:12:44,515 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,515 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,517 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,524 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:12:44,524 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,524 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,527 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,528 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,529 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,529 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,530 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:12:44,531 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:12:44,531 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:12:44,531 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:12:44,532 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (1/1) ... [2025-02-06 19:12:44,535 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:12:44,544 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:12:44,554 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:12:44,557 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:12:44,574 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:12:44,574 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:12:44,574 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:12:44,574 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:12:44,618 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:12:44,620 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:12:44,828 INFO L? ?]: Removed 32 outVars from TransFormulas that were not future-live. [2025-02-06 19:12:44,828 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:12:44,836 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:12:44,836 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:12:44,837 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:44 BoogieIcfgContainer [2025-02-06 19:12:44,837 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:12:44,839 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:12:44,839 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:12:44,843 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:12:44,843 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:12:44,844 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:12:44" (1/3) ... [2025-02-06 19:12:44,844 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@515ab8ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:12:44, skipping insertion in model container [2025-02-06 19:12:44,845 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:12:44,845 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:44" (2/3) ... [2025-02-06 19:12:44,846 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@515ab8ac and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:12:44, skipping insertion in model container [2025-02-06 19:12:44,846 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:12:44,846 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:44" (3/3) ... [2025-02-06 19:12:44,847 INFO L363 chiAutomizerObserver]: Analyzing ICFG test_locks_14-1.c [2025-02-06 19:12:44,878 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:12:44,878 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:12:44,879 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:12:44,879 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:12:44,879 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:12:44,879 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:12:44,879 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:12:44,879 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:12:44,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:44,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2025-02-06 19:12:44,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:44,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:44,898 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:44,899 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:44,899 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:12:44,899 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:44,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 44 [2025-02-06 19:12:44,901 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:44,901 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:44,901 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:44,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:44,906 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:44,906 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume 0 != main_~p1~0#1;main_~lk1~0#1 := 1;" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:44,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:44,910 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 1 times [2025-02-06 19:12:44,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:44,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [854578142] [2025-02-06 19:12:44,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:44,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:44,958 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:44,965 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:44,966 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:44,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:44,966 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:44,969 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:44,970 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:44,971 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:44,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:44,981 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:44,983 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:44,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1123980545, now seen corresponding path program 1 times [2025-02-06 19:12:44,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:44,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1702259154] [2025-02-06 19:12:44,983 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:44,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:44,989 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:44,997 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:44,997 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:44,997 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1702259154] [2025-02-06 19:12:45,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1702259154] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,078 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [637702353] [2025-02-06 19:12:45,078 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,081 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,082 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,106 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,106 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,107 INFO L87 Difference]: Start difference. First operand has 52 states, 51 states have (on average 1.8627450980392157) internal successors, (95), 51 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,147 INFO L93 Difference]: Finished difference Result 97 states and 177 transitions. [2025-02-06 19:12:45,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97 states and 177 transitions. [2025-02-06 19:12:45,153 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87 [2025-02-06 19:12:45,158 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97 states to 89 states and 143 transitions. [2025-02-06 19:12:45,159 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89 [2025-02-06 19:12:45,159 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89 [2025-02-06 19:12:45,160 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 143 transitions. [2025-02-06 19:12:45,160 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,160 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-02-06 19:12:45,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 143 transitions. [2025-02-06 19:12:45,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2025-02-06 19:12:45,190 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89 states, 89 states have (on average 1.6067415730337078) internal successors, (143), 88 states have internal predecessors, (143), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,193 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 143 transitions. [2025-02-06 19:12:45,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-02-06 19:12:45,195 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,197 INFO L432 stractBuchiCegarLoop]: Abstraction has 89 states and 143 transitions. [2025-02-06 19:12:45,197 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:12:45,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89 states and 143 transitions. [2025-02-06 19:12:45,198 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 87 [2025-02-06 19:12:45,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,199 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,199 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,199 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,199 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 2 times [2025-02-06 19:12:45,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176510298] [2025-02-06 19:12:45,200 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:12:45,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,203 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,205 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,205 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:12:45,205 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,205 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,206 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,209 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,210 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,210 INFO L85 PathProgramCache]: Analyzing trace with hash 869244000, now seen corresponding path program 1 times [2025-02-06 19:12:45,210 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93291223] [2025-02-06 19:12:45,210 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,215 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,224 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,224 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,269 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,269 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,269 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93291223] [2025-02-06 19:12:45,269 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93291223] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1246321533] [2025-02-06 19:12:45,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,270 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,270 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,270 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,270 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,270 INFO L87 Difference]: Start difference. First operand 89 states and 143 transitions. cyclomatic complexity: 56 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,290 INFO L93 Difference]: Finished difference Result 174 states and 278 transitions. [2025-02-06 19:12:45,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 174 states and 278 transitions. [2025-02-06 19:12:45,292 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 172 [2025-02-06 19:12:45,293 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 174 states to 174 states and 278 transitions. [2025-02-06 19:12:45,293 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 174 [2025-02-06 19:12:45,294 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 174 [2025-02-06 19:12:45,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 174 states and 278 transitions. [2025-02-06 19:12:45,294 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,294 INFO L218 hiAutomatonCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-02-06 19:12:45,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states and 278 transitions. [2025-02-06 19:12:45,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2025-02-06 19:12:45,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 174 states, 174 states have (on average 1.5977011494252873) internal successors, (278), 173 states have internal predecessors, (278), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 278 transitions. [2025-02-06 19:12:45,307 INFO L240 hiAutomatonCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-02-06 19:12:45,308 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,308 INFO L432 stractBuchiCegarLoop]: Abstraction has 174 states and 278 transitions. [2025-02-06 19:12:45,308 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:12:45,308 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 174 states and 278 transitions. [2025-02-06 19:12:45,310 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 172 [2025-02-06 19:12:45,312 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,313 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,313 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,314 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,314 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 3 times [2025-02-06 19:12:45,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,314 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [720464209] [2025-02-06 19:12:45,314 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:12:45,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,318 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,322 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,322 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:12:45,322 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,322 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,324 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,325 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,326 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,327 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,327 INFO L85 PathProgramCache]: Analyzing trace with hash 1830858017, now seen corresponding path program 1 times [2025-02-06 19:12:45,327 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [778443973] [2025-02-06 19:12:45,327 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,336 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,336 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,336 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [778443973] [2025-02-06 19:12:45,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [778443973] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [247917322] [2025-02-06 19:12:45,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,365 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,365 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,365 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,365 INFO L87 Difference]: Start difference. First operand 174 states and 278 transitions. cyclomatic complexity: 108 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,384 INFO L93 Difference]: Finished difference Result 342 states and 542 transitions. [2025-02-06 19:12:45,384 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 542 transitions. [2025-02-06 19:12:45,387 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 340 [2025-02-06 19:12:45,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 542 transitions. [2025-02-06 19:12:45,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 342 [2025-02-06 19:12:45,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 342 [2025-02-06 19:12:45,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 542 transitions. [2025-02-06 19:12:45,395 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-02-06 19:12:45,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 542 transitions. [2025-02-06 19:12:45,423 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2025-02-06 19:12:45,424 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 342 states have (on average 1.5847953216374269) internal successors, (542), 341 states have internal predecessors, (542), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,425 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 542 transitions. [2025-02-06 19:12:45,425 INFO L240 hiAutomatonCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-02-06 19:12:45,428 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,429 INFO L432 stractBuchiCegarLoop]: Abstraction has 342 states and 542 transitions. [2025-02-06 19:12:45,429 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:12:45,430 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 542 transitions. [2025-02-06 19:12:45,431 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 340 [2025-02-06 19:12:45,431 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,431 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,432 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,432 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,432 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,432 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 4 times [2025-02-06 19:12:45,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830705286] [2025-02-06 19:12:45,432 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:12:45,433 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,442 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 19:12:45,443 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,443 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:12:45,443 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,443 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,445 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,446 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,446 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,451 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1861877824, now seen corresponding path program 1 times [2025-02-06 19:12:45,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1589643665] [2025-02-06 19:12:45,452 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,456 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,462 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,465 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,466 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,497 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1589643665] [2025-02-06 19:12:45,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1589643665] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,498 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2047802926] [2025-02-06 19:12:45,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,498 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,499 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,499 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,500 INFO L87 Difference]: Start difference. First operand 342 states and 542 transitions. cyclomatic complexity: 208 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,522 INFO L93 Difference]: Finished difference Result 674 states and 1058 transitions. [2025-02-06 19:12:45,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 674 states and 1058 transitions. [2025-02-06 19:12:45,526 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 672 [2025-02-06 19:12:45,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 674 states to 674 states and 1058 transitions. [2025-02-06 19:12:45,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 674 [2025-02-06 19:12:45,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 674 [2025-02-06 19:12:45,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 674 states and 1058 transitions. [2025-02-06 19:12:45,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-02-06 19:12:45,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 674 states and 1058 transitions. [2025-02-06 19:12:45,549 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 674 to 674. [2025-02-06 19:12:45,550 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 674 states, 674 states have (on average 1.5697329376854599) internal successors, (1058), 673 states have internal predecessors, (1058), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 674 states to 674 states and 1058 transitions. [2025-02-06 19:12:45,555 INFO L240 hiAutomatonCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-02-06 19:12:45,556 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,556 INFO L432 stractBuchiCegarLoop]: Abstraction has 674 states and 1058 transitions. [2025-02-06 19:12:45,557 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:12:45,557 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 674 states and 1058 transitions. [2025-02-06 19:12:45,560 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 672 [2025-02-06 19:12:45,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,562 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,562 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,562 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 5 times [2025-02-06 19:12:45,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [655053674] [2025-02-06 19:12:45,562 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:12:45,562 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,565 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,567 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,568 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:12:45,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,568 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,569 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,571 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,572 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,572 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,574 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,575 INFO L85 PathProgramCache]: Analyzing trace with hash -215331519, now seen corresponding path program 1 times [2025-02-06 19:12:45,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [955568908] [2025-02-06 19:12:45,575 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,580 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,582 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,582 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,612 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,612 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [955568908] [2025-02-06 19:12:45,612 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [955568908] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,613 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,613 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,613 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793824169] [2025-02-06 19:12:45,613 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,613 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,613 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,613 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,613 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,614 INFO L87 Difference]: Start difference. First operand 674 states and 1058 transitions. cyclomatic complexity: 400 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,639 INFO L93 Difference]: Finished difference Result 1330 states and 2066 transitions. [2025-02-06 19:12:45,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1330 states and 2066 transitions. [2025-02-06 19:12:45,649 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 1328 [2025-02-06 19:12:45,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1330 states to 1330 states and 2066 transitions. [2025-02-06 19:12:45,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1330 [2025-02-06 19:12:45,656 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1330 [2025-02-06 19:12:45,656 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1330 states and 2066 transitions. [2025-02-06 19:12:45,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,658 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-02-06 19:12:45,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1330 states and 2066 transitions. [2025-02-06 19:12:45,671 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1330 to 1330. [2025-02-06 19:12:45,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1330 states, 1330 states have (on average 1.5533834586466166) internal successors, (2066), 1329 states have internal predecessors, (2066), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1330 states to 1330 states and 2066 transitions. [2025-02-06 19:12:45,678 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-02-06 19:12:45,678 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,680 INFO L432 stractBuchiCegarLoop]: Abstraction has 1330 states and 2066 transitions. [2025-02-06 19:12:45,681 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:12:45,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1330 states and 2066 transitions. [2025-02-06 19:12:45,686 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 1328 [2025-02-06 19:12:45,686 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,686 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,687 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,687 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,688 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,688 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,688 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,688 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 6 times [2025-02-06 19:12:45,688 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,689 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085273593] [2025-02-06 19:12:45,689 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:12:45,689 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,692 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,694 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,696 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:12:45,696 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,696 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,699 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,699 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,700 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,703 INFO L85 PathProgramCache]: Analyzing trace with hash -282338272, now seen corresponding path program 1 times [2025-02-06 19:12:45,703 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,703 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069998595] [2025-02-06 19:12:45,703 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,703 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,707 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,708 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,708 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,708 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069998595] [2025-02-06 19:12:45,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069998595] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540801813] [2025-02-06 19:12:45,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,737 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,737 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,737 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,737 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,737 INFO L87 Difference]: Start difference. First operand 1330 states and 2066 transitions. cyclomatic complexity: 768 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,762 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,762 INFO L93 Difference]: Finished difference Result 2626 states and 4034 transitions. [2025-02-06 19:12:45,762 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2626 states and 4034 transitions. [2025-02-06 19:12:45,780 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 2624 [2025-02-06 19:12:45,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2626 states to 2626 states and 4034 transitions. [2025-02-06 19:12:45,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2626 [2025-02-06 19:12:45,797 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2626 [2025-02-06 19:12:45,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2626 states and 4034 transitions. [2025-02-06 19:12:45,801 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-02-06 19:12:45,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2626 states and 4034 transitions. [2025-02-06 19:12:45,850 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2626 to 2626. [2025-02-06 19:12:45,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2626 states, 2626 states have (on average 1.5361766945925361) internal successors, (4034), 2625 states have internal predecessors, (4034), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2626 states to 2626 states and 4034 transitions. [2025-02-06 19:12:45,861 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-02-06 19:12:45,862 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:45,863 INFO L432 stractBuchiCegarLoop]: Abstraction has 2626 states and 4034 transitions. [2025-02-06 19:12:45,863 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:12:45,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2626 states and 4034 transitions. [2025-02-06 19:12:45,874 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 2624 [2025-02-06 19:12:45,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:45,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:45,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:45,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:45,876 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:45,876 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume 0 != main_~p7~0#1;main_~lk7~0#1 := 1;" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:45,876 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,876 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 7 times [2025-02-06 19:12:45,876 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1324418876] [2025-02-06 19:12:45,877 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:12:45,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,882 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,883 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,883 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,883 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:45,884 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:45,886 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:45,886 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,887 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:45,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:45,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:45,890 INFO L85 PathProgramCache]: Analyzing trace with hash 962426209, now seen corresponding path program 1 times [2025-02-06 19:12:45,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:45,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926437636] [2025-02-06 19:12:45,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:45,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:45,893 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:45,894 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:45,895 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:45,895 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:45,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:45,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:45,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [926437636] [2025-02-06 19:12:45,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [926437636] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:45,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:45,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:45,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1934263228] [2025-02-06 19:12:45,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:45,911 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:45,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:45,911 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:45,911 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:45,911 INFO L87 Difference]: Start difference. First operand 2626 states and 4034 transitions. cyclomatic complexity: 1472 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:45,937 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:45,937 INFO L93 Difference]: Finished difference Result 5186 states and 7874 transitions. [2025-02-06 19:12:45,937 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5186 states and 7874 transitions. [2025-02-06 19:12:45,964 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 5184 [2025-02-06 19:12:45,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5186 states to 5186 states and 7874 transitions. [2025-02-06 19:12:45,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5186 [2025-02-06 19:12:45,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5186 [2025-02-06 19:12:45,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5186 states and 7874 transitions. [2025-02-06 19:12:45,997 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:45,997 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-02-06 19:12:45,999 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5186 states and 7874 transitions. [2025-02-06 19:12:46,074 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5186 to 5186. [2025-02-06 19:12:46,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5186 states, 5186 states have (on average 1.5183185499421519) internal successors, (7874), 5185 states have internal predecessors, (7874), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:46,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5186 states to 5186 states and 7874 transitions. [2025-02-06 19:12:46,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-02-06 19:12:46,094 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:46,095 INFO L432 stractBuchiCegarLoop]: Abstraction has 5186 states and 7874 transitions. [2025-02-06 19:12:46,096 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:12:46,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5186 states and 7874 transitions. [2025-02-06 19:12:46,115 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 5184 [2025-02-06 19:12:46,115 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:46,115 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:46,116 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:46,116 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:46,116 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:46,116 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:46,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:46,117 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 8 times [2025-02-06 19:12:46,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:46,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724811054] [2025-02-06 19:12:46,117 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:12:46,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:46,120 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:46,122 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:46,122 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:12:46,122 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:46,122 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:46,123 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:46,124 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:46,124 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:46,124 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:46,125 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:46,125 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:46,125 INFO L85 PathProgramCache]: Analyzing trace with hash -1075630080, now seen corresponding path program 1 times [2025-02-06 19:12:46,125 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:46,125 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884263129] [2025-02-06 19:12:46,125 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:46,125 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:46,131 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:46,133 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:46,134 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:46,134 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:46,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:46,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:46,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884263129] [2025-02-06 19:12:46,150 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884263129] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:46,150 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:46,150 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:46,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [396389437] [2025-02-06 19:12:46,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:46,151 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:46,151 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:46,151 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:46,151 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:46,153 INFO L87 Difference]: Start difference. First operand 5186 states and 7874 transitions. cyclomatic complexity: 2816 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:46,187 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:46,188 INFO L93 Difference]: Finished difference Result 10242 states and 15362 transitions. [2025-02-06 19:12:46,188 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10242 states and 15362 transitions. [2025-02-06 19:12:46,261 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 10240 [2025-02-06 19:12:46,296 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10242 states to 10242 states and 15362 transitions. [2025-02-06 19:12:46,296 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10242 [2025-02-06 19:12:46,304 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10242 [2025-02-06 19:12:46,305 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10242 states and 15362 transitions. [2025-02-06 19:12:46,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:46,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-02-06 19:12:46,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10242 states and 15362 transitions. [2025-02-06 19:12:46,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10242 to 10242. [2025-02-06 19:12:46,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10242 states, 10242 states have (on average 1.4999023628197619) internal successors, (15362), 10241 states have internal predecessors, (15362), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:46,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10242 states to 10242 states and 15362 transitions. [2025-02-06 19:12:46,526 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-02-06 19:12:46,526 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:46,529 INFO L432 stractBuchiCegarLoop]: Abstraction has 10242 states and 15362 transitions. [2025-02-06 19:12:46,530 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:12:46,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10242 states and 15362 transitions. [2025-02-06 19:12:46,601 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 10240 [2025-02-06 19:12:46,623 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:46,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:46,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:46,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:46,624 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:46,624 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:46,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:46,625 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 9 times [2025-02-06 19:12:46,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:46,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797777455] [2025-02-06 19:12:46,625 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:12:46,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:46,630 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:46,631 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:46,631 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:12:46,631 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:46,631 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:46,633 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:46,634 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:46,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:46,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:46,636 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:46,639 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:46,639 INFO L85 PathProgramCache]: Analyzing trace with hash -864279167, now seen corresponding path program 1 times [2025-02-06 19:12:46,639 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:46,639 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1266625494] [2025-02-06 19:12:46,639 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:46,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:46,642 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:46,647 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:46,647 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:46,647 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:46,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:46,676 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:46,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1266625494] [2025-02-06 19:12:46,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1266625494] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:46,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:46,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:46,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [858876915] [2025-02-06 19:12:46,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:46,677 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:46,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:46,677 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:46,677 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:46,677 INFO L87 Difference]: Start difference. First operand 10242 states and 15362 transitions. cyclomatic complexity: 5376 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:46,741 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:46,741 INFO L93 Difference]: Finished difference Result 20226 states and 29954 transitions. [2025-02-06 19:12:46,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20226 states and 29954 transitions. [2025-02-06 19:12:46,828 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 20224 [2025-02-06 19:12:46,889 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20226 states to 20226 states and 29954 transitions. [2025-02-06 19:12:46,890 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20226 [2025-02-06 19:12:46,904 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20226 [2025-02-06 19:12:46,904 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20226 states and 29954 transitions. [2025-02-06 19:12:46,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:46,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-02-06 19:12:46,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20226 states and 29954 transitions. [2025-02-06 19:12:47,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20226 to 20226. [2025-02-06 19:12:47,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20226 states, 20226 states have (on average 1.4809650944329082) internal successors, (29954), 20225 states have internal predecessors, (29954), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:47,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20226 states to 20226 states and 29954 transitions. [2025-02-06 19:12:47,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-02-06 19:12:47,236 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:47,237 INFO L432 stractBuchiCegarLoop]: Abstraction has 20226 states and 29954 transitions. [2025-02-06 19:12:47,237 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:12:47,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20226 states and 29954 transitions. [2025-02-06 19:12:47,287 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 20224 [2025-02-06 19:12:47,287 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:47,287 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:47,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:47,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:47,288 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:47,288 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:47,288 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:47,288 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 10 times [2025-02-06 19:12:47,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:47,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092199317] [2025-02-06 19:12:47,288 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:12:47,288 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:47,290 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 19:12:47,291 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:47,291 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:12:47,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:47,291 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:47,292 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:47,293 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:47,293 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:47,293 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:47,294 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:47,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:47,294 INFO L85 PathProgramCache]: Analyzing trace with hash -1273103392, now seen corresponding path program 1 times [2025-02-06 19:12:47,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:47,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398232988] [2025-02-06 19:12:47,295 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:47,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:47,297 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:47,360 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:47,360 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:47,360 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:47,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:47,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:47,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398232988] [2025-02-06 19:12:47,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398232988] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:47,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:47,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:47,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [696362521] [2025-02-06 19:12:47,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:47,374 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:47,374 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:47,374 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:47,374 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:47,374 INFO L87 Difference]: Start difference. First operand 20226 states and 29954 transitions. cyclomatic complexity: 10240 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:47,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:47,445 INFO L93 Difference]: Finished difference Result 39938 states and 58370 transitions. [2025-02-06 19:12:47,445 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39938 states and 58370 transitions. [2025-02-06 19:12:47,703 INFO L131 ngComponentsAnalysis]: Automaton has 1024 accepting balls. 39936 [2025-02-06 19:12:47,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39938 states to 39938 states and 58370 transitions. [2025-02-06 19:12:47,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 39938 [2025-02-06 19:12:47,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 39938 [2025-02-06 19:12:47,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39938 states and 58370 transitions. [2025-02-06 19:12:47,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:47,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-02-06 19:12:47,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39938 states and 58370 transitions. [2025-02-06 19:12:48,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39938 to 39938. [2025-02-06 19:12:48,367 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39938 states, 39938 states have (on average 1.4615153487906254) internal successors, (58370), 39937 states have internal predecessors, (58370), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:48,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39938 states to 39938 states and 58370 transitions. [2025-02-06 19:12:48,441 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-02-06 19:12:48,441 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:48,443 INFO L432 stractBuchiCegarLoop]: Abstraction has 39938 states and 58370 transitions. [2025-02-06 19:12:48,443 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:12:48,443 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39938 states and 58370 transitions. [2025-02-06 19:12:48,537 INFO L131 ngComponentsAnalysis]: Automaton has 1024 accepting balls. 39936 [2025-02-06 19:12:48,538 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:48,538 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:48,538 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:48,538 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:48,539 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:48,539 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:48,539 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:48,539 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 11 times [2025-02-06 19:12:48,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:48,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [721666831] [2025-02-06 19:12:48,539 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 19:12:48,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:48,542 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:48,543 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:48,543 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:12:48,543 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:48,543 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:48,544 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:48,545 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:48,545 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:48,545 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:48,546 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:48,546 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:48,546 INFO L85 PathProgramCache]: Analyzing trace with hash -2117575263, now seen corresponding path program 1 times [2025-02-06 19:12:48,546 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:48,546 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354654033] [2025-02-06 19:12:48,547 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:48,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:48,549 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:48,550 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:48,550 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:48,551 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:48,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:48,561 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:48,562 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354654033] [2025-02-06 19:12:48,562 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354654033] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:48,562 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:48,562 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:48,562 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [301708918] [2025-02-06 19:12:48,562 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:48,562 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:48,562 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:48,562 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:48,563 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:48,563 INFO L87 Difference]: Start difference. First operand 39938 states and 58370 transitions. cyclomatic complexity: 19456 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:48,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:48,833 INFO L93 Difference]: Finished difference Result 78850 states and 113666 transitions. [2025-02-06 19:12:48,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 78850 states and 113666 transitions. [2025-02-06 19:12:49,204 INFO L131 ngComponentsAnalysis]: Automaton has 2048 accepting balls. 78848 [2025-02-06 19:12:49,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 78850 states to 78850 states and 113666 transitions. [2025-02-06 19:12:49,444 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 78850 [2025-02-06 19:12:49,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 78850 [2025-02-06 19:12:49,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78850 states and 113666 transitions. [2025-02-06 19:12:49,521 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:49,522 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-02-06 19:12:49,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78850 states and 113666 transitions. [2025-02-06 19:12:50,270 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78850 to 78850. [2025-02-06 19:12:50,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78850 states, 78850 states have (on average 1.4415472415979709) internal successors, (113666), 78849 states have internal predecessors, (113666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:50,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78850 states to 78850 states and 113666 transitions. [2025-02-06 19:12:50,529 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-02-06 19:12:50,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:50,530 INFO L432 stractBuchiCegarLoop]: Abstraction has 78850 states and 113666 transitions. [2025-02-06 19:12:50,530 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:12:50,530 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78850 states and 113666 transitions. [2025-02-06 19:12:50,950 INFO L131 ngComponentsAnalysis]: Automaton has 2048 accepting balls. 78848 [2025-02-06 19:12:50,950 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:50,950 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:50,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:50,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:50,951 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:50,951 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:50,952 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:50,952 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 12 times [2025-02-06 19:12:50,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:50,952 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2017950547] [2025-02-06 19:12:50,952 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 19:12:50,952 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:50,954 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:50,955 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:50,955 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 19:12:50,955 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:50,955 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:50,956 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:50,956 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:50,956 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:50,956 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:50,958 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:50,958 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:50,958 INFO L85 PathProgramCache]: Analyzing trace with hash 1180319680, now seen corresponding path program 1 times [2025-02-06 19:12:50,958 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:50,958 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1631567992] [2025-02-06 19:12:50,958 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:50,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:50,961 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:50,962 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:50,962 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:50,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:50,974 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:50,974 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:50,974 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1631567992] [2025-02-06 19:12:50,974 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1631567992] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:50,974 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:50,974 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:50,974 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951877097] [2025-02-06 19:12:50,974 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:50,975 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:50,975 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:50,975 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:50,975 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:50,975 INFO L87 Difference]: Start difference. First operand 78850 states and 113666 transitions. cyclomatic complexity: 36864 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:51,241 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:51,241 INFO L93 Difference]: Finished difference Result 155650 states and 221186 transitions. [2025-02-06 19:12:51,241 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 155650 states and 221186 transitions. [2025-02-06 19:12:52,086 INFO L131 ngComponentsAnalysis]: Automaton has 4096 accepting balls. 155648 [2025-02-06 19:12:52,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 155650 states to 155650 states and 221186 transitions. [2025-02-06 19:12:52,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 155650 [2025-02-06 19:12:52,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 155650 [2025-02-06 19:12:52,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155650 states and 221186 transitions. [2025-02-06 19:12:52,748 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:52,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-02-06 19:12:52,785 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155650 states and 221186 transitions. [2025-02-06 19:12:54,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155650 to 155650. [2025-02-06 19:12:54,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 155650 states, 155650 states have (on average 1.4210472213299068) internal successors, (221186), 155649 states have internal predecessors, (221186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:54,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 155650 states to 155650 states and 221186 transitions. [2025-02-06 19:12:54,647 INFO L240 hiAutomatonCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-02-06 19:12:54,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:12:54,648 INFO L432 stractBuchiCegarLoop]: Abstraction has 155650 states and 221186 transitions. [2025-02-06 19:12:54,648 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:12:54,648 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 155650 states and 221186 transitions. [2025-02-06 19:12:55,096 INFO L131 ngComponentsAnalysis]: Automaton has 4096 accepting balls. 155648 [2025-02-06 19:12:55,096 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:12:55,096 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:12:55,098 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:12:55,098 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:12:55,098 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:12:55,099 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:12:55,099 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:55,099 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 13 times [2025-02-06 19:12:55,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:55,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2035412863] [2025-02-06 19:12:55,099 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 19:12:55,099 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:55,102 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:55,103 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:55,103 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:55,103 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:55,103 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:12:55,104 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:12:55,104 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:12:55,104 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:55,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:12:55,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:12:55,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:12:55,106 INFO L85 PathProgramCache]: Analyzing trace with hash -1761337919, now seen corresponding path program 1 times [2025-02-06 19:12:55,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:12:55,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2143404349] [2025-02-06 19:12:55,106 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:12:55,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:12:55,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:12:55,110 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:12:55,110 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:12:55,110 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:12:55,122 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:12:55,122 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:12:55,122 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2143404349] [2025-02-06 19:12:55,122 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2143404349] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:12:55,122 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:12:55,122 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:12:55,122 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1880881948] [2025-02-06 19:12:55,122 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:12:55,123 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:12:55,123 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:12:55,123 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:12:55,123 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:12:55,123 INFO L87 Difference]: Start difference. First operand 155650 states and 221186 transitions. cyclomatic complexity: 69632 Second operand has 3 states, 3 states have (on average 10.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:12:55,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:12:55,913 INFO L93 Difference]: Finished difference Result 307202 states and 430082 transitions. [2025-02-06 19:12:55,913 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 307202 states and 430082 transitions. [2025-02-06 19:12:57,483 INFO L131 ngComponentsAnalysis]: Automaton has 8192 accepting balls. 307200 [2025-02-06 19:12:58,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 307202 states to 307202 states and 430082 transitions. [2025-02-06 19:12:58,037 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 307202 [2025-02-06 19:12:58,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 307202 [2025-02-06 19:12:58,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 307202 states and 430082 transitions. [2025-02-06 19:12:58,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:12:58,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-02-06 19:12:58,540 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307202 states and 430082 transitions. [2025-02-06 19:13:00,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307202 to 307202. [2025-02-06 19:13:01,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307202 states, 307202 states have (on average 1.3999973958502874) internal successors, (430082), 307201 states have internal predecessors, (430082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:13:02,123 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307202 states to 307202 states and 430082 transitions. [2025-02-06 19:13:02,123 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-02-06 19:13:02,124 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:13:02,124 INFO L432 stractBuchiCegarLoop]: Abstraction has 307202 states and 430082 transitions. [2025-02-06 19:13:02,124 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 19:13:02,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307202 states and 430082 transitions. [2025-02-06 19:13:02,731 INFO L131 ngComponentsAnalysis]: Automaton has 8192 accepting balls. 307200 [2025-02-06 19:13:02,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:13:02,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:13:02,735 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:13:02,735 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:13:02,735 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:13:02,735 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:13:02,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:13:02,735 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 14 times [2025-02-06 19:13:02,735 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:13:02,735 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [243248678] [2025-02-06 19:13:02,735 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:13:02,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:13:02,737 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:02,738 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:02,738 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:13:02,738 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:02,738 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:13:02,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:02,739 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:02,739 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:02,739 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:02,740 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:13:02,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:13:02,740 INFO L85 PathProgramCache]: Analyzing trace with hash 2023095200, now seen corresponding path program 1 times [2025-02-06 19:13:02,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:13:02,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815330508] [2025-02-06 19:13:02,740 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:13:02,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:13:02,742 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:13:02,743 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:13:02,743 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:02,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:13:02,752 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:13:02,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:13:02,753 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815330508] [2025-02-06 19:13:02,753 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815330508] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:13:02,753 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:13:02,753 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:13:02,753 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917830068] [2025-02-06 19:13:02,753 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:13:02,753 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:13:02,753 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:13:02,754 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:13:02,754 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:13:02,754 INFO L87 Difference]: Start difference. First operand 307202 states and 430082 transitions. cyclomatic complexity: 131072 Second operand has 3 states, 2 states have (on average 15.0) internal successors, (30), 3 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:13:04,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:13:04,852 INFO L93 Difference]: Finished difference Result 606210 states and 835586 transitions. [2025-02-06 19:13:04,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 606210 states and 835586 transitions. [2025-02-06 19:13:07,460 INFO L131 ngComponentsAnalysis]: Automaton has 16384 accepting balls. 606208 [2025-02-06 19:13:08,875 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 606210 states to 606210 states and 835586 transitions. [2025-02-06 19:13:08,875 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 606210 [2025-02-06 19:13:09,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 606210 [2025-02-06 19:13:09,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 606210 states and 835586 transitions. [2025-02-06 19:13:09,528 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:13:09,529 INFO L218 hiAutomatonCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-02-06 19:13:09,660 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 606210 states and 835586 transitions. [2025-02-06 19:13:14,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 606210 to 606210. [2025-02-06 19:13:15,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 606210 states, 606210 states have (on average 1.3783771300374457) internal successors, (835586), 606209 states have internal predecessors, (835586), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:13:16,528 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 606210 states to 606210 states and 835586 transitions. [2025-02-06 19:13:16,528 INFO L240 hiAutomatonCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-02-06 19:13:16,529 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:13:16,529 INFO L432 stractBuchiCegarLoop]: Abstraction has 606210 states and 835586 transitions. [2025-02-06 19:13:16,529 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 19:13:16,529 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 606210 states and 835586 transitions. [2025-02-06 19:13:18,353 INFO L131 ngComponentsAnalysis]: Automaton has 16384 accepting balls. 606208 [2025-02-06 19:13:18,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:13:18,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:13:18,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 19:13:18,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:13:18,360 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_~cond~0#1;" [2025-02-06 19:13:18,360 INFO L754 eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet18#1;main_~cond~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" [2025-02-06 19:13:18,361 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:13:18,361 INFO L85 PathProgramCache]: Analyzing trace with hash 5440, now seen corresponding path program 15 times [2025-02-06 19:13:18,361 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:13:18,361 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391148325] [2025-02-06 19:13:18,361 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:13:18,361 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:13:18,362 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:18,363 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:18,363 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:13:18,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,363 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:13:18,364 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:18,364 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:18,365 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:18,365 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,365 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:13:18,366 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:13:18,366 INFO L85 PathProgramCache]: Analyzing trace with hash -764320287, now seen corresponding path program 1 times [2025-02-06 19:13:18,366 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:13:18,366 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755899507] [2025-02-06 19:13:18,366 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:13:18,366 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:13:18,368 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:13:18,369 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:13:18,369 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:18,369 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,369 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:13:18,370 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-02-06 19:13:18,371 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-02-06 19:13:18,371 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:18,371 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,375 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:13:18,376 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:13:18,376 INFO L85 PathProgramCache]: Analyzing trace with hash 271057632, now seen corresponding path program 1 times [2025-02-06 19:13:18,376 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:13:18,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [675003613] [2025-02-06 19:13:18,376 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:13:18,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:13:18,379 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-02-06 19:13:18,380 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-02-06 19:13:18,380 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:18,380 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,380 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:13:18,381 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-02-06 19:13:18,382 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-02-06 19:13:18,382 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:18,382 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:18,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:13:19,208 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:19,209 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:19,209 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:19,209 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:19,209 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:13:19,213 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 19:13:19,214 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 19:13:19,214 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:13:19,214 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:13:19,244 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:13:19 BoogieIcfgContainer [2025-02-06 19:13:19,244 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:13:19,245 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:13:19,245 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:13:19,245 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:13:19,247 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:44" (3/4) ... [2025-02-06 19:13:19,248 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:13:19,282 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:13:19,282 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:13:19,284 INFO L158 Benchmark]: Toolchain (without parser) took 34984.46ms. Allocated memory was 142.6MB in the beginning and 13.4GB in the end (delta: 13.3GB). Free memory was 108.2MB in the beginning and 8.7GB in the end (delta: -8.6GB). Peak memory consumption was 4.7GB. Max. memory is 16.1GB. [2025-02-06 19:13:19,285 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 167.8MB. Free memory is still 93.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:13:19,285 INFO L158 Benchmark]: CACSL2BoogieTranslator took 183.19ms. Allocated memory is still 142.6MB. Free memory was 108.2MB in the beginning and 96.5MB in the end (delta: 11.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:13:19,285 INFO L158 Benchmark]: Boogie Procedure Inliner took 26.68ms. Allocated memory is still 142.6MB. Free memory was 96.3MB in the beginning and 95.1MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:13:19,285 INFO L158 Benchmark]: Boogie Preprocessor took 20.75ms. Allocated memory is still 142.6MB. Free memory was 95.1MB in the beginning and 93.8MB in the end (delta: 1.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:13:19,286 INFO L158 Benchmark]: IcfgBuilder took 305.86ms. Allocated memory is still 142.6MB. Free memory was 93.5MB in the beginning and 77.3MB in the end (delta: 16.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-02-06 19:13:19,286 INFO L158 Benchmark]: BuchiAutomizer took 34405.35ms. Allocated memory was 142.6MB in the beginning and 13.4GB in the end (delta: 13.3GB). Free memory was 77.1MB in the beginning and 8.7GB in the end (delta: -8.7GB). Peak memory consumption was 4.6GB. Max. memory is 16.1GB. [2025-02-06 19:13:19,286 INFO L158 Benchmark]: Witness Printer took 37.17ms. Allocated memory is still 13.4GB. Free memory was 8.7GB in the beginning and 8.7GB in the end (delta: 4.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:13:19,288 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 167.8MB. Free memory is still 93.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 183.19ms. Allocated memory is still 142.6MB. Free memory was 108.2MB in the beginning and 96.5MB in the end (delta: 11.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 26.68ms. Allocated memory is still 142.6MB. Free memory was 96.3MB in the beginning and 95.1MB in the end (delta: 1.2MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 20.75ms. Allocated memory is still 142.6MB. Free memory was 95.1MB in the beginning and 93.8MB in the end (delta: 1.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * IcfgBuilder took 305.86ms. Allocated memory is still 142.6MB. Free memory was 93.5MB in the beginning and 77.3MB in the end (delta: 16.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * BuchiAutomizer took 34405.35ms. Allocated memory was 142.6MB in the beginning and 13.4GB in the end (delta: 13.3GB). Free memory was 77.1MB in the beginning and 8.7GB in the end (delta: -8.7GB). Peak memory consumption was 4.6GB. Max. memory is 16.1GB. * Witness Printer took 37.17ms. Allocated memory is still 13.4GB. Free memory was 8.7GB in the beginning and 8.7GB in the end (delta: 4.0MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 14 terminating modules (14 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.14 modules have a trivial ranking function, the largest among these consists of 3 locations. The remainder module has 606210 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 34.3s and 15 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.1s. Büchi inclusion checks took 28.9s. Highest rank in rank-based complementation 0. Minimization of det autom 14. Minimization of nondet autom 0. Automata minimization 14.9s AutomataMinimizationTime, 14 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations. Non-live state removal took 8.9s Buchi closure took 0.7s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 800 SdHoareTripleChecker+Valid, 0.1s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 800 mSDsluCounter, 2507 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 968 mSDsCounter, 28 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 72 IncrementalHoareTripleChecker+Invalid, 100 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 28 mSolverCounterUnsat, 1539 mSDtfsCounter, 72 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI14 SFLT0 conc0 concLT0 SILN0 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 53]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L8] int p1 = __VERIFIER_nondet_int(); [L9] int lk1; [L11] int p2 = __VERIFIER_nondet_int(); [L12] int lk2; [L14] int p3 = __VERIFIER_nondet_int(); [L15] int lk3; [L17] int p4 = __VERIFIER_nondet_int(); [L18] int lk4; [L20] int p5 = __VERIFIER_nondet_int(); [L21] int lk5; [L23] int p6 = __VERIFIER_nondet_int(); [L24] int lk6; [L26] int p7 = __VERIFIER_nondet_int(); [L27] int lk7; [L29] int p8 = __VERIFIER_nondet_int(); [L30] int lk8; [L32] int p9 = __VERIFIER_nondet_int(); [L33] int lk9; [L35] int p10 = __VERIFIER_nondet_int(); [L36] int lk10; [L38] int p11 = __VERIFIER_nondet_int(); [L39] int lk11; [L41] int p12 = __VERIFIER_nondet_int(); [L42] int lk12; [L44] int p13 = __VERIFIER_nondet_int(); [L45] int lk13; [L47] int p14 = __VERIFIER_nondet_int(); [L48] int lk14; [L51] int cond; Loop: [L53] COND TRUE 1 [L54] cond = __VERIFIER_nondet_int() [L55] COND FALSE !(cond == 0) [L58] lk1 = 0 [L60] lk2 = 0 [L62] lk3 = 0 [L64] lk4 = 0 [L66] lk5 = 0 [L68] lk6 = 0 [L70] lk7 = 0 [L72] lk8 = 0 [L74] lk9 = 0 [L76] lk10 = 0 [L78] lk11 = 0 [L80] lk12 = 0 [L82] lk13 = 0 [L84] lk14 = 0 [L88] COND FALSE !(p1 != 0) [L92] COND FALSE !(p2 != 0) [L96] COND FALSE !(p3 != 0) [L100] COND FALSE !(p4 != 0) [L104] COND FALSE !(p5 != 0) [L108] COND FALSE !(p6 != 0) [L112] COND FALSE !(p7 != 0) [L116] COND FALSE !(p8 != 0) [L120] COND FALSE !(p9 != 0) [L124] COND FALSE !(p10 != 0) [L128] COND FALSE !(p11 != 0) [L132] COND FALSE !(p12 != 0) [L136] COND FALSE !(p13 != 0) [L140] COND FALSE !(p14 != 0) [L146] COND FALSE !(p1 != 0) [L151] COND FALSE !(p2 != 0) [L156] COND FALSE !(p3 != 0) [L161] COND FALSE !(p4 != 0) [L166] COND FALSE !(p5 != 0) [L171] COND FALSE !(p6 != 0) [L176] COND FALSE !(p7 != 0) [L181] COND FALSE !(p8 != 0) [L186] COND FALSE !(p9 != 0) [L191] COND FALSE !(p10 != 0) [L196] COND FALSE !(p11 != 0) [L201] COND FALSE !(p12 != 0) [L206] COND FALSE !(p13 != 0) [L211] COND FALSE !(p14 != 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 53]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L8] int p1 = __VERIFIER_nondet_int(); [L9] int lk1; [L11] int p2 = __VERIFIER_nondet_int(); [L12] int lk2; [L14] int p3 = __VERIFIER_nondet_int(); [L15] int lk3; [L17] int p4 = __VERIFIER_nondet_int(); [L18] int lk4; [L20] int p5 = __VERIFIER_nondet_int(); [L21] int lk5; [L23] int p6 = __VERIFIER_nondet_int(); [L24] int lk6; [L26] int p7 = __VERIFIER_nondet_int(); [L27] int lk7; [L29] int p8 = __VERIFIER_nondet_int(); [L30] int lk8; [L32] int p9 = __VERIFIER_nondet_int(); [L33] int lk9; [L35] int p10 = __VERIFIER_nondet_int(); [L36] int lk10; [L38] int p11 = __VERIFIER_nondet_int(); [L39] int lk11; [L41] int p12 = __VERIFIER_nondet_int(); [L42] int lk12; [L44] int p13 = __VERIFIER_nondet_int(); [L45] int lk13; [L47] int p14 = __VERIFIER_nondet_int(); [L48] int lk14; [L51] int cond; Loop: [L53] COND TRUE 1 [L54] cond = __VERIFIER_nondet_int() [L55] COND FALSE !(cond == 0) [L58] lk1 = 0 [L60] lk2 = 0 [L62] lk3 = 0 [L64] lk4 = 0 [L66] lk5 = 0 [L68] lk6 = 0 [L70] lk7 = 0 [L72] lk8 = 0 [L74] lk9 = 0 [L76] lk10 = 0 [L78] lk11 = 0 [L80] lk12 = 0 [L82] lk13 = 0 [L84] lk14 = 0 [L88] COND FALSE !(p1 != 0) [L92] COND FALSE !(p2 != 0) [L96] COND FALSE !(p3 != 0) [L100] COND FALSE !(p4 != 0) [L104] COND FALSE !(p5 != 0) [L108] COND FALSE !(p6 != 0) [L112] COND FALSE !(p7 != 0) [L116] COND FALSE !(p8 != 0) [L120] COND FALSE !(p9 != 0) [L124] COND FALSE !(p10 != 0) [L128] COND FALSE !(p11 != 0) [L132] COND FALSE !(p12 != 0) [L136] COND FALSE !(p13 != 0) [L140] COND FALSE !(p14 != 0) [L146] COND FALSE !(p1 != 0) [L151] COND FALSE !(p2 != 0) [L156] COND FALSE !(p3 != 0) [L161] COND FALSE !(p4 != 0) [L166] COND FALSE !(p5 != 0) [L171] COND FALSE !(p6 != 0) [L176] COND FALSE !(p7 != 0) [L181] COND FALSE !(p8 != 0) [L186] COND FALSE !(p9 != 0) [L191] COND FALSE !(p10 != 0) [L196] COND FALSE !(p11 != 0) [L201] COND FALSE !(p12 != 0) [L206] COND FALSE !(p13 != 0) [L211] COND FALSE !(p14 != 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:13:19,304 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)