./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/locks/test_locks_15-2.c --full-output --architecture 32bit


--------------------------------------------------------------------------------


Checking for termination
Using default analysis
Version c00e63dc
Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/locks/test_locks_15-2.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) )

 --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ad13fcacd201ae20f6800b42387b8ec1153fb1bf63cee7a12ec23f4a302be7c7
--- Real Ultimate output ---
This is Ultimate 0.3.0-?-c00e63d-m
[2025-02-06 19:12:44,793 INFO  L188        SettingsManager]: Resetting all preferences to default values...
[2025-02-06 19:12:44,856 INFO  L114        SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf
[2025-02-06 19:12:44,861 WARN  L101        SettingsManager]: Preference file contains the following unknown settings:
[2025-02-06 19:12:44,862 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.core.Log level for class
[2025-02-06 19:12:44,862 WARN  L103        SettingsManager]:   * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG
[2025-02-06 19:12:44,886 INFO  L130        SettingsManager]: Preferences different from defaults after loading the file:
[2025-02-06 19:12:44,887 INFO  L151        SettingsManager]: Preferences of UltimateCore differ from their defaults:
[2025-02-06 19:12:44,888 INFO  L153        SettingsManager]:  * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR;
[2025-02-06 19:12:44,888 INFO  L151        SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults:
[2025-02-06 19:12:44,889 INFO  L153        SettingsManager]:  * Use memory slicer=true
[2025-02-06 19:12:44,889 INFO  L151        SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults:
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Create parallel compositions if possible=false
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Use SBE=true
[2025-02-06 19:12:44,890 INFO  L151        SettingsManager]: Preferences of BuchiAutomizer differ from their defaults:
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * NCSB implementation=INTSET_LAZY3
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Use old map elimination=false
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Use external solver (rank synthesis)=false
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Use only trivial implications for array writes=true
[2025-02-06 19:12:44,890 INFO  L153        SettingsManager]:  * Rank analysis=LINEAR_WITH_GUESSES
[2025-02-06 19:12:44,891 INFO  L151        SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults:
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Pointer base address is valid at dereference=ASSUME
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * sizeof long=4
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Overapproximate operations on floating types=true
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * sizeof POINTER=4
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Check division by zero=IGNORE
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Pointer to allocated memory at dereference=ASSUME
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * If two pointers are subtracted or compared they have the same base address=ASSUME
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Check array bounds for arrays that are off heap=ASSUME
[2025-02-06 19:12:44,891 INFO  L153        SettingsManager]:  * Check unreachability of reach_error function=false
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * sizeof long double=12
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Check if freed pointer was valid=false
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Assume nondeterminstic values are in range=false
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Use constant arrays=true
[2025-02-06 19:12:44,892 INFO  L151        SettingsManager]: Preferences of IcfgBuilder differ from their defaults:
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Size of a code block=SequenceOfStatements
[2025-02-06 19:12:44,892 INFO  L151        SettingsManager]: Preferences of TraceAbstraction differ from their defaults:
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * Trace refinement strategy=CAMEL
[2025-02-06 19:12:44,892 INFO  L151        SettingsManager]: Preferences of IcfgTransformer differ from their defaults:
[2025-02-06 19:12:44,892 INFO  L153        SettingsManager]:  * TransformationType=MODULO_NEIGHBOR
Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) )


Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit
Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ad13fcacd201ae20f6800b42387b8ec1153fb1bf63cee7a12ec23f4a302be7c7
[2025-02-06 19:12:45,187 INFO  L75    nceAwareModelManager]: Repository-Root is: /tmp
[2025-02-06 19:12:45,198 INFO  L261   ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized
[2025-02-06 19:12:45,200 INFO  L217   ainManager$Toolchain]: [Toolchain 1]: Toolchain selected.
[2025-02-06 19:12:45,202 INFO  L270        PluginConnector]: Initializing CDTParser...
[2025-02-06 19:12:45,203 INFO  L274        PluginConnector]: CDTParser initialized
[2025-02-06 19:12:45,205 INFO  L431   ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/locks/test_locks_15-2.c
[2025-02-06 19:12:46,522 INFO  L533              CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a9fd351f4/f86e02a1302b4cc5bf1b78b4644abb1b/FLAGea773b2c2
[2025-02-06 19:12:46,776 INFO  L384              CDTParser]: Found 1 translation units.
[2025-02-06 19:12:46,777 INFO  L180              CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/locks/test_locks_15-2.c
[2025-02-06 19:12:46,814 INFO  L427              CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a9fd351f4/f86e02a1302b4cc5bf1b78b4644abb1b/FLAGea773b2c2
[2025-02-06 19:12:46,829 INFO  L435              CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a9fd351f4/f86e02a1302b4cc5bf1b78b4644abb1b
[2025-02-06 19:12:46,831 INFO  L299   ainManager$Toolchain]: ####################### [Toolchain 1] #######################
[2025-02-06 19:12:46,832 INFO  L133        ToolchainWalker]: Walking toolchain with 6 elements.
[2025-02-06 19:12:46,833 INFO  L112        PluginConnector]: ------------------------CACSL2BoogieTranslator----------------------------
[2025-02-06 19:12:46,833 INFO  L270        PluginConnector]: Initializing CACSL2BoogieTranslator...
[2025-02-06 19:12:46,837 INFO  L274        PluginConnector]: CACSL2BoogieTranslator initialized
[2025-02-06 19:12:46,837 INFO  L184        PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:12:46" (1/1) ...
[2025-02-06 19:12:46,838 INFO  L204        PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@206286ba and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:46, skipping insertion in model container
[2025-02-06 19:12:46,838 INFO  L184        PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:12:46" (1/1) ...
[2025-02-06 19:12:46,858 INFO  L175         MainTranslator]: Built tables and reachable declarations
[2025-02-06 19:12:46,996 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-02-06 19:12:47,006 INFO  L200         MainTranslator]: Completed pre-run
[2025-02-06 19:12:47,032 INFO  L210          PostProcessor]: Analyzing one entry point: main
[2025-02-06 19:12:47,046 INFO  L204         MainTranslator]: Completed translation
[2025-02-06 19:12:47,047 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47 WrapperNode
[2025-02-06 19:12:47,047 INFO  L131        PluginConnector]: ------------------------ END CACSL2BoogieTranslator----------------------------
[2025-02-06 19:12:47,048 INFO  L112        PluginConnector]: ------------------------Boogie Procedure Inliner----------------------------
[2025-02-06 19:12:47,048 INFO  L270        PluginConnector]: Initializing Boogie Procedure Inliner...
[2025-02-06 19:12:47,048 INFO  L274        PluginConnector]: Boogie Procedure Inliner initialized
[2025-02-06 19:12:47,053 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,058 INFO  L184        PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,081 INFO  L138                Inliner]: procedures = 12, calls = 8, calls flagged for inlining = 3, calls inlined = 3, statements flattened = 190
[2025-02-06 19:12:47,082 INFO  L131        PluginConnector]: ------------------------ END Boogie Procedure Inliner----------------------------
[2025-02-06 19:12:47,083 INFO  L112        PluginConnector]: ------------------------Boogie Preprocessor----------------------------
[2025-02-06 19:12:47,085 INFO  L270        PluginConnector]: Initializing Boogie Preprocessor...
[2025-02-06 19:12:47,085 INFO  L274        PluginConnector]: Boogie Preprocessor initialized
[2025-02-06 19:12:47,091 INFO  L184        PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,091 INFO  L184        PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,093 INFO  L184        PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,111 INFO  L175           MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0].
[2025-02-06 19:12:47,111 INFO  L184        PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,111 INFO  L184        PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,118 INFO  L184        PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,119 INFO  L184        PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,120 INFO  L184        PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,121 INFO  L184        PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,126 INFO  L131        PluginConnector]: ------------------------ END Boogie Preprocessor----------------------------
[2025-02-06 19:12:47,127 INFO  L112        PluginConnector]: ------------------------IcfgBuilder----------------------------
[2025-02-06 19:12:47,127 INFO  L270        PluginConnector]: Initializing IcfgBuilder...
[2025-02-06 19:12:47,127 INFO  L274        PluginConnector]: IcfgBuilder initialized
[2025-02-06 19:12:47,128 INFO  L184        PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (1/1) ...
[2025-02-06 19:12:47,132 INFO  L173          SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000
[2025-02-06 19:12:47,145 INFO  L189       MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3
[2025-02-06 19:12:47,161 INFO  L229       MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null)
[2025-02-06 19:12:47,165 INFO  L327       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process
[2025-02-06 19:12:47,189 INFO  L130     BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit
[2025-02-06 19:12:47,189 INFO  L130     BoogieDeclarations]: Found specification of procedure ULTIMATE.start
[2025-02-06 19:12:47,189 INFO  L138     BoogieDeclarations]: Found implementation of procedure ULTIMATE.start
[2025-02-06 19:12:47,189 INFO  L130     BoogieDeclarations]: Found specification of procedure write~init~int#0
[2025-02-06 19:12:47,253 INFO  L257             CfgBuilder]: Building ICFG
[2025-02-06 19:12:47,255 INFO  L287             CfgBuilder]: Building CFG for each procedure with an implementation
[2025-02-06 19:12:47,583 INFO  L?                        ?]: Removed 34 outVars from TransFormulas that were not future-live.
[2025-02-06 19:12:47,583 INFO  L308             CfgBuilder]: Performing block encoding
[2025-02-06 19:12:47,596 INFO  L332             CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start)
[2025-02-06 19:12:47,596 INFO  L337             CfgBuilder]: Removed 0 assume(true) statements.
[2025-02-06 19:12:47,597 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:47 BoogieIcfgContainer
[2025-02-06 19:12:47,597 INFO  L131        PluginConnector]: ------------------------ END IcfgBuilder----------------------------
[2025-02-06 19:12:47,599 INFO  L112        PluginConnector]: ------------------------BuchiAutomizer----------------------------
[2025-02-06 19:12:47,600 INFO  L270        PluginConnector]: Initializing BuchiAutomizer...
[2025-02-06 19:12:47,604 INFO  L274        PluginConnector]: BuchiAutomizer initialized
[2025-02-06 19:12:47,605 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:12:47,605 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:12:46" (1/3) ...
[2025-02-06 19:12:47,606 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16fe7bc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:12:47, skipping insertion in model container
[2025-02-06 19:12:47,606 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:12:47,607 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:12:47" (2/3) ...
[2025-02-06 19:12:47,607 INFO  L204        PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@16fe7bc6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:12:47, skipping insertion in model container
[2025-02-06 19:12:47,607 INFO  L99          BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis
[2025-02-06 19:12:47,607 INFO  L184        PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:47" (3/3) ...
[2025-02-06 19:12:47,608 INFO  L363   chiAutomizerObserver]: Analyzing ICFG test_locks_15-2.c
[2025-02-06 19:12:47,662 INFO  L306   stractBuchiCegarLoop]: Interprodecural is true
[2025-02-06 19:12:47,663 INFO  L307   stractBuchiCegarLoop]: Hoare is None
[2025-02-06 19:12:47,663 INFO  L308   stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates
[2025-02-06 19:12:47,663 INFO  L309   stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE
[2025-02-06 19:12:47,663 INFO  L310   stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION
[2025-02-06 19:12:47,664 INFO  L311   stractBuchiCegarLoop]: Difference is false
[2025-02-06 19:12:47,664 INFO  L312   stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA
[2025-02-06 19:12:47,664 INFO  L316   stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ========
[2025-02-06 19:12:47,670 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 55 states, 54 states have (on average 1.8703703703703705) internal successors, (101), 54 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:47,689 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 47
[2025-02-06 19:12:47,689 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:47,690 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:47,694 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:47,694 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:47,695 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 1 ============
[2025-02-06 19:12:47,695 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand  has 55 states, 54 states have (on average 1.8703703703703705) internal successors, (101), 54 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:47,698 INFO  L131   ngComponentsAnalysis]: Automaton has 1 accepting balls. 47
[2025-02-06 19:12:47,698 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:47,698 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:47,699 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:47,700 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:47,705 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:47,706 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume 0 != main_~p1~0#1;main_~lk1~0#1 := 1;" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:47,709 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:47,709 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 1 times
[2025-02-06 19:12:47,715 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:47,715 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012897521]
[2025-02-06 19:12:47,715 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:47,716 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:47,767 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:47,780 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:47,781 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:47,781 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:47,781 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:47,785 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:47,790 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:47,791 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:47,791 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:47,810 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:47,814 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:47,814 INFO  L85        PathProgramCache]: Analyzing trace with hash 1587644894, now seen corresponding path program 1 times
[2025-02-06 19:12:47,814 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:47,814 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903928588]
[2025-02-06 19:12:47,814 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:47,815 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:47,828 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:47,845 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:47,846 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:47,846 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:47,967 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:47,969 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:47,969 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [903928588]
[2025-02-06 19:12:47,970 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [903928588] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:47,970 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:47,970 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:47,971 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1638114290]
[2025-02-06 19:12:47,971 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:47,974 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:47,975 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:47,995 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:47,995 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:47,997 INFO  L87              Difference]: Start difference. First operand  has 55 states, 54 states have (on average 1.8703703703703705) internal successors, (101), 54 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,042 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,043 INFO  L93              Difference]: Finished difference Result 103 states and 189 transitions.
[2025-02-06 19:12:48,044 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 103 states and 189 transitions.
[2025-02-06 19:12:48,048 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 93
[2025-02-06 19:12:48,054 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 103 states to 95 states and 153 transitions.
[2025-02-06 19:12:48,055 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 95
[2025-02-06 19:12:48,056 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 95
[2025-02-06 19:12:48,056 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 95 states and 153 transitions.
[2025-02-06 19:12:48,057 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,057 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 95 states and 153 transitions.
[2025-02-06 19:12:48,069 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 95 states and 153 transitions.
[2025-02-06 19:12:48,085 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 95 to 95.
[2025-02-06 19:12:48,086 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 95 states, 95 states have (on average 1.6105263157894736) internal successors, (153), 94 states have internal predecessors, (153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,087 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 95 states to 95 states and 153 transitions.
[2025-02-06 19:12:48,089 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 95 states and 153 transitions.
[2025-02-06 19:12:48,094 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:48,097 INFO  L432   stractBuchiCegarLoop]: Abstraction has 95 states and 153 transitions.
[2025-02-06 19:12:48,099 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 2 ============
[2025-02-06 19:12:48,100 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 95 states and 153 transitions.
[2025-02-06 19:12:48,102 INFO  L131   ngComponentsAnalysis]: Automaton has 2 accepting balls. 93
[2025-02-06 19:12:48,102 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:48,102 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:48,102 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:48,103 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:48,103 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:48,103 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume 0 != main_~p2~0#1;main_~lk2~0#1 := 1;" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:48,103 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,104 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 2 times
[2025-02-06 19:12:48,104 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,104 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227418783]
[2025-02-06 19:12:48,104 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:12:48,104 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,109 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,112 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,112 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:12:48,112 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,114 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:48,116 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,117 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,118 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,118 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,122 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:48,122 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,122 INFO  L85        PathProgramCache]: Analyzing trace with hash 1598961021, now seen corresponding path program 1 times
[2025-02-06 19:12:48,122 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,123 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105493307]
[2025-02-06 19:12:48,123 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:48,123 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,134 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:48,144 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:48,144 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,144 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:48,192 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:48,193 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:48,193 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1105493307]
[2025-02-06 19:12:48,193 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1105493307] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:48,193 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:48,193 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:48,193 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [102513287]
[2025-02-06 19:12:48,193 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:48,194 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:48,195 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:48,195 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:48,196 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:48,196 INFO  L87              Difference]: Start difference. First operand 95 states and 153 transitions. cyclomatic complexity: 60 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,221 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,221 INFO  L93              Difference]: Finished difference Result 186 states and 298 transitions.
[2025-02-06 19:12:48,221 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 186 states and 298 transitions.
[2025-02-06 19:12:48,224 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 184
[2025-02-06 19:12:48,226 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 186 states to 186 states and 298 transitions.
[2025-02-06 19:12:48,226 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 186
[2025-02-06 19:12:48,228 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 186
[2025-02-06 19:12:48,228 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 186 states and 298 transitions.
[2025-02-06 19:12:48,229 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,231 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 186 states and 298 transitions.
[2025-02-06 19:12:48,231 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 186 states and 298 transitions.
[2025-02-06 19:12:48,240 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186.
[2025-02-06 19:12:48,241 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 186 states, 186 states have (on average 1.6021505376344085) internal successors, (298), 185 states have internal predecessors, (298), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,242 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 298 transitions.
[2025-02-06 19:12:48,244 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 186 states and 298 transitions.
[2025-02-06 19:12:48,245 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:48,246 INFO  L432   stractBuchiCegarLoop]: Abstraction has 186 states and 298 transitions.
[2025-02-06 19:12:48,246 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 3 ============
[2025-02-06 19:12:48,246 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 186 states and 298 transitions.
[2025-02-06 19:12:48,248 INFO  L131   ngComponentsAnalysis]: Automaton has 4 accepting balls. 184
[2025-02-06 19:12:48,248 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:48,249 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:48,249 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:48,249 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:48,249 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:48,250 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume 0 != main_~p3~0#1;main_~lk3~0#1 := 1;" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:48,250 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,250 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 3 times
[2025-02-06 19:12:48,250 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,251 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1531031828]
[2025-02-06 19:12:48,251 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-02-06 19:12:48,251 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,255 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,260 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,260 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-02-06 19:12:48,260 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,260 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:48,262 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,268 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,268 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,268 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,270 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:48,272 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,272 INFO  L85        PathProgramCache]: Analyzing trace with hash -2002904578, now seen corresponding path program 1 times
[2025-02-06 19:12:48,272 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,272 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527431181]
[2025-02-06 19:12:48,272 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:48,273 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,285 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:48,295 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:48,295 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,295 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:48,339 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:48,340 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:48,340 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527431181]
[2025-02-06 19:12:48,340 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527431181] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:48,340 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:48,340 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:48,340 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461244733]
[2025-02-06 19:12:48,340 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:48,341 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:48,341 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:48,341 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:48,341 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:48,341 INFO  L87              Difference]: Start difference. First operand 186 states and 298 transitions. cyclomatic complexity: 116 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,379 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,379 INFO  L93              Difference]: Finished difference Result 366 states and 582 transitions.
[2025-02-06 19:12:48,379 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 366 states and 582 transitions.
[2025-02-06 19:12:48,383 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 364
[2025-02-06 19:12:48,387 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 366 states to 366 states and 582 transitions.
[2025-02-06 19:12:48,387 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 366
[2025-02-06 19:12:48,388 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 366
[2025-02-06 19:12:48,388 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 366 states and 582 transitions.
[2025-02-06 19:12:48,389 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,390 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 366 states and 582 transitions.
[2025-02-06 19:12:48,390 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 366 states and 582 transitions.
[2025-02-06 19:12:48,413 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 366 to 366.
[2025-02-06 19:12:48,414 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 366 states, 366 states have (on average 1.5901639344262295) internal successors, (582), 365 states have internal predecessors, (582), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,417 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 366 states to 366 states and 582 transitions.
[2025-02-06 19:12:48,417 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 366 states and 582 transitions.
[2025-02-06 19:12:48,418 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:48,418 INFO  L432   stractBuchiCegarLoop]: Abstraction has 366 states and 582 transitions.
[2025-02-06 19:12:48,418 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 4 ============
[2025-02-06 19:12:48,419 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 366 states and 582 transitions.
[2025-02-06 19:12:48,421 INFO  L131   ngComponentsAnalysis]: Automaton has 8 accepting balls. 364
[2025-02-06 19:12:48,421 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:48,421 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:48,421 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:48,422 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:48,422 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:48,422 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume 0 != main_~p4~0#1;main_~lk4~0#1 := 1;" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:48,422 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,423 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 4 times
[2025-02-06 19:12:48,423 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,423 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371387311]
[2025-02-06 19:12:48,423 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-02-06 19:12:48,423 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,427 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes.
[2025-02-06 19:12:48,429 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,429 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-02-06 19:12:48,430 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,430 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:48,431 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,432 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,433 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,433 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,435 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:48,435 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,435 INFO  L85        PathProgramCache]: Analyzing trace with hash 2037326173, now seen corresponding path program 1 times
[2025-02-06 19:12:48,435 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,436 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1783325469]
[2025-02-06 19:12:48,436 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:48,436 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,441 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:48,449 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:48,449 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,449 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:48,488 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:48,488 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:48,488 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1783325469]
[2025-02-06 19:12:48,488 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1783325469] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:48,489 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:48,489 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:48,489 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067437884]
[2025-02-06 19:12:48,489 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:48,489 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:48,489 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:48,490 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:48,490 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:48,490 INFO  L87              Difference]: Start difference. First operand 366 states and 582 transitions. cyclomatic complexity: 224 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,511 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,511 INFO  L93              Difference]: Finished difference Result 722 states and 1138 transitions.
[2025-02-06 19:12:48,512 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 722 states and 1138 transitions.
[2025-02-06 19:12:48,518 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 720
[2025-02-06 19:12:48,524 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 722 states to 722 states and 1138 transitions.
[2025-02-06 19:12:48,525 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 722
[2025-02-06 19:12:48,527 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 722
[2025-02-06 19:12:48,527 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 722 states and 1138 transitions.
[2025-02-06 19:12:48,532 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,535 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 722 states and 1138 transitions.
[2025-02-06 19:12:48,536 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 722 states and 1138 transitions.
[2025-02-06 19:12:48,551 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 722 to 722.
[2025-02-06 19:12:48,552 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 722 states, 722 states have (on average 1.5761772853185596) internal successors, (1138), 721 states have internal predecessors, (1138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,555 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 722 states to 722 states and 1138 transitions.
[2025-02-06 19:12:48,556 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 722 states and 1138 transitions.
[2025-02-06 19:12:48,556 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:48,557 INFO  L432   stractBuchiCegarLoop]: Abstraction has 722 states and 1138 transitions.
[2025-02-06 19:12:48,557 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 5 ============
[2025-02-06 19:12:48,557 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 722 states and 1138 transitions.
[2025-02-06 19:12:48,562 INFO  L131   ngComponentsAnalysis]: Automaton has 16 accepting balls. 720
[2025-02-06 19:12:48,562 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:48,562 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:48,562 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:48,562 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:48,563 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:48,563 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume 0 != main_~p5~0#1;main_~lk5~0#1 := 1;" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:48,563 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,563 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 5 times
[2025-02-06 19:12:48,564 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,564 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1014650407]
[2025-02-06 19:12:48,564 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-02-06 19:12:48,564 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,572 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,574 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,574 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:12:48,574 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,574 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:48,578 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,580 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,584 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,585 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,587 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:48,587 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,588 INFO  L85        PathProgramCache]: Analyzing trace with hash -1296027106, now seen corresponding path program 1 times
[2025-02-06 19:12:48,588 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,588 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [856408026]
[2025-02-06 19:12:48,588 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:48,588 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,599 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:48,602 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:48,602 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,602 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:48,634 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:48,634 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:48,634 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [856408026]
[2025-02-06 19:12:48,635 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [856408026] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:48,635 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:48,635 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:48,635 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1006865329]
[2025-02-06 19:12:48,635 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:48,635 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:48,636 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:48,636 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:48,636 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:48,636 INFO  L87              Difference]: Start difference. First operand 722 states and 1138 transitions. cyclomatic complexity: 432 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,669 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,669 INFO  L93              Difference]: Finished difference Result 1426 states and 2226 transitions.
[2025-02-06 19:12:48,669 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 1426 states and 2226 transitions.
[2025-02-06 19:12:48,684 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 1424
[2025-02-06 19:12:48,694 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 1426 states to 1426 states and 2226 transitions.
[2025-02-06 19:12:48,695 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 1426
[2025-02-06 19:12:48,697 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 1426
[2025-02-06 19:12:48,697 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 1426 states and 2226 transitions.
[2025-02-06 19:12:48,700 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,700 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 1426 states and 2226 transitions.
[2025-02-06 19:12:48,701 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 1426 states and 2226 transitions.
[2025-02-06 19:12:48,731 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 1426 to 1426.
[2025-02-06 19:12:48,736 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 1426 states, 1426 states have (on average 1.5610098176718092) internal successors, (2226), 1425 states have internal predecessors, (2226), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,744 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 1426 states to 1426 states and 2226 transitions.
[2025-02-06 19:12:48,745 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 1426 states and 2226 transitions.
[2025-02-06 19:12:48,745 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:48,746 INFO  L432   stractBuchiCegarLoop]: Abstraction has 1426 states and 2226 transitions.
[2025-02-06 19:12:48,747 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 6 ============
[2025-02-06 19:12:48,747 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 1426 states and 2226 transitions.
[2025-02-06 19:12:48,756 INFO  L131   ngComponentsAnalysis]: Automaton has 32 accepting balls. 1424
[2025-02-06 19:12:48,757 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:48,757 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:48,758 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:48,758 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:48,758 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:48,758 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume 0 != main_~p6~0#1;main_~lk6~0#1 := 1;" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:48,759 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,759 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 6 times
[2025-02-06 19:12:48,759 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,759 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [553720814]
[2025-02-06 19:12:48,759 INFO  L95    rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE
[2025-02-06 19:12:48,760 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,764 INFO  L108    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,766 INFO  L111    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,767 INFO  L114    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s)
[2025-02-06 19:12:48,767 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,767 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:48,768 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:48,769 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:48,769 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,769 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:48,772 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:48,774 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:48,774 INFO  L85        PathProgramCache]: Analyzing trace with hash -1265007299, now seen corresponding path program 1 times
[2025-02-06 19:12:48,775 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:48,775 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1248642845]
[2025-02-06 19:12:48,775 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:48,775 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:48,782 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:48,785 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:48,785 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:48,785 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:48,812 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:48,813 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:48,813 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1248642845]
[2025-02-06 19:12:48,813 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1248642845] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:48,813 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:48,813 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:48,813 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [841392807]
[2025-02-06 19:12:48,813 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:48,814 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:48,814 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:48,816 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:48,817 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:48,817 INFO  L87              Difference]: Start difference. First operand 1426 states and 2226 transitions. cyclomatic complexity: 832 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:48,850 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:48,851 INFO  L93              Difference]: Finished difference Result 2818 states and 4354 transitions.
[2025-02-06 19:12:48,851 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 2818 states and 4354 transitions.
[2025-02-06 19:12:48,878 INFO  L131   ngComponentsAnalysis]: Automaton has 64 accepting balls. 2816
[2025-02-06 19:12:48,898 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 2818 states to 2818 states and 4354 transitions.
[2025-02-06 19:12:48,898 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 2818
[2025-02-06 19:12:48,901 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 2818
[2025-02-06 19:12:48,902 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 2818 states and 4354 transitions.
[2025-02-06 19:12:48,907 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:48,907 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 2818 states and 4354 transitions.
[2025-02-06 19:12:48,910 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 2818 states and 4354 transitions.
[2025-02-06 19:12:48,996 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 2818 to 2818.
[2025-02-06 19:12:49,001 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 2818 states, 2818 states have (on average 1.5450674237047552) internal successors, (4354), 2817 states have internal predecessors, (4354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:49,012 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 2818 states to 2818 states and 4354 transitions.
[2025-02-06 19:12:49,013 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 2818 states and 4354 transitions.
[2025-02-06 19:12:49,013 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:49,014 INFO  L432   stractBuchiCegarLoop]: Abstraction has 2818 states and 4354 transitions.
[2025-02-06 19:12:49,014 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 7 ============
[2025-02-06 19:12:49,014 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 2818 states and 4354 transitions.
[2025-02-06 19:12:49,032 INFO  L131   ngComponentsAnalysis]: Automaton has 64 accepting balls. 2816
[2025-02-06 19:12:49,033 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:49,033 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:49,035 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:49,035 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:49,035 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:49,035 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume 0 != main_~p8~0#1;main_~lk8~0#1 := 1;" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:49,036 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:49,036 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 7 times
[2025-02-06 19:12:49,036 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:49,036 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1853373490]
[2025-02-06 19:12:49,036 INFO  L95    rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY
[2025-02-06 19:12:49,036 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:49,042 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,044 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,044 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,044 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:49,045 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:49,050 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,051 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,052 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,052 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:49,053 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:49,056 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:49,056 INFO  L85        PathProgramCache]: Analyzing trace with hash 952750654, now seen corresponding path program 1 times
[2025-02-06 19:12:49,056 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:49,056 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27722666]
[2025-02-06 19:12:49,056 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:49,056 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:49,061 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:49,064 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:49,065 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,065 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:49,093 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:49,093 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:49,093 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27722666]
[2025-02-06 19:12:49,094 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27722666] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:49,094 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:49,094 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:49,094 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1569551741]
[2025-02-06 19:12:49,094 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:49,094 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:49,094 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:49,095 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:49,095 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:49,095 INFO  L87              Difference]: Start difference. First operand 2818 states and 4354 transitions. cyclomatic complexity: 1600 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:49,129 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:49,130 INFO  L93              Difference]: Finished difference Result 5570 states and 8514 transitions.
[2025-02-06 19:12:49,130 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 5570 states and 8514 transitions.
[2025-02-06 19:12:49,170 INFO  L131   ngComponentsAnalysis]: Automaton has 128 accepting balls. 5568
[2025-02-06 19:12:49,200 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 5570 states to 5570 states and 8514 transitions.
[2025-02-06 19:12:49,200 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 5570
[2025-02-06 19:12:49,205 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 5570
[2025-02-06 19:12:49,205 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 5570 states and 8514 transitions.
[2025-02-06 19:12:49,215 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:49,215 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 5570 states and 8514 transitions.
[2025-02-06 19:12:49,219 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 5570 states and 8514 transitions.
[2025-02-06 19:12:49,322 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 5570 to 5570.
[2025-02-06 19:12:49,332 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 5570 states, 5570 states have (on average 1.5285457809694794) internal successors, (8514), 5569 states have internal predecessors, (8514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:49,352 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 5570 states to 5570 states and 8514 transitions.
[2025-02-06 19:12:49,352 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 5570 states and 8514 transitions.
[2025-02-06 19:12:49,352 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:49,354 INFO  L432   stractBuchiCegarLoop]: Abstraction has 5570 states and 8514 transitions.
[2025-02-06 19:12:49,354 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 8 ============
[2025-02-06 19:12:49,354 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 5570 states and 8514 transitions.
[2025-02-06 19:12:49,384 INFO  L131   ngComponentsAnalysis]: Automaton has 128 accepting balls. 5568
[2025-02-06 19:12:49,384 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:49,384 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:49,385 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:49,385 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:49,385 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:49,385 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume 0 != main_~p9~0#1;main_~lk9~0#1 := 1;" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:49,386 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:49,386 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 8 times
[2025-02-06 19:12:49,386 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:49,386 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481823044]
[2025-02-06 19:12:49,386 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:12:49,386 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:49,389 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,391 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,391 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:12:49,391 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:49,391 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:49,392 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,395 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,397 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,397 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:49,399 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:49,402 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:49,402 INFO  L85        PathProgramCache]: Analyzing trace with hash -2097452161, now seen corresponding path program 1 times
[2025-02-06 19:12:49,403 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:49,403 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126971568]
[2025-02-06 19:12:49,403 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:49,403 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:49,407 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:49,411 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:49,412 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,412 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:49,439 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:49,440 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:49,440 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126971568]
[2025-02-06 19:12:49,440 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126971568] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:49,441 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:49,441 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:49,441 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1755024796]
[2025-02-06 19:12:49,441 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:49,441 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:49,441 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:49,442 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:49,444 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:49,445 INFO  L87              Difference]: Start difference. First operand 5570 states and 8514 transitions. cyclomatic complexity: 3072 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:49,492 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:49,493 INFO  L93              Difference]: Finished difference Result 11010 states and 16642 transitions.
[2025-02-06 19:12:49,493 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 11010 states and 16642 transitions.
[2025-02-06 19:12:49,556 INFO  L131   ngComponentsAnalysis]: Automaton has 256 accepting balls. 11008
[2025-02-06 19:12:49,679 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 11010 states to 11010 states and 16642 transitions.
[2025-02-06 19:12:49,680 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 11010
[2025-02-06 19:12:49,689 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 11010
[2025-02-06 19:12:49,690 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 11010 states and 16642 transitions.
[2025-02-06 19:12:49,708 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:49,708 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 11010 states and 16642 transitions.
[2025-02-06 19:12:49,717 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 11010 states and 16642 transitions.
[2025-02-06 19:12:49,871 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 11010 to 11010.
[2025-02-06 19:12:49,893 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 11010 states, 11010 states have (on average 1.5115349682107175) internal successors, (16642), 11009 states have internal predecessors, (16642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:49,933 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 11010 states to 11010 states and 16642 transitions.
[2025-02-06 19:12:49,934 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 11010 states and 16642 transitions.
[2025-02-06 19:12:49,934 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:49,937 INFO  L432   stractBuchiCegarLoop]: Abstraction has 11010 states and 16642 transitions.
[2025-02-06 19:12:49,937 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 9 ============
[2025-02-06 19:12:49,937 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 11010 states and 16642 transitions.
[2025-02-06 19:12:49,984 INFO  L131   ngComponentsAnalysis]: Automaton has 256 accepting balls. 11008
[2025-02-06 19:12:49,985 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:49,985 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:49,985 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:49,985 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:49,985 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:49,986 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume 0 != main_~p10~0#1;main_~lk10~0#1 := 1;" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:49,986 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:49,986 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 9 times
[2025-02-06 19:12:49,986 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:49,986 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658964998]
[2025-02-06 19:12:49,987 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2
[2025-02-06 19:12:49,987 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:49,992 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,993 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,993 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s)
[2025-02-06 19:12:49,993 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:49,993 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:49,995 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:49,996 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:49,996 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:49,996 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:50,000 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:50,002 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:50,002 INFO  L85        PathProgramCache]: Analyzing trace with hash 159458846, now seen corresponding path program 1 times
[2025-02-06 19:12:50,002 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:50,002 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105628469]
[2025-02-06 19:12:50,002 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:50,002 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:50,011 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:50,013 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:50,015 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:50,016 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:50,037 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:50,038 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:50,038 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [105628469]
[2025-02-06 19:12:50,038 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [105628469] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:50,038 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:50,038 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:50,038 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1776353992]
[2025-02-06 19:12:50,038 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:50,038 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:50,039 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:50,039 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:50,039 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:50,039 INFO  L87              Difference]: Start difference. First operand 11010 states and 16642 transitions. cyclomatic complexity: 5888 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:50,111 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:50,111 INFO  L93              Difference]: Finished difference Result 21762 states and 32514 transitions.
[2025-02-06 19:12:50,111 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 21762 states and 32514 transitions.
[2025-02-06 19:12:50,235 INFO  L131   ngComponentsAnalysis]: Automaton has 512 accepting balls. 21760
[2025-02-06 19:12:50,339 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 21762 states to 21762 states and 32514 transitions.
[2025-02-06 19:12:50,340 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 21762
[2025-02-06 19:12:50,364 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 21762
[2025-02-06 19:12:50,364 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 21762 states and 32514 transitions.
[2025-02-06 19:12:50,396 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:50,396 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 21762 states and 32514 transitions.
[2025-02-06 19:12:50,502 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 21762 states and 32514 transitions.
[2025-02-06 19:12:50,743 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 21762 to 21762.
[2025-02-06 19:12:50,793 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 21762 states, 21762 states have (on average 1.4940722360077199) internal successors, (32514), 21761 states have internal predecessors, (32514), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:50,874 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 21762 states to 21762 states and 32514 transitions.
[2025-02-06 19:12:50,874 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 21762 states and 32514 transitions.
[2025-02-06 19:12:50,875 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:50,875 INFO  L432   stractBuchiCegarLoop]: Abstraction has 21762 states and 32514 transitions.
[2025-02-06 19:12:50,875 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 10 ============
[2025-02-06 19:12:50,876 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 21762 states and 32514 transitions.
[2025-02-06 19:12:50,946 INFO  L131   ngComponentsAnalysis]: Automaton has 512 accepting balls. 21760
[2025-02-06 19:12:50,946 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:50,946 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:50,947 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:50,947 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:50,947 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:50,947 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume 0 != main_~p11~0#1;main_~lk11~0#1 := 1;" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:50,947 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:50,948 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 10 times
[2025-02-06 19:12:50,948 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:50,948 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [518421824]
[2025-02-06 19:12:50,948 INFO  L95    rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST
[2025-02-06 19:12:50,948 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:50,950 INFO  L108    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes.
[2025-02-06 19:12:50,951 INFO  L111    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:50,952 INFO  L114    AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s)
[2025-02-06 19:12:50,952 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:50,952 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:50,954 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:50,955 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:50,956 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:50,956 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:50,959 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:50,960 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:50,960 INFO  L85        PathProgramCache]: Analyzing trace with hash 370809759, now seen corresponding path program 1 times
[2025-02-06 19:12:50,961 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:50,961 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [401503829]
[2025-02-06 19:12:50,961 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:50,961 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:50,965 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:50,966 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:50,966 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:50,967 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:50,983 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:50,983 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:50,983 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [401503829]
[2025-02-06 19:12:50,983 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [401503829] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:50,984 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:50,984 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:50,984 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473931435]
[2025-02-06 19:12:50,984 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:50,984 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:50,984 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:50,985 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:50,985 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:50,986 INFO  L87              Difference]: Start difference. First operand 21762 states and 32514 transitions. cyclomatic complexity: 11264 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:51,185 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:51,185 INFO  L93              Difference]: Finished difference Result 43010 states and 63490 transitions.
[2025-02-06 19:12:51,185 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 43010 states and 63490 transitions.
[2025-02-06 19:12:51,493 INFO  L131   ngComponentsAnalysis]: Automaton has 1024 accepting balls. 43008
[2025-02-06 19:12:51,716 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 43010 states to 43010 states and 63490 transitions.
[2025-02-06 19:12:51,717 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 43010
[2025-02-06 19:12:51,743 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 43010
[2025-02-06 19:12:51,744 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 43010 states and 63490 transitions.
[2025-02-06 19:12:51,778 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:51,778 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 43010 states and 63490 transitions.
[2025-02-06 19:12:51,811 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 43010 states and 63490 transitions.
[2025-02-06 19:12:52,282 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 43010 to 43010.
[2025-02-06 19:12:52,344 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 43010 states, 43010 states have (on average 1.4761683329458266) internal successors, (63490), 43009 states have internal predecessors, (63490), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:52,483 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 43010 states to 43010 states and 63490 transitions.
[2025-02-06 19:12:52,483 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 43010 states and 63490 transitions.
[2025-02-06 19:12:52,484 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:52,485 INFO  L432   stractBuchiCegarLoop]: Abstraction has 43010 states and 63490 transitions.
[2025-02-06 19:12:52,486 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 11 ============
[2025-02-06 19:12:52,486 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 43010 states and 63490 transitions.
[2025-02-06 19:12:52,765 INFO  L131   ngComponentsAnalysis]: Automaton has 1024 accepting balls. 43008
[2025-02-06 19:12:52,765 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:52,765 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:52,766 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:52,766 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:52,766 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:52,766 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume 0 != main_~p12~0#1;main_~lk12~0#1 := 1;" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:52,767 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:52,767 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 11 times
[2025-02-06 19:12:52,767 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:52,767 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105453886]
[2025-02-06 19:12:52,767 INFO  L95    rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1
[2025-02-06 19:12:52,767 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:52,771 INFO  L108    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:52,772 INFO  L111    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:52,773 INFO  L114    AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:12:52,773 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:52,773 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:52,775 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:52,777 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:52,777 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:52,778 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:52,779 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:52,781 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:52,783 INFO  L85        PathProgramCache]: Analyzing trace with hash -38014466, now seen corresponding path program 1 times
[2025-02-06 19:12:52,783 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:52,783 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1634481546]
[2025-02-06 19:12:52,783 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:52,783 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:52,787 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:52,792 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:52,795 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:52,795 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:52,819 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:52,820 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:52,820 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1634481546]
[2025-02-06 19:12:52,820 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1634481546] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:52,820 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:52,820 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:52,820 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1711731668]
[2025-02-06 19:12:52,821 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:52,821 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:52,821 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:52,821 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:52,821 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:52,822 INFO  L87              Difference]: Start difference. First operand 43010 states and 63490 transitions. cyclomatic complexity: 21504 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:53,134 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:53,134 INFO  L93              Difference]: Finished difference Result 84994 states and 123906 transitions.
[2025-02-06 19:12:53,134 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 84994 states and 123906 transitions.
[2025-02-06 19:12:53,560 INFO  L131   ngComponentsAnalysis]: Automaton has 2048 accepting balls. 84992
[2025-02-06 19:12:53,952 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 84994 states to 84994 states and 123906 transitions.
[2025-02-06 19:12:53,953 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 84994
[2025-02-06 19:12:53,988 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 84994
[2025-02-06 19:12:53,988 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 84994 states and 123906 transitions.
[2025-02-06 19:12:54,079 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:54,080 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 84994 states and 123906 transitions.
[2025-02-06 19:12:54,113 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 84994 states and 123906 transitions.
[2025-02-06 19:12:54,946 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 84994 to 84994.
[2025-02-06 19:12:55,024 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 84994 states, 84994 states have (on average 1.4578205520389675) internal successors, (123906), 84993 states have internal predecessors, (123906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:55,400 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 84994 states to 84994 states and 123906 transitions.
[2025-02-06 19:12:55,401 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 84994 states and 123906 transitions.
[2025-02-06 19:12:55,403 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:55,404 INFO  L432   stractBuchiCegarLoop]: Abstraction has 84994 states and 123906 transitions.
[2025-02-06 19:12:55,404 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 12 ============
[2025-02-06 19:12:55,404 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 84994 states and 123906 transitions.
[2025-02-06 19:12:55,635 INFO  L131   ngComponentsAnalysis]: Automaton has 2048 accepting balls. 84992
[2025-02-06 19:12:55,635 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:12:55,635 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:12:55,637 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:12:55,637 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:12:55,637 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:12:55,638 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume 0 != main_~p13~0#1;main_~lk13~0#1 := 1;" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:12:55,638 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:55,638 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 12 times
[2025-02-06 19:12:55,638 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:55,638 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1189657136]
[2025-02-06 19:12:55,638 INFO  L95    rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE
[2025-02-06 19:12:55,639 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:55,642 INFO  L108    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:55,644 INFO  L111    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:55,644 INFO  L114    AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s)
[2025-02-06 19:12:55,644 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:55,645 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:12:55,647 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:12:55,648 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:12:55,648 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:55,648 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:12:55,650 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:12:55,651 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:12:55,651 INFO  L85        PathProgramCache]: Analyzing trace with hash -882486337, now seen corresponding path program 1 times
[2025-02-06 19:12:55,651 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:12:55,651 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1136490149]
[2025-02-06 19:12:55,651 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:12:55,651 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:12:55,655 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:12:55,656 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:12:55,656 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:12:55,656 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:12:55,670 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:12:55,670 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:12:55,670 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1136490149]
[2025-02-06 19:12:55,670 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1136490149] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:12:55,670 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:12:55,670 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:12:55,670 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [736215955]
[2025-02-06 19:12:55,671 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:12:55,671 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:12:55,671 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:12:55,671 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:12:55,671 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:12:55,671 INFO  L87              Difference]: Start difference. First operand 84994 states and 123906 transitions. cyclomatic complexity: 40960 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:56,184 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:12:56,184 INFO  L93              Difference]: Finished difference Result 167938 states and 241666 transitions.
[2025-02-06 19:12:56,184 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 167938 states and 241666 transitions.
[2025-02-06 19:12:56,943 INFO  L131   ngComponentsAnalysis]: Automaton has 4096 accepting balls. 167936
[2025-02-06 19:12:57,459 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 167938 states to 167938 states and 241666 transitions.
[2025-02-06 19:12:57,459 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 167938
[2025-02-06 19:12:57,528 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 167938
[2025-02-06 19:12:57,529 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 167938 states and 241666 transitions.
[2025-02-06 19:12:57,622 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:12:57,622 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 167938 states and 241666 transitions.
[2025-02-06 19:12:57,682 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 167938 states and 241666 transitions.
[2025-02-06 19:12:59,162 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 167938 to 167938.
[2025-02-06 19:12:59,282 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 167938 states, 167938 states have (on average 1.4390191618335337) internal successors, (241666), 167937 states have internal predecessors, (241666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:12:59,631 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 167938 states to 167938 states and 241666 transitions.
[2025-02-06 19:12:59,631 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 167938 states and 241666 transitions.
[2025-02-06 19:12:59,632 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:12:59,632 INFO  L432   stractBuchiCegarLoop]: Abstraction has 167938 states and 241666 transitions.
[2025-02-06 19:12:59,632 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 13 ============
[2025-02-06 19:12:59,632 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 167938 states and 241666 transitions.
[2025-02-06 19:13:00,404 INFO  L131   ngComponentsAnalysis]: Automaton has 4096 accepting balls. 167936
[2025-02-06 19:13:00,405 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:13:00,405 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:13:00,407 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:13:00,407 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:13:00,407 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:13:00,407 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume 0 != main_~p14~0#1;main_~lk14~0#1 := 1;" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:13:00,408 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:13:00,408 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 13 times
[2025-02-06 19:13:00,408 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:13:00,408 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332413506]
[2025-02-06 19:13:00,408 INFO  L95    rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY
[2025-02-06 19:13:00,408 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:13:00,411 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:00,412 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:00,412 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:00,412 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:00,412 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:13:00,413 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:00,413 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:00,414 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:00,414 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:00,415 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:13:00,415 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:13:00,415 INFO  L85        PathProgramCache]: Analyzing trace with hash -1879558690, now seen corresponding path program 1 times
[2025-02-06 19:13:00,415 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:13:00,416 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1700923860]
[2025-02-06 19:13:00,416 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:13:00,416 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:13:00,419 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:13:00,422 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:13:00,423 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:00,423 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is unsat
[2025-02-06 19:13:00,442 INFO  L134       CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked.
[2025-02-06 19:13:00,443 INFO  L136   FreeRefinementEngine]: Strategy CAMEL found an infeasible trace
[2025-02-06 19:13:00,443 INFO  L334   FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1700923860]
[2025-02-06 19:13:00,443 INFO  L158   FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1700923860] provided 1 perfect and 0 imperfect interpolant sequences
[2025-02-06 19:13:00,443 INFO  L185   FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences.
[2025-02-06 19:13:00,443 INFO  L198   FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3
[2025-02-06 19:13:00,443 INFO  L121   tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1820568495]
[2025-02-06 19:13:00,443 INFO  L85    oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton
[2025-02-06 19:13:00,444 INFO  L769   eck$LassoCheckResult]: loop already infeasible
[2025-02-06 19:13:00,444 INFO  L100   FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL
[2025-02-06 19:13:00,444 INFO  L144   InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants.
[2025-02-06 19:13:00,444 INFO  L146   InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6
[2025-02-06 19:13:00,444 INFO  L87              Difference]: Start difference. First operand 167938 states and 241666 transitions. cyclomatic complexity: 77824 Second operand  has 3 states, 3 states have (on average 10.666666666666666) internal successors, (32), 3 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:13:01,417 INFO  L144             Difference]: Subtrahend was deterministic. Have not used determinization.
[2025-02-06 19:13:01,417 INFO  L93              Difference]: Finished difference Result 331778 states and 471042 transitions.
[2025-02-06 19:13:01,417 INFO  L82        GeneralOperation]: Start removeNonLiveStates. Operand 331778 states and 471042 transitions.
[2025-02-06 19:13:03,016 INFO  L131   ngComponentsAnalysis]: Automaton has 8192 accepting balls. 331776
[2025-02-06 19:13:04,072 INFO  L88        GeneralOperation]: Finished removeNonLiveStates. Reduced from 331778 states to 331778 states and 471042 transitions.
[2025-02-06 19:13:04,073 INFO  L87         BuchiClosureNwa]: Accepting states before buchiClosure: 331778
[2025-02-06 19:13:04,160 INFO  L106        BuchiClosureNwa]: Accepting states after buchiClosure: 331778
[2025-02-06 19:13:04,161 INFO  L73         IsDeterministic]: Start isDeterministic. Operand 331778 states and 471042 transitions.
[2025-02-06 19:13:04,245 INFO  L80         IsDeterministic]: Finished isDeterministic. Operand is deterministic.
[2025-02-06 19:13:04,245 INFO  L218   hiAutomatonCegarLoop]: Abstraction has 331778 states and 471042 transitions.
[2025-02-06 19:13:04,336 INFO  L82        GeneralOperation]: Start minimizeSevpa. Operand 331778 states and 471042 transitions.
[2025-02-06 19:13:07,050 INFO  L88        GeneralOperation]: Finished minimizeSevpa. Reduced states from 331778 to 331778.
[2025-02-06 19:13:07,311 INFO  L82        GeneralOperation]: Start removeUnreachable. Operand  has 331778 states, 331778 states have (on average 1.419750556094738) internal successors, (471042), 331777 states have internal predecessors, (471042), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)
[2025-02-06 19:13:08,195 INFO  L88        GeneralOperation]: Finished removeUnreachable. Reduced from 331778 states to 331778 states and 471042 transitions.
[2025-02-06 19:13:08,195 INFO  L240   hiAutomatonCegarLoop]: Abstraction has 331778 states and 471042 transitions.
[2025-02-06 19:13:08,196 INFO  L141   InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. 
[2025-02-06 19:13:08,196 INFO  L432   stractBuchiCegarLoop]: Abstraction has 331778 states and 471042 transitions.
[2025-02-06 19:13:08,196 INFO  L338   stractBuchiCegarLoop]: ======== Iteration 14 ============
[2025-02-06 19:13:08,196 INFO  L72            BuchiIsEmpty]: Start buchiIsEmpty. Operand 331778 states and 471042 transitions.
[2025-02-06 19:13:09,712 INFO  L131   ngComponentsAnalysis]: Automaton has 8192 accepting balls. 331776
[2025-02-06 19:13:09,712 INFO  L87            BuchiIsEmpty]: Finished buchiIsEmpty Result is false
[2025-02-06 19:13:09,712 INFO  L119           BuchiIsEmpty]: Starting construction of run
[2025-02-06 19:13:09,716 INFO  L148   hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1]
[2025-02-06 19:13:09,716 INFO  L149   hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]
[2025-02-06 19:13:09,716 INFO  L752   eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);call #Ultimate.allocInit(12, 3);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet4#1, main_#t~nondet5#1, main_#t~nondet6#1, main_#t~nondet7#1, main_#t~nondet8#1, main_#t~nondet9#1, main_#t~nondet10#1, main_#t~nondet11#1, main_#t~nondet12#1, main_#t~nondet13#1, main_#t~nondet14#1, main_#t~nondet15#1, main_#t~nondet16#1, main_#t~nondet17#1, main_#t~nondet18#1, main_#t~nondet19#1, main_~p1~0#1, main_~lk1~0#1, main_~p2~0#1, main_~lk2~0#1, main_~p3~0#1, main_~lk3~0#1, main_~p4~0#1, main_~lk4~0#1, main_~p5~0#1, main_~lk5~0#1, main_~p6~0#1, main_~lk6~0#1, main_~p7~0#1, main_~lk7~0#1, main_~p8~0#1, main_~lk8~0#1, main_~p9~0#1, main_~lk9~0#1, main_~p10~0#1, main_~lk10~0#1, main_~p11~0#1, main_~lk11~0#1, main_~p12~0#1, main_~lk12~0#1, main_~p13~0#1, main_~lk13~0#1, main_~p14~0#1, main_~lk14~0#1, main_~p15~0#1, main_~lk15~0#1, main_~cond~0#1;havoc main_#t~nondet4#1;main_~p1~0#1 := main_#t~nondet4#1;havoc main_#t~nondet4#1;havoc main_~lk1~0#1;havoc main_#t~nondet5#1;main_~p2~0#1 := main_#t~nondet5#1;havoc main_#t~nondet5#1;havoc main_~lk2~0#1;havoc main_#t~nondet6#1;main_~p3~0#1 := main_#t~nondet6#1;havoc main_#t~nondet6#1;havoc main_~lk3~0#1;havoc main_#t~nondet7#1;main_~p4~0#1 := main_#t~nondet7#1;havoc main_#t~nondet7#1;havoc main_~lk4~0#1;havoc main_#t~nondet8#1;main_~p5~0#1 := main_#t~nondet8#1;havoc main_#t~nondet8#1;havoc main_~lk5~0#1;havoc main_#t~nondet9#1;main_~p6~0#1 := main_#t~nondet9#1;havoc main_#t~nondet9#1;havoc main_~lk6~0#1;havoc main_#t~nondet10#1;main_~p7~0#1 := main_#t~nondet10#1;havoc main_#t~nondet10#1;havoc main_~lk7~0#1;havoc main_#t~nondet11#1;main_~p8~0#1 := main_#t~nondet11#1;havoc main_#t~nondet11#1;havoc main_~lk8~0#1;havoc main_#t~nondet12#1;main_~p9~0#1 := main_#t~nondet12#1;havoc main_#t~nondet12#1;havoc main_~lk9~0#1;havoc main_#t~nondet13#1;main_~p10~0#1 := main_#t~nondet13#1;havoc main_#t~nondet13#1;havoc main_~lk10~0#1;havoc main_#t~nondet14#1;main_~p11~0#1 := main_#t~nondet14#1;havoc main_#t~nondet14#1;havoc main_~lk11~0#1;havoc main_#t~nondet15#1;main_~p12~0#1 := main_#t~nondet15#1;havoc main_#t~nondet15#1;havoc main_~lk12~0#1;havoc main_#t~nondet16#1;main_~p13~0#1 := main_#t~nondet16#1;havoc main_#t~nondet16#1;havoc main_~lk13~0#1;havoc main_#t~nondet17#1;main_~p14~0#1 := main_#t~nondet17#1;havoc main_#t~nondet17#1;havoc main_~lk14~0#1;havoc main_#t~nondet18#1;main_~p15~0#1 := main_#t~nondet18#1;havoc main_#t~nondet18#1;havoc main_~lk15~0#1;havoc main_~cond~0#1;" 
[2025-02-06 19:13:09,716 INFO  L754   eck$LassoCheckResult]: Loop: "assume true;havoc main_#t~nondet19#1;main_~cond~0#1 := main_#t~nondet19#1;havoc main_#t~nondet19#1;" "assume !(0 == main_~cond~0#1);main_~lk1~0#1 := 0;main_~lk2~0#1 := 0;main_~lk3~0#1 := 0;main_~lk4~0#1 := 0;main_~lk5~0#1 := 0;main_~lk6~0#1 := 0;main_~lk7~0#1 := 0;main_~lk8~0#1 := 0;main_~lk9~0#1 := 0;main_~lk10~0#1 := 0;main_~lk11~0#1 := 0;main_~lk12~0#1 := 0;main_~lk13~0#1 := 0;main_~lk14~0#1 := 0;main_~lk15~0#1 := 0;" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" "assume !(0 != main_~p1~0#1);" "assume !(0 != main_~p2~0#1);" "assume !(0 != main_~p3~0#1);" "assume !(0 != main_~p4~0#1);" "assume !(0 != main_~p5~0#1);" "assume !(0 != main_~p6~0#1);" "assume !(0 != main_~p7~0#1);" "assume !(0 != main_~p8~0#1);" "assume !(0 != main_~p9~0#1);" "assume !(0 != main_~p10~0#1);" "assume !(0 != main_~p11~0#1);" "assume !(0 != main_~p12~0#1);" "assume !(0 != main_~p13~0#1);" "assume !(0 != main_~p14~0#1);" "assume !(0 != main_~p15~0#1);" 
[2025-02-06 19:13:09,717 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:13:09,717 INFO  L85        PathProgramCache]: Analyzing trace with hash 5728, now seen corresponding path program 14 times
[2025-02-06 19:13:09,717 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:13:09,717 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471866288]
[2025-02-06 19:13:09,717 INFO  L95    rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1
[2025-02-06 19:13:09,717 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:13:09,719 INFO  L108    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:09,720 INFO  L111    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:09,720 INFO  L114    AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s)
[2025-02-06 19:13:09,720 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,720 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:13:09,721 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:09,722 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:09,722 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:09,722 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,723 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:13:09,723 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:13:09,723 INFO  L85        PathProgramCache]: Analyzing trace with hash -526248993, now seen corresponding path program 1 times
[2025-02-06 19:13:09,723 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:13:09,723 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [635955428]
[2025-02-06 19:13:09,723 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:13:09,723 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:13:09,726 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:13:09,727 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:13:09,727 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:09,727 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,728 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:13:09,729 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes.
[2025-02-06 19:13:09,730 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements.
[2025-02-06 19:13:09,730 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:09,730 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,737 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:13:09,738 INFO  L157       PredicateUnifier]: Initialized classic predicate unifier
[2025-02-06 19:13:09,738 INFO  L85        PathProgramCache]: Analyzing trace with hash 500756030, now seen corresponding path program 1 times
[2025-02-06 19:13:09,738 INFO  L118   FreeRefinementEngine]: Executing refinement strategy CAMEL
[2025-02-06 19:13:09,738 INFO  L334   FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1219075478]
[2025-02-06 19:13:09,738 INFO  L97    rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY
[2025-02-06 19:13:09,738 INFO  L127          SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms
[2025-02-06 19:13:09,742 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-02-06 19:13:09,744 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-02-06 19:13:09,744 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:09,745 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,745 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:13:09,746 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes.
[2025-02-06 19:13:09,748 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements.
[2025-02-06 19:13:09,748 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:09,748 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:09,752 INFO  L130   FreeRefinementEngine]: Strategy CAMEL found a feasible trace
[2025-02-06 19:13:10,426 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:10,428 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:10,428 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:10,428 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:10,428 INFO  L348             TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders.
[2025-02-06 19:13:10,433 INFO  L108    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes.
[2025-02-06 19:13:10,434 INFO  L111    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements.
[2025-02-06 19:13:10,434 INFO  L114    AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s)
[2025-02-06 19:13:10,434 INFO  L115    AnnotateAndAsserter]: Conjunction of SSA is sat
[2025-02-06 19:13:10,487 INFO  L201        PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:13:10 BoogieIcfgContainer
[2025-02-06 19:13:10,488 INFO  L131        PluginConnector]: ------------------------ END BuchiAutomizer----------------------------
[2025-02-06 19:13:10,489 INFO  L112        PluginConnector]: ------------------------Witness Printer----------------------------
[2025-02-06 19:13:10,489 INFO  L270        PluginConnector]: Initializing Witness Printer...
[2025-02-06 19:13:10,489 INFO  L274        PluginConnector]: Witness Printer initialized
[2025-02-06 19:13:10,490 INFO  L184        PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:12:47" (3/4) ...
[2025-02-06 19:13:10,492 INFO  L143         WitnessPrinter]: Generating witness for non-termination counterexample
[2025-02-06 19:13:10,531 INFO  L149         WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml
[2025-02-06 19:13:10,531 INFO  L131        PluginConnector]: ------------------------ END Witness Printer----------------------------
[2025-02-06 19:13:10,534 INFO  L158              Benchmark]: Toolchain (without parser) took 23700.08ms. Allocated memory was 142.6MB in the beginning and 12.4GB in the end (delta: 12.2GB). Free memory was 111.2MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 2.7GB. Max. memory is 16.1GB.
[2025-02-06 19:13:10,535 INFO  L158              Benchmark]: CDTParser took 0.34ms. Allocated memory is still 201.3MB. Free memory is still 121.4MB. There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:13:10,535 INFO  L158              Benchmark]: CACSL2BoogieTranslator took 214.27ms. Allocated memory is still 142.6MB. Free memory was 109.8MB in the beginning and 99.0MB in the end (delta: 10.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-02-06 19:13:10,535 INFO  L158              Benchmark]: Boogie Procedure Inliner took 34.73ms. Allocated memory is still 142.6MB. Free memory was 99.0MB in the beginning and 97.4MB in the end (delta: 1.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-02-06 19:13:10,536 INFO  L158              Benchmark]: Boogie Preprocessor took 42.90ms. Allocated memory is still 142.6MB. Free memory was 97.4MB in the beginning and 96.0MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:13:10,536 INFO  L158              Benchmark]: IcfgBuilder took 472.07ms. Allocated memory is still 142.6MB. Free memory was 96.0MB in the beginning and 79.3MB in the end (delta: 16.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
[2025-02-06 19:13:10,536 INFO  L158              Benchmark]: BuchiAutomizer took 22889.04ms. Allocated memory was 142.6MB in the beginning and 12.4GB in the end (delta: 12.2GB). Free memory was 79.3MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 2.7GB. Max. memory is 16.1GB.
[2025-02-06 19:13:10,537 INFO  L158              Benchmark]: Witness Printer took 42.49ms. Allocated memory is still 12.4GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 4.0MB). There was no memory consumed. Max. memory is 16.1GB.
[2025-02-06 19:13:10,538 INFO  L338   ainManager$Toolchain]: #######################  End [Toolchain 1] #######################
 --- Results ---
 * Results from de.uni_freiburg.informatik.ultimate.core:
  - StatisticsResult: Toolchain Benchmarks
    Benchmark results are:
 * CDTParser took 0.34ms. Allocated memory is still 201.3MB. Free memory is still 121.4MB. There was no memory consumed. Max. memory is 16.1GB.
 * CACSL2BoogieTranslator took 214.27ms. Allocated memory is still 142.6MB. Free memory was 109.8MB in the beginning and 99.0MB in the end (delta: 10.9MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * Boogie Procedure Inliner took 34.73ms. Allocated memory is still 142.6MB. Free memory was 99.0MB in the beginning and 97.4MB in the end (delta: 1.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * Boogie Preprocessor took 42.90ms. Allocated memory is still 142.6MB. Free memory was 97.4MB in the beginning and 96.0MB in the end (delta: 1.4MB). There was no memory consumed. Max. memory is 16.1GB.
 * IcfgBuilder took 472.07ms. Allocated memory is still 142.6MB. Free memory was 96.0MB in the beginning and 79.3MB in the end (delta: 16.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB.
 * BuchiAutomizer took 22889.04ms. Allocated memory was 142.6MB in the beginning and 12.4GB in the end (delta: 12.2GB). Free memory was 79.3MB in the beginning and 9.6GB in the end (delta: -9.5GB). Peak memory consumption was 2.7GB. Max. memory is 16.1GB.
 * Witness Printer took 42.49ms. Allocated memory is still 12.4GB. Free memory was 9.6GB in the beginning and 9.6GB in the end (delta: 4.0MB). There was no memory consumed. Max. memory is 16.1GB.
 * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction:
  - StatisticsResult: Constructed decomposition of program
    Your program was decomposed into 13 terminating modules (13 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.13 modules have a trivial ranking function, the largest among these consists of 3 locations. The remainder module has 331778 locations.
  - StatisticsResult: Timing statistics
    BüchiAutomizer plugin needed 22.8s and 14 iterations.  TraceHistogramMax:1. Analysis of lassos took 1.7s. Construction of modules took 0.1s. Büchi inclusion checks took 17.8s. Highest rank in rank-based complementation 0. Minimization of det autom 13. Minimization of nondet autom 0. Automata minimization 9.1s AutomataMinimizationTime, 13 MinimizatonAttempts, 0 StatesRemovedByMinimization, 0 NontrivialMinimizations. Non-live state removal took 5.8s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1.	Nontrivial modules had stage [0, 0, 0, 0, 0].	InterpolantCoveringCapabilityFinite: 0/0	InterpolantCoveringCapabilityBuchi: 0/0	HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 797 SdHoareTripleChecker+Valid, 0.2s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 797 mSDsluCounter, 2503 SdHoareTripleChecker+Invalid, 0.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 966 mSDsCounter, 26 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 67 IncrementalHoareTripleChecker+Invalid, 93 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 26 mSolverCounterUnsat, 1537 mSDtfsCounter, 67 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown	LassoAnalysisResults: nont1 unkn0 SFLI13 SFLT0 conc0 concLT0 SILN0 SILU0 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0	LassoNonterminationAnalysisSatUnbounded: 0	LassoNonterminationAnalysisUnsat: 0	LassoNonterminationAnalysisUnknown: 0	LassoNonterminationAnalysisTime: 0.0s	InitialAbstractionConstructionTime: 0.0s
  - TerminationAnalysisResult: Nontermination possible
    Buchi Automizer proved that your program is nonterminating for some inputs
  - LassoShapedNonTerminationArgument [Line: 56]: Nontermination argument in form of an infinite program execution.
    Nontermination argument in form of an infinite program execution.
Stem:
[L8]         int p1 = __VERIFIER_nondet_int();
[L9]         int lk1;
[L11]        int p2 = __VERIFIER_nondet_int();
[L12]        int lk2;
[L14]        int p3 = __VERIFIER_nondet_int();
[L15]        int lk3;
[L17]        int p4 = __VERIFIER_nondet_int();
[L18]        int lk4;
[L20]        int p5 = __VERIFIER_nondet_int();
[L21]        int lk5;
[L23]        int p6 = __VERIFIER_nondet_int();
[L24]        int lk6;
[L26]        int p7 = __VERIFIER_nondet_int();
[L27]        int lk7;
[L29]        int p8 = __VERIFIER_nondet_int();
[L30]        int lk8;
[L32]        int p9 = __VERIFIER_nondet_int();
[L33]        int lk9;
[L35]        int p10 = __VERIFIER_nondet_int();
[L36]        int lk10;
[L38]        int p11 = __VERIFIER_nondet_int();
[L39]        int lk11;
[L41]        int p12 = __VERIFIER_nondet_int();
[L42]        int lk12;
[L44]        int p13 = __VERIFIER_nondet_int();
[L45]        int lk13;
[L47]        int p14 = __VERIFIER_nondet_int();
[L48]        int lk14;
[L50]        int p15 = __VERIFIER_nondet_int();
[L51]        int lk15;
[L54]        int cond;
Loop:
[L56]   COND TRUE   1
[L57]               cond = __VERIFIER_nondet_int()
[L58]   COND FALSE  !(cond == 0)
[L61]               lk1 = 0
[L63]               lk2 = 0
[L65]               lk3 = 0
[L67]               lk4 = 0
[L69]               lk5 = 0
[L71]               lk6 = 0
[L73]               lk7 = 0
[L75]               lk8 = 0
[L77]               lk9 = 0
[L79]               lk10 = 0
[L81]               lk11 = 0
[L83]               lk12 = 0
[L85]               lk13 = 0
[L87]               lk14 = 0
[L89]               lk15 = 0
[L93]   COND FALSE  !(p1 != 0)
[L97]   COND FALSE  !(p2 != 0)
[L101]  COND FALSE  !(p3 != 0)
[L105]  COND FALSE  !(p4 != 0)
[L109]  COND FALSE  !(p5 != 0)
[L113]  COND FALSE  !(p6 != 0)
[L117]  COND FALSE  !(p7 != 0)
[L121]  COND FALSE  !(p8 != 0)
[L125]  COND FALSE  !(p9 != 0)
[L129]  COND FALSE  !(p10 != 0)
[L133]  COND FALSE  !(p11 != 0)
[L137]  COND FALSE  !(p12 != 0)
[L141]  COND FALSE  !(p13 != 0)
[L145]  COND FALSE  !(p14 != 0)
[L149]  COND FALSE  !(p15 != 0)
[L155]  COND FALSE  !(p1 != 0)
[L160]  COND FALSE  !(p2 != 0)
[L165]  COND FALSE  !(p3 != 0)
[L170]  COND FALSE  !(p4 != 0)
[L175]  COND FALSE  !(p5 != 0)
[L180]  COND FALSE  !(p6 != 0)
[L185]  COND FALSE  !(p7 != 0)
[L190]  COND FALSE  !(p8 != 0)
[L195]  COND FALSE  !(p9 != 0)
[L200]  COND FALSE  !(p10 != 0)
[L205]  COND FALSE  !(p11 != 0)
[L210]  COND FALSE  !(p12 != 0)
[L215]  COND FALSE  !(p13 != 0)
[L220]  COND FALSE  !(p14 != 0)
[L225]  COND FALSE  !(p15 != 0)
End of lasso representation.
  - StatisticsResult: NonterminationArgumentStatistics
    Fixpoint
  - NonterminatingLassoResult [Line: 56]: Nonterminating execution
    Found a nonterminating execution for the following lasso shaped sequence of statements.
Stem:
[L8]         int p1 = __VERIFIER_nondet_int();
[L9]         int lk1;
[L11]        int p2 = __VERIFIER_nondet_int();
[L12]        int lk2;
[L14]        int p3 = __VERIFIER_nondet_int();
[L15]        int lk3;
[L17]        int p4 = __VERIFIER_nondet_int();
[L18]        int lk4;
[L20]        int p5 = __VERIFIER_nondet_int();
[L21]        int lk5;
[L23]        int p6 = __VERIFIER_nondet_int();
[L24]        int lk6;
[L26]        int p7 = __VERIFIER_nondet_int();
[L27]        int lk7;
[L29]        int p8 = __VERIFIER_nondet_int();
[L30]        int lk8;
[L32]        int p9 = __VERIFIER_nondet_int();
[L33]        int lk9;
[L35]        int p10 = __VERIFIER_nondet_int();
[L36]        int lk10;
[L38]        int p11 = __VERIFIER_nondet_int();
[L39]        int lk11;
[L41]        int p12 = __VERIFIER_nondet_int();
[L42]        int lk12;
[L44]        int p13 = __VERIFIER_nondet_int();
[L45]        int lk13;
[L47]        int p14 = __VERIFIER_nondet_int();
[L48]        int lk14;
[L50]        int p15 = __VERIFIER_nondet_int();
[L51]        int lk15;
[L54]        int cond;
Loop:
[L56]   COND TRUE   1
[L57]               cond = __VERIFIER_nondet_int()
[L58]   COND FALSE  !(cond == 0)
[L61]               lk1 = 0
[L63]               lk2 = 0
[L65]               lk3 = 0
[L67]               lk4 = 0
[L69]               lk5 = 0
[L71]               lk6 = 0
[L73]               lk7 = 0
[L75]               lk8 = 0
[L77]               lk9 = 0
[L79]               lk10 = 0
[L81]               lk11 = 0
[L83]               lk12 = 0
[L85]               lk13 = 0
[L87]               lk14 = 0
[L89]               lk15 = 0
[L93]   COND FALSE  !(p1 != 0)
[L97]   COND FALSE  !(p2 != 0)
[L101]  COND FALSE  !(p3 != 0)
[L105]  COND FALSE  !(p4 != 0)
[L109]  COND FALSE  !(p5 != 0)
[L113]  COND FALSE  !(p6 != 0)
[L117]  COND FALSE  !(p7 != 0)
[L121]  COND FALSE  !(p8 != 0)
[L125]  COND FALSE  !(p9 != 0)
[L129]  COND FALSE  !(p10 != 0)
[L133]  COND FALSE  !(p11 != 0)
[L137]  COND FALSE  !(p12 != 0)
[L141]  COND FALSE  !(p13 != 0)
[L145]  COND FALSE  !(p14 != 0)
[L149]  COND FALSE  !(p15 != 0)
[L155]  COND FALSE  !(p1 != 0)
[L160]  COND FALSE  !(p2 != 0)
[L165]  COND FALSE  !(p3 != 0)
[L170]  COND FALSE  !(p4 != 0)
[L175]  COND FALSE  !(p5 != 0)
[L180]  COND FALSE  !(p6 != 0)
[L185]  COND FALSE  !(p7 != 0)
[L190]  COND FALSE  !(p8 != 0)
[L195]  COND FALSE  !(p9 != 0)
[L200]  COND FALSE  !(p10 != 0)
[L205]  COND FALSE  !(p11 != 0)
[L210]  COND FALSE  !(p12 != 0)
[L215]  COND FALSE  !(p13 != 0)
[L220]  COND FALSE  !(p14 != 0)
[L225]  COND FALSE  !(p15 != 0)
End of lasso representation.
RESULT: Ultimate proved your program to be incorrect!
[2025-02-06 19:13:10,557 INFO  L552       MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0
Received shutdown request...
--- End real Ultimate output ---

Execution finished normally
Writing output log to file Ultimate.log
Writing human readable error path to file UltimateCounterExample.errorpath
Result:
FALSE(TERM)