./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/toy2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/toy2.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash a77d6f304c19846fdc8cd5bba9216d69953659ded966cffbf7faa285e2d864a4 --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:52:17,335 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:52:17,409 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:52:17,416 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:52:17,416 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:52:17,417 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:52:17,440 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:52:17,441 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:52:17,441 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:52:17,441 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:52:17,441 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:52:17,442 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:52:17,442 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:52:17,442 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:52:17,442 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:52:17,443 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:52:17,443 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:52:17,443 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:52:17,443 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> a77d6f304c19846fdc8cd5bba9216d69953659ded966cffbf7faa285e2d864a4 [2025-02-06 19:52:17,659 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:52:17,676 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:52:17,678 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:52:17,678 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:52:17,678 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:52:17,679 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/toy2.cil.c [2025-02-06 19:52:18,845 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a3c95e11c/2d179a1817e148fdac9c45bf2e4956a2/FLAG6ccf128d0 [2025-02-06 19:52:19,113 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:52:19,114 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/toy2.cil.c [2025-02-06 19:52:19,120 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a3c95e11c/2d179a1817e148fdac9c45bf2e4956a2/FLAG6ccf128d0 [2025-02-06 19:52:19,428 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a3c95e11c/2d179a1817e148fdac9c45bf2e4956a2 [2025-02-06 19:52:19,430 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:52:19,432 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:52:19,433 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:52:19,433 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:52:19,436 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:52:19,436 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,437 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@1c16604a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19, skipping insertion in model container [2025-02-06 19:52:19,437 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,452 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:52:19,587 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:52:19,595 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:52:19,630 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:52:19,643 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:52:19,643 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19 WrapperNode [2025-02-06 19:52:19,643 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:52:19,647 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:52:19,647 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:52:19,647 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:52:19,652 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,657 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,672 INFO L138 Inliner]: procedures = 20, calls = 16, calls flagged for inlining = 11, calls inlined = 11, statements flattened = 343 [2025-02-06 19:52:19,672 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:52:19,673 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:52:19,673 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:52:19,673 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:52:19,679 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,679 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,680 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,687 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:52:19,687 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,687 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,690 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,691 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,691 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,692 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,693 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:52:19,694 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:52:19,694 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:52:19,694 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:52:19,694 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (1/1) ... [2025-02-06 19:52:19,698 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:52:19,707 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:52:19,728 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:52:19,733 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:52:19,745 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:52:19,745 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:52:19,745 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:52:19,745 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:52:19,791 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:52:19,793 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:52:20,108 INFO L? ?]: Removed 20 outVars from TransFormulas that were not future-live. [2025-02-06 19:52:20,108 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:52:20,119 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:52:20,120 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:52:20,120 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20 BoogieIcfgContainer [2025-02-06 19:52:20,120 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:52:20,121 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:52:20,121 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:52:20,125 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:52:20,125 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,126 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:52:19" (1/3) ... [2025-02-06 19:52:20,128 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4e97571e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:52:20, skipping insertion in model container [2025-02-06 19:52:20,128 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,128 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:19" (2/3) ... [2025-02-06 19:52:20,128 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@4e97571e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:52:20, skipping insertion in model container [2025-02-06 19:52:20,128 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,129 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20" (3/3) ... [2025-02-06 19:52:20,130 INFO L363 chiAutomizerObserver]: Analyzing ICFG toy2.cil.c [2025-02-06 19:52:20,170 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:52:20,170 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:52:20,170 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:52:20,171 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:52:20,171 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:52:20,171 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:52:20,171 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:52:20,171 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:52:20,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,192 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:52:20,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,199 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:52:20,200 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,205 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-02-06 19:52:20,208 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,208 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,208 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,208 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,215 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume !(1 == ~wl_i~0);~wl_st~0 := 2;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,215 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !true;" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,219 INFO L85 PathProgramCache]: Analyzing trace with hash 1320311430, now seen corresponding path program 1 times [2025-02-06 19:52:20,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,224 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264453051] [2025-02-06 19:52:20,224 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,276 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,291 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,292 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,292 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,402 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,402 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [264453051] [2025-02-06 19:52:20,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [264453051] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,405 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1519771572] [2025-02-06 19:52:20,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,409 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:20,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,410 INFO L85 PathProgramCache]: Analyzing trace with hash -1426895027, now seen corresponding path program 1 times [2025-02-06 19:52:20,410 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,410 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [336333086] [2025-02-06 19:52:20,410 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,415 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-02-06 19:52:20,416 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-02-06 19:52:20,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [336333086] [2025-02-06 19:52:20,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [336333086] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:20,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772522058] [2025-02-06 19:52:20,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,424 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:20,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:20,440 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-02-06 19:52:20,441 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-02-06 19:52:20,442 INFO L87 Difference]: Start difference. First operand has 135 states, 134 states have (on average 1.7537313432835822) internal successors, (235), 134 states have internal predecessors, (235), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 11.5) internal successors, (23), 2 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:20,452 INFO L93 Difference]: Finished difference Result 133 states and 226 transitions. [2025-02-06 19:52:20,453 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133 states and 226 transitions. [2025-02-06 19:52:20,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133 states to 128 states and 221 transitions. [2025-02-06 19:52:20,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-02-06 19:52:20,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-02-06 19:52:20,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 221 transitions. [2025-02-06 19:52:20,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:20,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-02-06 19:52:20,479 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 221 transitions. [2025-02-06 19:52:20,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-02-06 19:52:20,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.7265625) internal successors, (221), 127 states have internal predecessors, (221), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,496 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 221 transitions. [2025-02-06 19:52:20,499 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-02-06 19:52:20,499 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-02-06 19:52:20,501 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 221 transitions. [2025-02-06 19:52:20,501 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:52:20,501 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 221 transitions. [2025-02-06 19:52:20,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,508 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume !(1 == ~wl_i~0);~wl_st~0 := 2;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,508 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,508 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,508 INFO L85 PathProgramCache]: Analyzing trace with hash 1320311430, now seen corresponding path program 2 times [2025-02-06 19:52:20,508 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,508 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [548869817] [2025-02-06 19:52:20,508 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:20,508 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,521 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,533 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,535 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:20,535 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,616 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,616 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [548869817] [2025-02-06 19:52:20,616 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [548869817] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,616 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,616 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034936327] [2025-02-06 19:52:20,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,616 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:20,617 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,617 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 1 times [2025-02-06 19:52:20,617 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,617 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17359674] [2025-02-06 19:52:20,617 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,624 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:20,630 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:20,630 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,661 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,661 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17359674] [2025-02-06 19:52:20,661 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17359674] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,661 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,661 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1663131079] [2025-02-06 19:52:20,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,662 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:20,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:20,663 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:20,664 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:20,664 INFO L87 Difference]: Start difference. First operand 128 states and 221 transitions. cyclomatic complexity: 94 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,687 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:20,688 INFO L93 Difference]: Finished difference Result 128 states and 220 transitions. [2025-02-06 19:52:20,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 220 transitions. [2025-02-06 19:52:20,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,693 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 220 transitions. [2025-02-06 19:52:20,693 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-02-06 19:52:20,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-02-06 19:52:20,694 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 220 transitions. [2025-02-06 19:52:20,694 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:20,694 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-02-06 19:52:20,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 220 transitions. [2025-02-06 19:52:20,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-02-06 19:52:20,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.71875) internal successors, (220), 127 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 220 transitions. [2025-02-06 19:52:20,699 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-02-06 19:52:20,700 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:20,700 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 220 transitions. [2025-02-06 19:52:20,701 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:52:20,701 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 220 transitions. [2025-02-06 19:52:20,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,702 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,702 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,703 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,703 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume !(1 == ~c1_i~0);~c1_st~0 := 2;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,703 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,703 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,704 INFO L85 PathProgramCache]: Analyzing trace with hash 1108960517, now seen corresponding path program 1 times [2025-02-06 19:52:20,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826693826] [2025-02-06 19:52:20,704 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,737 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,740 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,740 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,774 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,774 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,774 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826693826] [2025-02-06 19:52:20,774 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826693826] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,775 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,775 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,775 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1999514987] [2025-02-06 19:52:20,775 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,775 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:20,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1715491550, now seen corresponding path program 1 times [2025-02-06 19:52:20,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564052512] [2025-02-06 19:52:20,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,782 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:20,785 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:20,786 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,801 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,801 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,801 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564052512] [2025-02-06 19:52:20,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564052512] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1966841014] [2025-02-06 19:52:20,802 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,802 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:20,802 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:20,802 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:20,802 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:20,802 INFO L87 Difference]: Start difference. First operand 128 states and 220 transitions. cyclomatic complexity: 93 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:20,812 INFO L93 Difference]: Finished difference Result 128 states and 219 transitions. [2025-02-06 19:52:20,812 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 219 transitions. [2025-02-06 19:52:20,813 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,813 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 219 transitions. [2025-02-06 19:52:20,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-02-06 19:52:20,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-02-06 19:52:20,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 219 transitions. [2025-02-06 19:52:20,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:20,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-02-06 19:52:20,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 219 transitions. [2025-02-06 19:52:20,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-02-06 19:52:20,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.7109375) internal successors, (219), 127 states have internal predecessors, (219), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,818 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 219 transitions. [2025-02-06 19:52:20,818 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-02-06 19:52:20,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:20,819 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 219 transitions. [2025-02-06 19:52:20,819 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:52:20,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 219 transitions. [2025-02-06 19:52:20,820 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,820 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,820 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,821 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume !(1 == ~c2_i~0);~c2_st~0 := 2;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,821 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,822 INFO L85 PathProgramCache]: Analyzing trace with hash 1517784742, now seen corresponding path program 1 times [2025-02-06 19:52:20,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [422257317] [2025-02-06 19:52:20,822 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,827 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,830 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,830 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,830 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,853 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [422257317] [2025-02-06 19:52:20,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [422257317] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1912829780] [2025-02-06 19:52:20,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,853 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:20,853 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,853 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 2 times [2025-02-06 19:52:20,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1666158863] [2025-02-06 19:52:20,854 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:20,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,857 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:20,859 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:20,859 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:20,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,872 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,872 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,872 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1666158863] [2025-02-06 19:52:20,872 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1666158863] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,872 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,872 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,872 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1532843056] [2025-02-06 19:52:20,872 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,873 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:20,873 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:20,873 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:20,873 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:20,873 INFO L87 Difference]: Start difference. First operand 128 states and 219 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:20,883 INFO L93 Difference]: Finished difference Result 128 states and 218 transitions. [2025-02-06 19:52:20,883 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 218 transitions. [2025-02-06 19:52:20,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 218 transitions. [2025-02-06 19:52:20,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-02-06 19:52:20,884 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-02-06 19:52:20,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 218 transitions. [2025-02-06 19:52:20,885 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:20,885 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-02-06 19:52:20,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 218 transitions. [2025-02-06 19:52:20,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-02-06 19:52:20,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.703125) internal successors, (218), 127 states have internal predecessors, (218), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 218 transitions. [2025-02-06 19:52:20,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-02-06 19:52:20,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:20,889 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 218 transitions. [2025-02-06 19:52:20,889 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:52:20,889 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 218 transitions. [2025-02-06 19:52:20,890 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,890 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,891 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume !(1 == ~wb_i~0);~wb_st~0 := 2;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,891 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,892 INFO L85 PathProgramCache]: Analyzing trace with hash -1932710683, now seen corresponding path program 1 times [2025-02-06 19:52:20,892 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467668252] [2025-02-06 19:52:20,892 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,896 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467668252] [2025-02-06 19:52:20,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467668252] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432374618] [2025-02-06 19:52:20,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,925 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:20,926 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,926 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 3 times [2025-02-06 19:52:20,926 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,926 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [199959849] [2025-02-06 19:52:20,926 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:52:20,926 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,932 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:20,933 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:20,933 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:52:20,933 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:20,960 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:20,960 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:20,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [199959849] [2025-02-06 19:52:20,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [199959849] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:20,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:20,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:20,961 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1587696498] [2025-02-06 19:52:20,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:20,962 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:20,962 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:20,962 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:20,962 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:20,962 INFO L87 Difference]: Start difference. First operand 128 states and 218 transitions. cyclomatic complexity: 91 Second operand has 3 states, 3 states have (on average 8.0) internal successors, (24), 3 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:20,973 INFO L93 Difference]: Finished difference Result 128 states and 217 transitions. [2025-02-06 19:52:20,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 128 states and 217 transitions. [2025-02-06 19:52:20,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,979 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 128 states to 128 states and 217 transitions. [2025-02-06 19:52:20,979 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2025-02-06 19:52:20,980 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2025-02-06 19:52:20,980 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 217 transitions. [2025-02-06 19:52:20,980 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:20,980 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-02-06 19:52:20,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 217 transitions. [2025-02-06 19:52:20,983 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2025-02-06 19:52:20,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.6953125) internal successors, (217), 127 states have internal predecessors, (217), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 217 transitions. [2025-02-06 19:52:20,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-02-06 19:52:20,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:20,984 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 217 transitions. [2025-02-06 19:52:20,984 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:52:20,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 217 transitions. [2025-02-06 19:52:20,985 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 97 [2025-02-06 19:52:20,985 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,985 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,986 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:20,986 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume 0 == ~e_e~0;~e_e~0 := 1;" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:20,987 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,987 INFO L85 PathProgramCache]: Analyzing trace with hash -935638330, now seen corresponding path program 1 times [2025-02-06 19:52:20,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [732547450] [2025-02-06 19:52:20,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,991 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:20,994 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:20,994 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,994 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [732547450] [2025-02-06 19:52:21,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [732547450] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,019 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:21,019 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1000826615] [2025-02-06 19:52:21,019 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,019 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,019 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,019 INFO L85 PathProgramCache]: Analyzing trace with hash 347199293, now seen corresponding path program 4 times [2025-02-06 19:52:21,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1734881386] [2025-02-06 19:52:21,020 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:52:21,020 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,024 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 28 statements into 2 equivalence classes. [2025-02-06 19:52:21,026 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,026 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-02-06 19:52:21,026 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1734881386] [2025-02-06 19:52:21,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1734881386] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [510522643] [2025-02-06 19:52:21,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,045 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,045 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,045 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,045 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,045 INFO L87 Difference]: Start difference. First operand 128 states and 217 transitions. cyclomatic complexity: 90 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,148 INFO L93 Difference]: Finished difference Result 218 states and 363 transitions. [2025-02-06 19:52:21,148 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 363 transitions. [2025-02-06 19:52:21,149 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 178 [2025-02-06 19:52:21,154 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 363 transitions. [2025-02-06 19:52:21,154 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218 [2025-02-06 19:52:21,154 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218 [2025-02-06 19:52:21,154 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 363 transitions. [2025-02-06 19:52:21,155 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,155 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 363 transitions. [2025-02-06 19:52:21,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 363 transitions. [2025-02-06 19:52:21,163 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 213. [2025-02-06 19:52:21,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 213 states, 213 states have (on average 1.6807511737089202) internal successors, (358), 212 states have internal predecessors, (358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 358 transitions. [2025-02-06 19:52:21,165 INFO L240 hiAutomatonCegarLoop]: Abstraction has 213 states and 358 transitions. [2025-02-06 19:52:21,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:21,169 INFO L432 stractBuchiCegarLoop]: Abstraction has 213 states and 358 transitions. [2025-02-06 19:52:21,169 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:52:21,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 213 states and 358 transitions. [2025-02-06 19:52:21,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 178 [2025-02-06 19:52:21,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,170 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,171 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:21,171 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume 1 == ~wl_pc~0;" "assume 1 == ~e_wl~0;~wl_st~0 := 0;" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:21,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1442120476, now seen corresponding path program 1 times [2025-02-06 19:52:21,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1084274579] [2025-02-06 19:52:21,171 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,178 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,184 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,184 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1084274579] [2025-02-06 19:52:21,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1084274579] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,228 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,228 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:21,228 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1449996144] [2025-02-06 19:52:21,228 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,228 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,228 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,228 INFO L85 PathProgramCache]: Analyzing trace with hash 1854751102, now seen corresponding path program 1 times [2025-02-06 19:52:21,228 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152916267] [2025-02-06 19:52:21,228 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,240 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:21,241 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,241 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,241 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [152916267] [2025-02-06 19:52:21,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [152916267] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,263 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,263 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1118027869] [2025-02-06 19:52:21,263 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,263 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,263 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,264 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,264 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,264 INFO L87 Difference]: Start difference. First operand 213 states and 358 transitions. cyclomatic complexity: 147 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,369 INFO L93 Difference]: Finished difference Result 544 states and 900 transitions. [2025-02-06 19:52:21,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 544 states and 900 transitions. [2025-02-06 19:52:21,372 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-02-06 19:52:21,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 544 states to 544 states and 900 transitions. [2025-02-06 19:52:21,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 544 [2025-02-06 19:52:21,375 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 544 [2025-02-06 19:52:21,375 INFO L73 IsDeterministic]: Start isDeterministic. Operand 544 states and 900 transitions. [2025-02-06 19:52:21,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,376 INFO L218 hiAutomatonCegarLoop]: Abstraction has 544 states and 900 transitions. [2025-02-06 19:52:21,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 544 states and 900 transitions. [2025-02-06 19:52:21,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 544 to 518. [2025-02-06 19:52:21,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 518 states, 518 states have (on average 1.664092664092664) internal successors, (862), 517 states have internal predecessors, (862), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 518 states to 518 states and 862 transitions. [2025-02-06 19:52:21,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 518 states and 862 transitions. [2025-02-06 19:52:21,395 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:21,396 INFO L432 stractBuchiCegarLoop]: Abstraction has 518 states and 862 transitions. [2025-02-06 19:52:21,396 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:52:21,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 518 states and 862 transitions. [2025-02-06 19:52:21,398 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 486 [2025-02-06 19:52:21,398 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,398 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,403 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:21,403 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume 1 == ~e_e~0;~e_e~0 := 2;" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:21,404 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,404 INFO L85 PathProgramCache]: Analyzing trace with hash -123185569, now seen corresponding path program 1 times [2025-02-06 19:52:21,404 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,404 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1332607527] [2025-02-06 19:52:21,404 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,404 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,408 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,410 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,410 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,410 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1332607527] [2025-02-06 19:52:21,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1332607527] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:21,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1491640260] [2025-02-06 19:52:21,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,443 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,444 INFO L85 PathProgramCache]: Analyzing trace with hash -207939741, now seen corresponding path program 1 times [2025-02-06 19:52:21,444 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,444 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1079863556] [2025-02-06 19:52:21,444 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,444 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,450 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:21,452 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,455 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,455 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1079863556] [2025-02-06 19:52:21,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1079863556] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,466 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,466 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [130723113] [2025-02-06 19:52:21,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,467 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,467 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,467 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,467 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,468 INFO L87 Difference]: Start difference. First operand 518 states and 862 transitions. cyclomatic complexity: 348 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,524 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,524 INFO L93 Difference]: Finished difference Result 1009 states and 1646 transitions. [2025-02-06 19:52:21,524 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1009 states and 1646 transitions. [2025-02-06 19:52:21,530 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 959 [2025-02-06 19:52:21,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1009 states to 1009 states and 1646 transitions. [2025-02-06 19:52:21,535 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1009 [2025-02-06 19:52:21,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1009 [2025-02-06 19:52:21,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1009 states and 1646 transitions. [2025-02-06 19:52:21,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,536 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1009 states and 1646 transitions. [2025-02-06 19:52:21,537 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1009 states and 1646 transitions. [2025-02-06 19:52:21,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1009 to 1007. [2025-02-06 19:52:21,561 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1007 states, 1007 states have (on average 1.6325719960278053) internal successors, (1644), 1006 states have internal predecessors, (1644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1007 states to 1007 states and 1644 transitions. [2025-02-06 19:52:21,564 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1007 states and 1644 transitions. [2025-02-06 19:52:21,565 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:21,565 INFO L432 stractBuchiCegarLoop]: Abstraction has 1007 states and 1644 transitions. [2025-02-06 19:52:21,565 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:52:21,565 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1007 states and 1644 transitions. [2025-02-06 19:52:21,569 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 957 [2025-02-06 19:52:21,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,570 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:21,570 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume 0 == ~e_c~0;~e_c~0 := 1;" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume 1 == ~e_c~0;~r_st~0 := 0;" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume 1 == ~e_c~0;~e_c~0 := 2;" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:21,571 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,571 INFO L85 PathProgramCache]: Analyzing trace with hash 171111168, now seen corresponding path program 1 times [2025-02-06 19:52:21,571 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,571 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [936026432] [2025-02-06 19:52:21,571 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,571 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,574 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,576 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,576 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,605 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,605 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [936026432] [2025-02-06 19:52:21,605 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [936026432] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,605 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:21,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [166686899] [2025-02-06 19:52:21,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,605 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,606 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,606 INFO L85 PathProgramCache]: Analyzing trace with hash -179310590, now seen corresponding path program 1 times [2025-02-06 19:52:21,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1555699555] [2025-02-06 19:52:21,606 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,610 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:21,611 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,622 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,622 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1555699555] [2025-02-06 19:52:21,622 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1555699555] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,622 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198176440] [2025-02-06 19:52:21,623 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,623 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,623 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,623 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,624 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,624 INFO L87 Difference]: Start difference. First operand 1007 states and 1644 transitions. cyclomatic complexity: 645 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,689 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,689 INFO L93 Difference]: Finished difference Result 1195 states and 1921 transitions. [2025-02-06 19:52:21,689 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1195 states and 1921 transitions. [2025-02-06 19:52:21,695 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1154 [2025-02-06 19:52:21,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1195 states to 1195 states and 1921 transitions. [2025-02-06 19:52:21,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1195 [2025-02-06 19:52:21,702 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1195 [2025-02-06 19:52:21,703 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1195 states and 1921 transitions. [2025-02-06 19:52:21,704 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,704 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1195 states and 1921 transitions. [2025-02-06 19:52:21,705 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1195 states and 1921 transitions. [2025-02-06 19:52:21,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1195 to 1185. [2025-02-06 19:52:21,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1185 states, 1185 states have (on average 1.6126582278481012) internal successors, (1911), 1184 states have internal predecessors, (1911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,730 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1185 states to 1185 states and 1911 transitions. [2025-02-06 19:52:21,731 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1185 states and 1911 transitions. [2025-02-06 19:52:21,731 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:21,732 INFO L432 stractBuchiCegarLoop]: Abstraction has 1185 states and 1911 transitions. [2025-02-06 19:52:21,732 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:52:21,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1185 states and 1911 transitions. [2025-02-06 19:52:21,736 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 1154 [2025-02-06 19:52:21,737 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,738 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,739 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:21,739 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~e_f~0;~e_f~0 := 1;" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume 1 == ~e_f~0;~e_f~0 := 2;" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:21,739 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,739 INFO L85 PathProgramCache]: Analyzing trace with hash -122291839, now seen corresponding path program 1 times [2025-02-06 19:52:21,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007094904] [2025-02-06 19:52:21,739 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,745 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,747 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,748 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,748 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,775 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,776 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,776 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007094904] [2025-02-06 19:52:21,776 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007094904] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,776 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,776 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:21,777 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [579136292] [2025-02-06 19:52:21,777 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,777 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,777 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,777 INFO L85 PathProgramCache]: Analyzing trace with hash 202635427, now seen corresponding path program 1 times [2025-02-06 19:52:21,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [813333965] [2025-02-06 19:52:21,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,781 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:21,781 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,781 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,781 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [813333965] [2025-02-06 19:52:21,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [813333965] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1694342721] [2025-02-06 19:52:21,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,791 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,791 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,791 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,791 INFO L87 Difference]: Start difference. First operand 1185 states and 1911 transitions. cyclomatic complexity: 735 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,855 INFO L93 Difference]: Finished difference Result 1119 states and 1758 transitions. [2025-02-06 19:52:21,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1119 states and 1758 transitions. [2025-02-06 19:52:21,860 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1081 [2025-02-06 19:52:21,865 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1119 states to 1119 states and 1758 transitions. [2025-02-06 19:52:21,865 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1119 [2025-02-06 19:52:21,867 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1119 [2025-02-06 19:52:21,867 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1119 states and 1758 transitions. [2025-02-06 19:52:21,868 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,868 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1119 states and 1758 transitions. [2025-02-06 19:52:21,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1119 states and 1758 transitions. [2025-02-06 19:52:21,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1119 to 1107. [2025-02-06 19:52:21,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1107 states, 1107 states have (on average 1.5772357723577235) internal successors, (1746), 1106 states have internal predecessors, (1746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,919 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1107 states to 1107 states and 1746 transitions. [2025-02-06 19:52:21,919 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1107 states and 1746 transitions. [2025-02-06 19:52:21,922 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:21,922 INFO L432 stractBuchiCegarLoop]: Abstraction has 1107 states and 1746 transitions. [2025-02-06 19:52:21,922 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:52:21,923 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1107 states and 1746 transitions. [2025-02-06 19:52:21,926 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1079 [2025-02-06 19:52:21,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,927 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:21,927 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:21,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,927 INFO L85 PathProgramCache]: Analyzing trace with hash -122262048, now seen corresponding path program 1 times [2025-02-06 19:52:21,927 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,927 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765999062] [2025-02-06 19:52:21,927 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,927 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,931 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,933 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,933 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,933 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:21,933 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:21,934 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:21,935 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:21,935 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,935 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:21,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:21,949 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,949 INFO L85 PathProgramCache]: Analyzing trace with hash 1556868645, now seen corresponding path program 1 times [2025-02-06 19:52:21,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1316634279] [2025-02-06 19:52:21,949 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,952 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:21,953 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:21,953 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,953 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,966 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,966 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1316634279] [2025-02-06 19:52:21,966 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1316634279] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,966 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,966 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,966 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465709674] [2025-02-06 19:52:21,966 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,966 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,966 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,967 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:21,967 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:21,967 INFO L87 Difference]: Start difference. First operand 1107 states and 1746 transitions. cyclomatic complexity: 646 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,995 INFO L93 Difference]: Finished difference Result 1626 states and 2540 transitions. [2025-02-06 19:52:21,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1626 states and 2540 transitions. [2025-02-06 19:52:22,002 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1583 [2025-02-06 19:52:22,008 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1626 states to 1626 states and 2540 transitions. [2025-02-06 19:52:22,008 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1626 [2025-02-06 19:52:22,009 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1626 [2025-02-06 19:52:22,009 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1626 states and 2540 transitions. [2025-02-06 19:52:22,011 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,011 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1626 states and 2540 transitions. [2025-02-06 19:52:22,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1626 states and 2540 transitions. [2025-02-06 19:52:22,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1626 to 1622. [2025-02-06 19:52:22,026 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1622 states, 1622 states have (on average 1.563501849568434) internal successors, (2536), 1621 states have internal predecessors, (2536), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1622 states to 1622 states and 2536 transitions. [2025-02-06 19:52:22,030 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1622 states and 2536 transitions. [2025-02-06 19:52:22,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,031 INFO L432 stractBuchiCegarLoop]: Abstraction has 1622 states and 2536 transitions. [2025-02-06 19:52:22,031 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:52:22,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1622 states and 2536 transitions. [2025-02-06 19:52:22,037 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 1579 [2025-02-06 19:52:22,037 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,037 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,038 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,038 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,038 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" [2025-02-06 19:52:22,038 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume 0 == ~e_wl~0;~e_wl~0 := 1;" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:22,038 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,038 INFO L85 PathProgramCache]: Analyzing trace with hash -251344768, now seen corresponding path program 1 times [2025-02-06 19:52:22,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [43469393] [2025-02-06 19:52:22,038 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,039 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:22,043 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:22,043 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,043 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,077 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,077 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,077 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [43469393] [2025-02-06 19:52:22,077 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [43469393] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,077 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,077 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 19:52:22,077 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [168296687] [2025-02-06 19:52:22,077 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,077 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:22,077 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,077 INFO L85 PathProgramCache]: Analyzing trace with hash 1556868614, now seen corresponding path program 1 times [2025-02-06 19:52:22,077 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540664950] [2025-02-06 19:52:22,077 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,078 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,080 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:22,081 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:22,081 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540664950] [2025-02-06 19:52:22,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540664950] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:22,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1403053714] [2025-02-06 19:52:22,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,090 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,090 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:22,090 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:22,091 INFO L87 Difference]: Start difference. First operand 1622 states and 2536 transitions. cyclomatic complexity: 921 Second operand has 4 states, 4 states have (on average 6.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,153 INFO L93 Difference]: Finished difference Result 2609 states and 4065 transitions. [2025-02-06 19:52:22,153 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2609 states and 4065 transitions. [2025-02-06 19:52:22,163 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2557 [2025-02-06 19:52:22,172 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2609 states to 2609 states and 4065 transitions. [2025-02-06 19:52:22,172 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2609 [2025-02-06 19:52:22,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2609 [2025-02-06 19:52:22,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2609 states and 4065 transitions. [2025-02-06 19:52:22,177 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,177 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2609 states and 4065 transitions. [2025-02-06 19:52:22,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2609 states and 4065 transitions. [2025-02-06 19:52:22,200 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2609 to 2577. [2025-02-06 19:52:22,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2577 states, 2577 states have (on average 1.561893674815677) internal successors, (4025), 2576 states have internal predecessors, (4025), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2577 states to 2577 states and 4025 transitions. [2025-02-06 19:52:22,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2577 states and 4025 transitions. [2025-02-06 19:52:22,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:22,210 INFO L432 stractBuchiCegarLoop]: Abstraction has 2577 states and 4025 transitions. [2025-02-06 19:52:22,210 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:52:22,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2577 states and 4025 transitions. [2025-02-06 19:52:22,218 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2549 [2025-02-06 19:52:22,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,218 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,218 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,218 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume 1 == ~e_wl~0;~e_wl~0 := 2;" [2025-02-06 19:52:22,218 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:22,218 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,218 INFO L85 PathProgramCache]: Analyzing trace with hash -122262049, now seen corresponding path program 1 times [2025-02-06 19:52:22,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1385482385] [2025-02-06 19:52:22,219 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,222 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:22,223 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:22,223 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,223 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1385482385] [2025-02-06 19:52:22,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1385482385] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:22,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2018156017] [2025-02-06 19:52:22,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,282 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:22,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1263465638, now seen corresponding path program 1 times [2025-02-06 19:52:22,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748024888] [2025-02-06 19:52:22,286 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,289 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:22,290 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:22,290 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,290 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,302 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,302 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748024888] [2025-02-06 19:52:22,302 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748024888] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,302 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,302 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:22,302 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [359171304] [2025-02-06 19:52:22,302 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,302 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,302 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,302 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:22,302 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:22,302 INFO L87 Difference]: Start difference. First operand 2577 states and 4025 transitions. cyclomatic complexity: 1461 Second operand has 4 states, 3 states have (on average 8.0) internal successors, (24), 4 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,357 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,357 INFO L93 Difference]: Finished difference Result 2376 states and 3681 transitions. [2025-02-06 19:52:22,358 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2376 states and 3681 transitions. [2025-02-06 19:52:22,368 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2336 [2025-02-06 19:52:22,378 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2376 states to 2376 states and 3681 transitions. [2025-02-06 19:52:22,378 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2376 [2025-02-06 19:52:22,380 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2376 [2025-02-06 19:52:22,380 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2376 states and 3681 transitions. [2025-02-06 19:52:22,384 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,384 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2376 states and 3681 transitions. [2025-02-06 19:52:22,385 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2376 states and 3681 transitions. [2025-02-06 19:52:22,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2376 to 2368. [2025-02-06 19:52:22,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2368 states, 2368 states have (on average 1.551097972972973) internal successors, (3673), 2367 states have internal predecessors, (3673), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,418 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2368 states to 2368 states and 3673 transitions. [2025-02-06 19:52:22,419 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2368 states and 3673 transitions. [2025-02-06 19:52:22,419 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:22,419 INFO L432 stractBuchiCegarLoop]: Abstraction has 2368 states and 3673 transitions. [2025-02-06 19:52:22,419 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 19:52:22,419 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2368 states and 3673 transitions. [2025-02-06 19:52:22,425 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 2336 [2025-02-06 19:52:22,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,425 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" [2025-02-06 19:52:22,425 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~wl_st~0);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~c_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~e_f~0);" "assume 0 == ~e_g~0;~e_g~0 := 1;" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume 1 == ~e_g~0;~e_g~0 := 2;" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume 0 == ~wl_st~0;" [2025-02-06 19:52:22,426 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,426 INFO L85 PathProgramCache]: Analyzing trace with hash -122262048, now seen corresponding path program 2 times [2025-02-06 19:52:22,426 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,426 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1003521952] [2025-02-06 19:52:22,426 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:22,426 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,429 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:22,431 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:22,431 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:22,431 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,431 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,433 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-06 19:52:22,435 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-06 19:52:22,435 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,435 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,439 INFO L85 PathProgramCache]: Analyzing trace with hash 1263465638, now seen corresponding path program 2 times [2025-02-06 19:52:22,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,439 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [3316295] [2025-02-06 19:52:22,439 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:22,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,443 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-02-06 19:52:22,443 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-06 19:52:22,444 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:22,444 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,460 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [3316295] [2025-02-06 19:52:22,460 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [3316295] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,460 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:22,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [342836204] [2025-02-06 19:52:22,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,460 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,460 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,460 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,460 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,460 INFO L87 Difference]: Start difference. First operand 2368 states and 3673 transitions. cyclomatic complexity: 1318 Second operand has 3 states, 2 states have (on average 14.0) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,487 INFO L93 Difference]: Finished difference Result 2650 states and 4034 transitions. [2025-02-06 19:52:22,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2650 states and 4034 transitions. [2025-02-06 19:52:22,495 INFO L131 ngComponentsAnalysis]: Automaton has 19 accepting balls. 2562 [2025-02-06 19:52:22,504 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2650 states to 2650 states and 4034 transitions. [2025-02-06 19:52:22,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2650 [2025-02-06 19:52:22,506 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2650 [2025-02-06 19:52:22,506 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2650 states and 4034 transitions. [2025-02-06 19:52:22,508 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,508 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2650 states and 4034 transitions. [2025-02-06 19:52:22,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2650 states and 4034 transitions. [2025-02-06 19:52:22,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2650 to 2323. [2025-02-06 19:52:22,538 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2323 states, 2323 states have (on average 1.5264743865690917) internal successors, (3546), 2322 states have internal predecessors, (3546), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,545 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2323 states to 2323 states and 3546 transitions. [2025-02-06 19:52:22,545 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2323 states and 3546 transitions. [2025-02-06 19:52:22,545 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,546 INFO L432 stractBuchiCegarLoop]: Abstraction has 2323 states and 3546 transitions. [2025-02-06 19:52:22,546 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 19:52:22,546 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2323 states and 3546 transitions. [2025-02-06 19:52:22,551 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 2247 [2025-02-06 19:52:22,551 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,551 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,551 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,551 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,551 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:52:22,551 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~c1_st~0);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-02-06 19:52:22,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,551 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 1 times [2025-02-06 19:52:22,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [159890823] [2025-02-06 19:52:22,552 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,556 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:22,557 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:22,557 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,557 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,557 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,559 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:22,560 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:22,560 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,560 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,563 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,563 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,563 INFO L85 PathProgramCache]: Analyzing trace with hash 339625268, now seen corresponding path program 1 times [2025-02-06 19:52:22,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1063485632] [2025-02-06 19:52:22,563 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:52:22,565 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:52:22,565 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,565 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,565 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-06 19:52:22,566 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-06 19:52:22,566 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,566 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,567 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,567 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,567 INFO L85 PathProgramCache]: Analyzing trace with hash 1341855250, now seen corresponding path program 1 times [2025-02-06 19:52:22,567 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,567 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1705124062] [2025-02-06 19:52:22,567 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,567 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,571 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-02-06 19:52:22,573 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-02-06 19:52:22,573 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,573 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,584 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,584 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,584 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1705124062] [2025-02-06 19:52:22,584 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1705124062] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,584 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,585 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:22,585 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2058233629] [2025-02-06 19:52:22,585 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,631 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,631 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,631 INFO L87 Difference]: Start difference. First operand 2323 states and 3546 transitions. cyclomatic complexity: 1238 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,686 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,686 INFO L93 Difference]: Finished difference Result 3568 states and 5413 transitions. [2025-02-06 19:52:22,686 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3568 states and 5413 transitions. [2025-02-06 19:52:22,700 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 3474 [2025-02-06 19:52:22,719 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3568 states to 3568 states and 5413 transitions. [2025-02-06 19:52:22,719 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3568 [2025-02-06 19:52:22,721 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3568 [2025-02-06 19:52:22,722 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3568 states and 5413 transitions. [2025-02-06 19:52:22,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,726 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-02-06 19:52:22,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3568 states and 5413 transitions. [2025-02-06 19:52:22,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3568 to 3568. [2025-02-06 19:52:22,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3568 states, 3568 states have (on average 1.5170964125560538) internal successors, (5413), 3567 states have internal predecessors, (5413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3568 states to 3568 states and 5413 transitions. [2025-02-06 19:52:22,768 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-02-06 19:52:22,768 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,768 INFO L432 stractBuchiCegarLoop]: Abstraction has 3568 states and 5413 transitions. [2025-02-06 19:52:22,768 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-06 19:52:22,769 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3568 states and 5413 transitions. [2025-02-06 19:52:22,774 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 3474 [2025-02-06 19:52:22,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,775 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:52:22,776 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~c2_st~0);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-02-06 19:52:22,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 2 times [2025-02-06 19:52:22,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2012763575] [2025-02-06 19:52:22,776 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:22,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,780 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:22,781 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:22,782 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:22,782 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,782 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:22,784 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:22,785 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,785 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1938204300, now seen corresponding path program 1 times [2025-02-06 19:52:22,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124620995] [2025-02-06 19:52:22,788 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,790 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:52:22,790 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:52:22,790 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,790 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,791 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-02-06 19:52:22,791 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-02-06 19:52:22,791 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,791 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,792 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,793 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,793 INFO L85 PathProgramCache]: Analyzing trace with hash -1352404626, now seen corresponding path program 1 times [2025-02-06 19:52:22,793 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,793 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071307910] [2025-02-06 19:52:22,793 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,800 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 35 statements into 1 equivalence classes. [2025-02-06 19:52:22,802 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 35 of 35 statements. [2025-02-06 19:52:22,802 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,802 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,827 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,827 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,827 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2071307910] [2025-02-06 19:52:22,827 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2071307910] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,827 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,827 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:22,827 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [4663353] [2025-02-06 19:52:22,827 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,875 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,875 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,875 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,875 INFO L87 Difference]: Start difference. First operand 3568 states and 5413 transitions. cyclomatic complexity: 1860 Second operand has 3 states, 3 states have (on average 11.666666666666666) internal successors, (35), 3 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,903 INFO L93 Difference]: Finished difference Result 5616 states and 8441 transitions. [2025-02-06 19:52:22,903 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5616 states and 8441 transitions. [2025-02-06 19:52:22,919 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 5486 [2025-02-06 19:52:22,934 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5616 states to 5616 states and 8441 transitions. [2025-02-06 19:52:22,934 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5616 [2025-02-06 19:52:22,938 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5616 [2025-02-06 19:52:22,938 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5616 states and 8441 transitions. [2025-02-06 19:52:22,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-02-06 19:52:22,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5616 states and 8441 transitions. [2025-02-06 19:52:23,035 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5616 to 5616. [2025-02-06 19:52:23,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5616 states, 5616 states have (on average 1.5030270655270654) internal successors, (8441), 5615 states have internal predecessors, (8441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:23,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5616 states to 5616 states and 8441 transitions. [2025-02-06 19:52:23,057 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-02-06 19:52:23,058 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:23,058 INFO L432 stractBuchiCegarLoop]: Abstraction has 5616 states and 8441 transitions. [2025-02-06 19:52:23,058 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-06 19:52:23,058 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5616 states and 8441 transitions. [2025-02-06 19:52:23,073 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 5486 [2025-02-06 19:52:23,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:23,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:23,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:23,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:23,074 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:52:23,075 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~c2_st~0;havoc eval_#t~nondet6#1;eval_~tmp___1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp___1~0#1);" "assume !(0 == ~wb_st~0);" "assume !(0 == ~r_st~0);" [2025-02-06 19:52:23,075 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,075 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 3 times [2025-02-06 19:52:23,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080590548] [2025-02-06 19:52:23,075 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:52:23,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,080 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:23,083 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:23,083 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:52:23,083 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,083 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,084 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:23,087 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:23,087 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,087 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,090 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:23,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,094 INFO L85 PathProgramCache]: Analyzing trace with hash -45216854, now seen corresponding path program 1 times [2025-02-06 19:52:23,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,095 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [345180047] [2025-02-06 19:52:23,095 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:23,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,096 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:52:23,097 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:52:23,097 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,097 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,097 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,098 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:52:23,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:52:23,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,100 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:23,100 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,100 INFO L85 PathProgramCache]: Analyzing trace with hash 1025121544, now seen corresponding path program 1 times [2025-02-06 19:52:23,100 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,100 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1260341599] [2025-02-06 19:52:23,101 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:23,101 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,105 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-06 19:52:23,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-06 19:52:23,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:23,121 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:23,121 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:23,121 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1260341599] [2025-02-06 19:52:23,121 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1260341599] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:23,121 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:23,121 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:23,121 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136384675] [2025-02-06 19:52:23,121 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:23,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:23,150 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:23,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:23,151 INFO L87 Difference]: Start difference. First operand 5616 states and 8441 transitions. cyclomatic complexity: 2840 Second operand has 3 states, 3 states have (on average 12.0) internal successors, (36), 3 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:23,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:23,193 INFO L93 Difference]: Finished difference Result 9558 states and 14306 transitions. [2025-02-06 19:52:23,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9558 states and 14306 transitions. [2025-02-06 19:52:23,226 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 9344 [2025-02-06 19:52:23,261 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9558 states to 9558 states and 14306 transitions. [2025-02-06 19:52:23,261 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9558 [2025-02-06 19:52:23,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9558 [2025-02-06 19:52:23,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9558 states and 14306 transitions. [2025-02-06 19:52:23,305 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:23,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-02-06 19:52:23,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9558 states and 14306 transitions. [2025-02-06 19:52:23,517 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9558 to 9558. [2025-02-06 19:52:23,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9558 states, 9558 states have (on average 1.496756643649299) internal successors, (14306), 9557 states have internal predecessors, (14306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:23,663 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9558 states to 9558 states and 14306 transitions. [2025-02-06 19:52:23,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-02-06 19:52:23,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:23,667 INFO L432 stractBuchiCegarLoop]: Abstraction has 9558 states and 14306 transitions. [2025-02-06 19:52:23,667 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-06 19:52:23,668 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9558 states and 14306 transitions. [2025-02-06 19:52:23,712 INFO L131 ngComponentsAnalysis]: Automaton has 15 accepting balls. 9344 [2025-02-06 19:52:23,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:23,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:23,713 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:23,713 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:23,713 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);call #Ultimate.allocInit(12, 3);~c~0 := 0;~c_t~0 := 0;~c_req_up~0 := 0;~p_in~0 := 0;~p_out~0 := 0;~wl_st~0 := 0;~c1_st~0 := 0;~c2_st~0 := 0;~wb_st~0 := 0;~r_st~0 := 0;~wl_i~0 := 0;~c1_i~0 := 0;~c2_i~0 := 0;~wb_i~0 := 0;~r_i~0 := 0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~e_e~0 := 0;~e_f~0 := 0;~e_g~0 := 0;~e_c~0 := 0;~e_p_in~0 := 0;~e_wl~0 := 0;~d~0 := 0;~data~0 := 0;~processed~0 := 0;~t_b~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~0#1;havoc main_~__retres1~0#1;~e_wl~0 := 2;~e_c~0 := ~e_wl~0;~e_g~0 := ~e_c~0;~e_f~0 := ~e_g~0;~e_e~0 := ~e_f~0;~wl_pc~0 := 0;~c1_pc~0 := 0;~c2_pc~0 := 0;~wb_pc~0 := 0;~wb_i~0 := 1;~c2_i~0 := ~wb_i~0;~c1_i~0 := ~c2_i~0;~wl_i~0 := ~c1_i~0;~r_i~0 := 0;~c_req_up~0 := 0;~d~0 := 0;~c~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~c_req_up~0);" "assume 1 == ~wl_i~0;~wl_st~0 := 0;" "assume 1 == ~c1_i~0;~c1_st~0 := 0;" "assume 1 == ~c2_i~0;~c2_st~0 := 0;" "assume 1 == ~wb_i~0;~wb_st~0 := 0;" "assume !(1 == ~r_i~0);~r_st~0 := 2;" "assume !(0 == ~e_f~0);" "assume !(0 == ~e_g~0);" "assume !(0 == ~e_e~0);" "assume !(0 == ~e_c~0);" "assume !(0 == ~e_wl~0);" "assume !(1 == ~wl_pc~0);" "assume !(2 == ~wl_pc~0);" "assume !(1 == ~c1_pc~0);" "assume !(1 == ~c2_pc~0);" "assume !(1 == ~wb_pc~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_e~0);" "assume !(1 == ~e_f~0);" "assume !(1 == ~e_g~0);" "assume !(1 == ~e_c~0);" "assume !(1 == ~e_wl~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-02-06 19:52:23,713 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume 0 == ~wl_st~0;" "assume 0 == ~wl_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~c1_st~0;havoc eval_#t~nondet5#1;eval_~tmp___0~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~c2_st~0;havoc eval_#t~nondet6#1;eval_~tmp___1~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp___1~0#1);" "assume 0 == ~wb_st~0;havoc eval_#t~nondet7#1;eval_~tmp___2~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___2~0#1);" "assume !(0 == ~r_st~0);" [2025-02-06 19:52:23,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,713 INFO L85 PathProgramCache]: Analyzing trace with hash -1529704737, now seen corresponding path program 4 times [2025-02-06 19:52:23,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54075043] [2025-02-06 19:52:23,714 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:52:23,714 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,721 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 26 statements into 2 equivalence classes. [2025-02-06 19:52:23,723 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:23,724 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:52:23,724 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,724 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,725 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:23,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:23,728 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,728 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,731 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:23,732 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1401722858, now seen corresponding path program 1 times [2025-02-06 19:52:23,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [357362806] [2025-02-06 19:52:23,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:23,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,735 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-02-06 19:52:23,735 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-02-06 19:52:23,735 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,735 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,735 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,736 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-02-06 19:52:23,736 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-02-06 19:52:23,736 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,736 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,738 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:23,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:23,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1713996408, now seen corresponding path program 1 times [2025-02-06 19:52:23,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:23,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127782668] [2025-02-06 19:52:23,738 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:23,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:23,742 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:52:23,744 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:52:23,744 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,744 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,744 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,745 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:52:23,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:52:23,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,753 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:24,633 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:24,636 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:24,636 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:24,636 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:24,636 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:24,643 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-02-06 19:52:24,646 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-02-06 19:52:24,646 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:24,646 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:24,733 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:52:24 BoogieIcfgContainer [2025-02-06 19:52:24,734 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:52:24,734 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:52:24,734 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:52:24,734 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:52:24,735 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20" (3/4) ... [2025-02-06 19:52:24,736 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:52:24,790 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:52:24,790 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:52:24,790 INFO L158 Benchmark]: Toolchain (without parser) took 5359.80ms. Allocated memory was 167.8MB in the beginning and 260.0MB in the end (delta: 92.3MB). Free memory was 130.8MB in the beginning and 113.0MB in the end (delta: 17.8MB). Peak memory consumption was 111.7MB. Max. memory is 16.1GB. [2025-02-06 19:52:24,790 INFO L158 Benchmark]: CDTParser took 0.15ms. Allocated memory is still 209.7MB. Free memory is still 133.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:24,790 INFO L158 Benchmark]: CACSL2BoogieTranslator took 213.28ms. Allocated memory is still 167.8MB. Free memory was 130.8MB in the beginning and 116.3MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-02-06 19:52:24,790 INFO L158 Benchmark]: Boogie Procedure Inliner took 25.64ms. Allocated memory is still 167.8MB. Free memory was 116.3MB in the beginning and 114.4MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:24,791 INFO L158 Benchmark]: Boogie Preprocessor took 20.30ms. Allocated memory is still 167.8MB. Free memory was 114.4MB in the beginning and 112.6MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:24,791 INFO L158 Benchmark]: IcfgBuilder took 426.41ms. Allocated memory is still 167.8MB. Free memory was 112.6MB in the beginning and 87.3MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-02-06 19:52:24,791 INFO L158 Benchmark]: BuchiAutomizer took 4612.97ms. Allocated memory was 167.8MB in the beginning and 260.0MB in the end (delta: 92.3MB). Free memory was 87.3MB in the beginning and 119.8MB in the end (delta: -32.4MB). Peak memory consumption was 61.3MB. Max. memory is 16.1GB. [2025-02-06 19:52:24,791 INFO L158 Benchmark]: Witness Printer took 55.61ms. Allocated memory is still 260.0MB. Free memory was 119.8MB in the beginning and 113.0MB in the end (delta: 6.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:52:24,792 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15ms. Allocated memory is still 209.7MB. Free memory is still 133.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 213.28ms. Allocated memory is still 167.8MB. Free memory was 130.8MB in the beginning and 116.3MB in the end (delta: 14.5MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 25.64ms. Allocated memory is still 167.8MB. Free memory was 116.3MB in the beginning and 114.4MB in the end (delta: 1.9MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 20.30ms. Allocated memory is still 167.8MB. Free memory was 114.4MB in the beginning and 112.6MB in the end (delta: 1.8MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 426.41ms. Allocated memory is still 167.8MB. Free memory was 112.6MB in the beginning and 87.3MB in the end (delta: 25.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 4612.97ms. Allocated memory was 167.8MB in the beginning and 260.0MB in the end (delta: 92.3MB). Free memory was 87.3MB in the beginning and 119.8MB in the end (delta: -32.4MB). Peak memory consumption was 61.3MB. Max. memory is 16.1GB. * Witness Printer took 55.61ms. Allocated memory is still 260.0MB. Free memory was 119.8MB in the beginning and 113.0MB in the end (delta: 6.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 17 terminating modules (17 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.17 modules have a trivial ranking function, the largest among these consists of 4 locations. The remainder module has 9558 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.5s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 2.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.6s. Highest rank in rank-based complementation 0. Minimization of det autom 17. Minimization of nondet autom 0. Automata minimization 0.8s AutomataMinimizationTime, 17 MinimizatonAttempts, 426 StatesRemovedByMinimization, 9 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 4392 SdHoareTripleChecker+Valid, 0.5s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 4392 mSDsluCounter, 6386 SdHoareTripleChecker+Invalid, 0.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2228 mSDsCounter, 135 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 415 IncrementalHoareTripleChecker+Invalid, 550 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 135 mSolverCounterUnsat, 4158 mSDtfsCounter, 415 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI2 SFLT0 conc3 concLT0 SILN0 SILU0 SILI12 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 294]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L28] int c ; [L29] int c_t ; [L30] int c_req_up ; [L31] int p_in ; [L32] int p_out ; [L33] int wl_st ; [L34] int c1_st ; [L35] int c2_st ; [L36] int wb_st ; [L37] int r_st ; [L38] int wl_i ; [L39] int c1_i ; [L40] int c2_i ; [L41] int wb_i ; [L42] int r_i ; [L43] int wl_pc ; [L44] int c1_pc ; [L45] int c2_pc ; [L46] int wb_pc ; [L47] int e_e ; [L48] int e_f ; [L49] int e_g ; [L50] int e_c ; [L51] int e_p_in ; [L52] int e_wl ; [L58] int d ; [L59] int data ; [L60] int processed ; [L61] static int t_b ; VAL [c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L689] int __retres1 ; [L693] e_wl = 2 [L694] e_c = e_wl [L695] e_g = e_c [L696] e_f = e_g [L697] e_e = e_f [L698] wl_pc = 0 [L699] c1_pc = 0 [L700] c2_pc = 0 [L701] wb_pc = 0 [L702] wb_i = 1 [L703] c2_i = wb_i [L704] c1_i = c2_i [L705] wl_i = c1_i [L706] r_i = 0 [L707] c_req_up = 0 [L708] d = 0 [L709] c = 0 [L710] CALL start_simulation() [L400] int kernel_st ; [L403] kernel_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L404] COND FALSE !((int )c_req_up == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )wl_i == 1 [L416] wl_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )c1_i == 1 [L421] c1_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND TRUE (int )c2_i == 1 [L426] c2_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND TRUE (int )wb_i == 1 [L431] wb_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )r_i == 1) [L438] r_st = 2 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_f == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_g == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_e == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )e_c == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L460] COND FALSE !((int )e_wl == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L465] COND FALSE !((int )wl_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )wl_pc == 2) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L483] COND FALSE !((int )c1_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L492] COND FALSE !((int )c2_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L501] COND FALSE !((int )wb_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_e == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_f == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_g == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L530] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] COND FALSE !((int )e_wl == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L541] COND TRUE 1 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L544] kernel_st = 1 [L545] CALL eval() [L286] int tmp ; [L287] int tmp___0 ; [L288] int tmp___1 ; [L289] int tmp___2 ; [L290] int tmp___3 ; VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] Loop: [L294] COND TRUE 1 [L296] COND TRUE (int )wl_st == 0 [L317] COND TRUE (int )wl_st == 0 [L319] tmp = __VERIFIER_nondet_int() [L321] COND FALSE !(\read(tmp)) [L332] COND TRUE (int )c1_st == 0 [L334] tmp___0 = __VERIFIER_nondet_int() [L336] COND FALSE !(\read(tmp___0)) [L347] COND TRUE (int )c2_st == 0 [L349] tmp___1 = __VERIFIER_nondet_int() [L351] COND FALSE !(\read(tmp___1)) [L362] COND TRUE (int )wb_st == 0 [L364] tmp___2 = __VERIFIER_nondet_int() [L366] COND FALSE !(\read(tmp___2)) [L377] COND FALSE !((int )r_st == 0) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 294]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L28] int c ; [L29] int c_t ; [L30] int c_req_up ; [L31] int p_in ; [L32] int p_out ; [L33] int wl_st ; [L34] int c1_st ; [L35] int c2_st ; [L36] int wb_st ; [L37] int r_st ; [L38] int wl_i ; [L39] int c1_i ; [L40] int c2_i ; [L41] int wb_i ; [L42] int r_i ; [L43] int wl_pc ; [L44] int c1_pc ; [L45] int c2_pc ; [L46] int wb_pc ; [L47] int e_e ; [L48] int e_f ; [L49] int e_g ; [L50] int e_c ; [L51] int e_p_in ; [L52] int e_wl ; [L58] int d ; [L59] int data ; [L60] int processed ; [L61] static int t_b ; VAL [c1_i=0, c1_pc=0, c1_st=0, c2_i=0, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=0, e_e=0, e_f=0, e_g=0, e_p_in=0, e_wl=0, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=0, wb_pc=0, wb_st=0, wl_i=0, wl_pc=0, wl_st=0] [L689] int __retres1 ; [L693] e_wl = 2 [L694] e_c = e_wl [L695] e_g = e_c [L696] e_f = e_g [L697] e_e = e_f [L698] wl_pc = 0 [L699] c1_pc = 0 [L700] c2_pc = 0 [L701] wb_pc = 0 [L702] wb_i = 1 [L703] c2_i = wb_i [L704] c1_i = c2_i [L705] wl_i = c1_i [L706] r_i = 0 [L707] c_req_up = 0 [L708] d = 0 [L709] c = 0 [L710] CALL start_simulation() [L400] int kernel_st ; [L403] kernel_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L404] COND FALSE !((int )c_req_up == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L415] COND TRUE (int )wl_i == 1 [L416] wl_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L420] COND TRUE (int )c1_i == 1 [L421] c1_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L425] COND TRUE (int )c2_i == 1 [L426] c2_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L430] COND TRUE (int )wb_i == 1 [L431] wb_st = 0 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=0, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L435] COND FALSE !((int )r_i == 1) [L438] r_st = 2 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L440] COND FALSE !((int )e_f == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L445] COND FALSE !((int )e_g == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L450] COND FALSE !((int )e_e == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L455] COND FALSE !((int )e_c == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L460] COND FALSE !((int )e_wl == 0) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L465] COND FALSE !((int )wl_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L473] COND FALSE !((int )wl_pc == 2) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L483] COND FALSE !((int )c1_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L492] COND FALSE !((int )c2_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L501] COND FALSE !((int )wb_pc == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L510] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L515] COND FALSE !((int )e_e == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L520] COND FALSE !((int )e_f == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L525] COND FALSE !((int )e_g == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L530] COND FALSE !((int )e_c == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L535] COND FALSE !((int )e_wl == 1) VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L541] COND TRUE 1 VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] [L544] kernel_st = 1 [L545] CALL eval() [L286] int tmp ; [L287] int tmp___0 ; [L288] int tmp___1 ; [L289] int tmp___2 ; [L290] int tmp___3 ; VAL [c1_i=1, c1_pc=0, c1_st=0, c2_i=1, c2_pc=0, c2_st=0, c=0, c_req_up=0, c_t=0, d=0, data=0, e_c=2, e_e=2, e_f=2, e_g=2, e_p_in=0, e_wl=2, p_in=0, p_out=0, processed=0, r_i=0, r_st=2, t_b=0, wb_i=1, wb_pc=0, wb_st=0, wl_i=1, wl_pc=0, wl_st=0] Loop: [L294] COND TRUE 1 [L296] COND TRUE (int )wl_st == 0 [L317] COND TRUE (int )wl_st == 0 [L319] tmp = __VERIFIER_nondet_int() [L321] COND FALSE !(\read(tmp)) [L332] COND TRUE (int )c1_st == 0 [L334] tmp___0 = __VERIFIER_nondet_int() [L336] COND FALSE !(\read(tmp___0)) [L347] COND TRUE (int )c2_st == 0 [L349] tmp___1 = __VERIFIER_nondet_int() [L351] COND FALSE !(\read(tmp___1)) [L362] COND TRUE (int )wb_st == 0 [L364] tmp___2 = __VERIFIER_nondet_int() [L366] COND FALSE !(\read(tmp___2)) [L377] COND FALSE !((int )r_st == 0) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:52:24,813 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)