./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 19:52:18,322 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 19:52:18,363 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 19:52:18,367 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 19:52:18,368 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 19:52:18,368 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 19:52:18,382 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 19:52:18,383 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 19:52:18,383 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 19:52:18,383 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 19:52:18,383 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 19:52:18,383 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 19:52:18,383 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 19:52:18,383 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 19:52:18,384 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 19:52:18,384 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 19:52:18,384 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 19:52:18,385 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 19:52:18,385 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 19:52:18,386 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 19:52:18,386 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 19:52:18,386 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 19:52:18,386 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 19:52:18,386 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2025-02-06 19:52:18,552 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 19:52:18,557 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 19:52:18,559 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 19:52:18,559 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 19:52:18,559 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 19:52:18,560 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-02-06 19:52:19,771 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/be410ff65/4383de3ef9a54be9bd03d692d237b267/FLAG1a2eb44a9 [2025-02-06 19:52:20,057 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 19:52:20,060 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.01.cil.c [2025-02-06 19:52:20,071 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/be410ff65/4383de3ef9a54be9bd03d692d237b267/FLAG1a2eb44a9 [2025-02-06 19:52:20,086 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/be410ff65/4383de3ef9a54be9bd03d692d237b267 [2025-02-06 19:52:20,088 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 19:52:20,089 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 19:52:20,090 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 19:52:20,090 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 19:52:20,093 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 19:52:20,094 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,095 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6c07243e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20, skipping insertion in model container [2025-02-06 19:52:20,096 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,111 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 19:52:20,242 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:52:20,256 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 19:52:20,281 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 19:52:20,298 INFO L204 MainTranslator]: Completed translation [2025-02-06 19:52:20,299 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20 WrapperNode [2025-02-06 19:52:20,299 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 19:52:20,299 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 19:52:20,300 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 19:52:20,300 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 19:52:20,303 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,312 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,332 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 346 [2025-02-06 19:52:20,336 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 19:52:20,336 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 19:52:20,336 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 19:52:20,336 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 19:52:20,341 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,342 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,343 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,360 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-02-06 19:52:20,360 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,360 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,366 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,367 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,368 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,369 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,370 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 19:52:20,375 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 19:52:20,375 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 19:52:20,375 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 19:52:20,376 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (1/1) ... [2025-02-06 19:52:20,380 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 19:52:20,389 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 19:52:20,405 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 19:52:20,416 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 19:52:20,434 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 19:52:20,434 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 19:52:20,434 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 19:52:20,435 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 19:52:20,489 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 19:52:20,490 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 19:52:20,771 INFO L? ?]: Removed 60 outVars from TransFormulas that were not future-live. [2025-02-06 19:52:20,771 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 19:52:20,784 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 19:52:20,785 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-06 19:52:20,786 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20 BoogieIcfgContainer [2025-02-06 19:52:20,786 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 19:52:20,786 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 19:52:20,786 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 19:52:20,790 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 19:52:20,791 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,791 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 07:52:20" (1/3) ... [2025-02-06 19:52:20,792 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c9a6c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:52:20, skipping insertion in model container [2025-02-06 19:52:20,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,792 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 07:52:20" (2/3) ... [2025-02-06 19:52:20,792 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3c9a6c7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 07:52:20, skipping insertion in model container [2025-02-06 19:52:20,792 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 19:52:20,792 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20" (3/3) ... [2025-02-06 19:52:20,793 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2025-02-06 19:52:20,833 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 19:52:20,833 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 19:52:20,833 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 19:52:20,833 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 19:52:20,833 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 19:52:20,833 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 19:52:20,833 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 19:52:20,837 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 19:52:20,846 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 140 states, 139 states have (on average 1.460431654676259) internal successors, (203), 139 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,875 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2025-02-06 19:52:20,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,879 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 19:52:20,880 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 140 states, 139 states have (on average 1.460431654676259) internal successors, (203), 139 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:20,883 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 107 [2025-02-06 19:52:20,883 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:20,883 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:20,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,884 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:20,889 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:20,889 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:20,893 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:20,893 INFO L85 PathProgramCache]: Analyzing trace with hash -705338932, now seen corresponding path program 1 times [2025-02-06 19:52:20,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:20,898 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1521035972] [2025-02-06 19:52:20,898 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:20,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:20,948 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:20,957 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:20,957 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:20,957 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,011 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1521035972] [2025-02-06 19:52:21,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1521035972] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,012 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,012 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1699491308] [2025-02-06 19:52:21,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,016 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,017 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,017 INFO L85 PathProgramCache]: Analyzing trace with hash -1979412185, now seen corresponding path program 1 times [2025-02-06 19:52:21,017 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,017 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1668849943] [2025-02-06 19:52:21,018 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,018 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,025 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-02-06 19:52:21,026 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-02-06 19:52:21,026 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,026 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1668849943] [2025-02-06 19:52:21,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1668849943] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:21,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786055457] [2025-02-06 19:52:21,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,036 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,053 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:21,054 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:21,057 INFO L87 Difference]: Start difference. First operand has 140 states, 139 states have (on average 1.460431654676259) internal successors, (203), 139 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,078 INFO L93 Difference]: Finished difference Result 137 states and 193 transitions. [2025-02-06 19:52:21,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 137 states and 193 transitions. [2025-02-06 19:52:21,083 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2025-02-06 19:52:21,088 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 137 states to 131 states and 187 transitions. [2025-02-06 19:52:21,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 131 [2025-02-06 19:52:21,090 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 131 [2025-02-06 19:52:21,090 INFO L73 IsDeterministic]: Start isDeterministic. Operand 131 states and 187 transitions. [2025-02-06 19:52:21,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 131 states and 187 transitions. [2025-02-06 19:52:21,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states and 187 transitions. [2025-02-06 19:52:21,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2025-02-06 19:52:21,110 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 131 states, 131 states have (on average 1.4274809160305344) internal successors, (187), 130 states have internal predecessors, (187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,111 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 187 transitions. [2025-02-06 19:52:21,112 INFO L240 hiAutomatonCegarLoop]: Abstraction has 131 states and 187 transitions. [2025-02-06 19:52:21,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:21,119 INFO L432 stractBuchiCegarLoop]: Abstraction has 131 states and 187 transitions. [2025-02-06 19:52:21,119 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 19:52:21,119 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131 states and 187 transitions. [2025-02-06 19:52:21,120 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2025-02-06 19:52:21,120 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,121 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,121 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,121 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,122 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,123 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,123 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,123 INFO L85 PathProgramCache]: Analyzing trace with hash -1950103413, now seen corresponding path program 1 times [2025-02-06 19:52:21,124 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,124 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257315887] [2025-02-06 19:52:21,124 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,124 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,129 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,132 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,132 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,132 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [257315887] [2025-02-06 19:52:21,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [257315887] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,160 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,160 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1290356488] [2025-02-06 19:52:21,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,161 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,161 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1432488311, now seen corresponding path program 1 times [2025-02-06 19:52:21,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,162 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344885050] [2025-02-06 19:52:21,162 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,162 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,168 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,175 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,176 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344885050] [2025-02-06 19:52:21,229 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344885050] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [412103823] [2025-02-06 19:52:21,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,229 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,229 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:21,229 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:21,230 INFO L87 Difference]: Start difference. First operand 131 states and 187 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,243 INFO L93 Difference]: Finished difference Result 131 states and 186 transitions. [2025-02-06 19:52:21,243 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 131 states and 186 transitions. [2025-02-06 19:52:21,249 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2025-02-06 19:52:21,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 131 states to 131 states and 186 transitions. [2025-02-06 19:52:21,250 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 131 [2025-02-06 19:52:21,250 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 131 [2025-02-06 19:52:21,250 INFO L73 IsDeterministic]: Start isDeterministic. Operand 131 states and 186 transitions. [2025-02-06 19:52:21,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 131 states and 186 transitions. [2025-02-06 19:52:21,251 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 131 states and 186 transitions. [2025-02-06 19:52:21,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 131 to 131. [2025-02-06 19:52:21,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 131 states, 131 states have (on average 1.4198473282442747) internal successors, (186), 130 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 186 transitions. [2025-02-06 19:52:21,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 131 states and 186 transitions. [2025-02-06 19:52:21,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:21,261 INFO L432 stractBuchiCegarLoop]: Abstraction has 131 states and 186 transitions. [2025-02-06 19:52:21,261 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 19:52:21,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 131 states and 186 transitions. [2025-02-06 19:52:21,262 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 102 [2025-02-06 19:52:21,262 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,262 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,263 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,263 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,266 INFO L85 PathProgramCache]: Analyzing trace with hash 87952876, now seen corresponding path program 1 times [2025-02-06 19:52:21,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745782301] [2025-02-06 19:52:21,267 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,274 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,280 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,280 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,307 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745782301] [2025-02-06 19:52:21,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745782301] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:21,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2022704609] [2025-02-06 19:52:21,307 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,307 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,308 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,308 INFO L85 PathProgramCache]: Analyzing trace with hash 1432488311, now seen corresponding path program 2 times [2025-02-06 19:52:21,308 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,308 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [902126668] [2025-02-06 19:52:21,308 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:21,308 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,316 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,320 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,321 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:21,321 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [902126668] [2025-02-06 19:52:21,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [902126668] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1957177068] [2025-02-06 19:52:21,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,364 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,364 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,364 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:21,365 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:21,365 INFO L87 Difference]: Start difference. First operand 131 states and 186 transitions. cyclomatic complexity: 56 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,404 INFO L93 Difference]: Finished difference Result 226 states and 314 transitions. [2025-02-06 19:52:21,405 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 226 states and 314 transitions. [2025-02-06 19:52:21,407 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 197 [2025-02-06 19:52:21,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 226 states to 226 states and 314 transitions. [2025-02-06 19:52:21,410 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 226 [2025-02-06 19:52:21,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 226 [2025-02-06 19:52:21,410 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226 states and 314 transitions. [2025-02-06 19:52:21,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 226 states and 314 transitions. [2025-02-06 19:52:21,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states and 314 transitions. [2025-02-06 19:52:21,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 211. [2025-02-06 19:52:21,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 211 states, 211 states have (on average 1.3981042654028435) internal successors, (295), 210 states have internal predecessors, (295), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 295 transitions. [2025-02-06 19:52:21,421 INFO L240 hiAutomatonCegarLoop]: Abstraction has 211 states and 295 transitions. [2025-02-06 19:52:21,422 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:21,422 INFO L432 stractBuchiCegarLoop]: Abstraction has 211 states and 295 transitions. [2025-02-06 19:52:21,423 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 19:52:21,423 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 211 states and 295 transitions. [2025-02-06 19:52:21,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 182 [2025-02-06 19:52:21,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,425 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,425 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,425 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,426 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,427 INFO L85 PathProgramCache]: Analyzing trace with hash 857282377, now seen corresponding path program 1 times [2025-02-06 19:52:21,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,427 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [806678346] [2025-02-06 19:52:21,427 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,456 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,466 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,466 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,466 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [806678346] [2025-02-06 19:52:21,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [806678346] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1473438062] [2025-02-06 19:52:21,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,512 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,513 INFO L85 PathProgramCache]: Analyzing trace with hash 1088732913, now seen corresponding path program 1 times [2025-02-06 19:52:21,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [967432188] [2025-02-06 19:52:21,513 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,518 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,523 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,523 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,523 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,552 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [967432188] [2025-02-06 19:52:21,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [967432188] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1336797490] [2025-02-06 19:52:21,552 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,552 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,552 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,552 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,552 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,553 INFO L87 Difference]: Start difference. First operand 211 states and 295 transitions. cyclomatic complexity: 86 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,626 INFO L93 Difference]: Finished difference Result 472 states and 647 transitions. [2025-02-06 19:52:21,626 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 472 states and 647 transitions. [2025-02-06 19:52:21,629 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 419 [2025-02-06 19:52:21,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 472 states to 472 states and 647 transitions. [2025-02-06 19:52:21,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 472 [2025-02-06 19:52:21,632 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 472 [2025-02-06 19:52:21,632 INFO L73 IsDeterministic]: Start isDeterministic. Operand 472 states and 647 transitions. [2025-02-06 19:52:21,633 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,633 INFO L218 hiAutomatonCegarLoop]: Abstraction has 472 states and 647 transitions. [2025-02-06 19:52:21,633 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states and 647 transitions. [2025-02-06 19:52:21,640 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 376. [2025-02-06 19:52:21,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 376 states, 376 states have (on average 1.3829787234042554) internal successors, (520), 375 states have internal predecessors, (520), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 376 states to 376 states and 520 transitions. [2025-02-06 19:52:21,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 376 states and 520 transitions. [2025-02-06 19:52:21,642 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:21,642 INFO L432 stractBuchiCegarLoop]: Abstraction has 376 states and 520 transitions. [2025-02-06 19:52:21,642 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 19:52:21,642 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 376 states and 520 transitions. [2025-02-06 19:52:21,643 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 347 [2025-02-06 19:52:21,643 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,644 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,644 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,644 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,644 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,645 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,645 INFO L85 PathProgramCache]: Analyzing trace with hash -19289498, now seen corresponding path program 1 times [2025-02-06 19:52:21,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [629223660] [2025-02-06 19:52:21,645 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,649 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,650 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,650 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,650 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,684 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,684 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,684 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [629223660] [2025-02-06 19:52:21,684 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [629223660] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,684 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,684 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:52:21,684 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1601903616] [2025-02-06 19:52:21,684 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,684 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,684 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,685 INFO L85 PathProgramCache]: Analyzing trace with hash 1088732913, now seen corresponding path program 2 times [2025-02-06 19:52:21,685 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,685 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1460774596] [2025-02-06 19:52:21,685 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:21,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,691 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,693 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,693 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:21,693 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,708 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,709 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,709 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1460774596] [2025-02-06 19:52:21,709 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1460774596] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,709 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,709 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,709 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [242140196] [2025-02-06 19:52:21,709 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,709 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,709 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:52:21,709 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:52:21,710 INFO L87 Difference]: Start difference. First operand 376 states and 520 transitions. cyclomatic complexity: 146 Second operand has 5 states, 5 states have (on average 5.4) internal successors, (27), 5 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,788 INFO L93 Difference]: Finished difference Result 391 states and 529 transitions. [2025-02-06 19:52:21,788 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 391 states and 529 transitions. [2025-02-06 19:52:21,790 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2025-02-06 19:52:21,793 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 391 states to 391 states and 529 transitions. [2025-02-06 19:52:21,793 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 391 [2025-02-06 19:52:21,793 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 391 [2025-02-06 19:52:21,793 INFO L73 IsDeterministic]: Start isDeterministic. Operand 391 states and 529 transitions. [2025-02-06 19:52:21,794 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,794 INFO L218 hiAutomatonCegarLoop]: Abstraction has 391 states and 529 transitions. [2025-02-06 19:52:21,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391 states and 529 transitions. [2025-02-06 19:52:21,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391 to 391. [2025-02-06 19:52:21,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 391 states, 391 states have (on average 1.3529411764705883) internal successors, (529), 390 states have internal predecessors, (529), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 391 states to 391 states and 529 transitions. [2025-02-06 19:52:21,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 391 states and 529 transitions. [2025-02-06 19:52:21,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:21,809 INFO L432 stractBuchiCegarLoop]: Abstraction has 391 states and 529 transitions. [2025-02-06 19:52:21,809 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 19:52:21,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 391 states and 529 transitions. [2025-02-06 19:52:21,810 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 362 [2025-02-06 19:52:21,810 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,810 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,811 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,811 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,812 INFO L85 PathProgramCache]: Analyzing trace with hash 9339653, now seen corresponding path program 1 times [2025-02-06 19:52:21,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [979178549] [2025-02-06 19:52:21,812 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,815 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,817 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,818 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,818 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:21,818 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:21,819 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,821 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,821 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,821 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:21,833 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:21,833 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,833 INFO L85 PathProgramCache]: Analyzing trace with hash 91660560, now seen corresponding path program 1 times [2025-02-06 19:52:21,834 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,834 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [391351123] [2025-02-06 19:52:21,834 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,834 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,838 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,839 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,840 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,853 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [391351123] [2025-02-06 19:52:21,853 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [391351123] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107587058] [2025-02-06 19:52:21,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,853 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,853 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,854 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:21,854 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:21,854 INFO L87 Difference]: Start difference. First operand 391 states and 529 transitions. cyclomatic complexity: 140 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,869 INFO L93 Difference]: Finished difference Result 481 states and 644 transitions. [2025-02-06 19:52:21,869 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 481 states and 644 transitions. [2025-02-06 19:52:21,872 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 436 [2025-02-06 19:52:21,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 481 states to 481 states and 644 transitions. [2025-02-06 19:52:21,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 481 [2025-02-06 19:52:21,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 481 [2025-02-06 19:52:21,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 481 states and 644 transitions. [2025-02-06 19:52:21,875 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:21,875 INFO L218 hiAutomatonCegarLoop]: Abstraction has 481 states and 644 transitions. [2025-02-06 19:52:21,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states and 644 transitions. [2025-02-06 19:52:21,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 481. [2025-02-06 19:52:21,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 481 states, 481 states have (on average 1.338877338877339) internal successors, (644), 480 states have internal predecessors, (644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 481 states to 481 states and 644 transitions. [2025-02-06 19:52:21,881 INFO L240 hiAutomatonCegarLoop]: Abstraction has 481 states and 644 transitions. [2025-02-06 19:52:21,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:21,882 INFO L432 stractBuchiCegarLoop]: Abstraction has 481 states and 644 transitions. [2025-02-06 19:52:21,882 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 19:52:21,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 481 states and 644 transitions. [2025-02-06 19:52:21,884 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 436 [2025-02-06 19:52:21,884 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:21,884 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:21,884 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,885 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:21,885 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:21,885 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:21,885 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,885 INFO L85 PathProgramCache]: Analyzing trace with hash 853810563, now seen corresponding path program 1 times [2025-02-06 19:52:21,885 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,886 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54057233] [2025-02-06 19:52:21,886 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,886 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,889 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:21,890 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:21,890 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54057233] [2025-02-06 19:52:21,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54057233] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,910 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,910 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:21,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2001134772] [2025-02-06 19:52:21,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,910 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:21,910 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:21,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1415891249, now seen corresponding path program 1 times [2025-02-06 19:52:21,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:21,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [421796874] [2025-02-06 19:52:21,911 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:21,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:21,914 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:21,916 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:21,916 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:21,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:21,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:21,944 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:21,944 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [421796874] [2025-02-06 19:52:21,944 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [421796874] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:21,944 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:21,944 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:52:21,944 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1827348096] [2025-02-06 19:52:21,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:21,944 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:21,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:21,945 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 19:52:21,945 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 19:52:21,945 INFO L87 Difference]: Start difference. First operand 481 states and 644 transitions. cyclomatic complexity: 165 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:21,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:21,995 INFO L93 Difference]: Finished difference Result 680 states and 911 transitions. [2025-02-06 19:52:21,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 680 states and 911 transitions. [2025-02-06 19:52:21,998 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 646 [2025-02-06 19:52:22,001 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 680 states to 680 states and 911 transitions. [2025-02-06 19:52:22,001 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 680 [2025-02-06 19:52:22,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 680 [2025-02-06 19:52:22,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 680 states and 911 transitions. [2025-02-06 19:52:22,003 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,003 INFO L218 hiAutomatonCegarLoop]: Abstraction has 680 states and 911 transitions. [2025-02-06 19:52:22,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 680 states and 911 transitions. [2025-02-06 19:52:22,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 680 to 680. [2025-02-06 19:52:22,029 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 680 states, 680 states have (on average 1.339705882352941) internal successors, (911), 679 states have internal predecessors, (911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 680 states to 680 states and 911 transitions. [2025-02-06 19:52:22,031 INFO L240 hiAutomatonCegarLoop]: Abstraction has 680 states and 911 transitions. [2025-02-06 19:52:22,031 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 19:52:22,032 INFO L432 stractBuchiCegarLoop]: Abstraction has 680 states and 911 transitions. [2025-02-06 19:52:22,032 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 19:52:22,032 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 680 states and 911 transitions. [2025-02-06 19:52:22,034 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 646 [2025-02-06 19:52:22,034 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,035 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,035 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,035 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,035 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:22,036 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:22,036 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,036 INFO L85 PathProgramCache]: Analyzing trace with hash 9309862, now seen corresponding path program 1 times [2025-02-06 19:52:22,036 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,036 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2014584902] [2025-02-06 19:52:22,036 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,036 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,039 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,041 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,041 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,041 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,058 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2014584902] [2025-02-06 19:52:22,058 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2014584902] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,058 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,058 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:22,058 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1285566519] [2025-02-06 19:52:22,058 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,058 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-02-06 19:52:22,058 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,059 INFO L85 PathProgramCache]: Analyzing trace with hash 442460497, now seen corresponding path program 1 times [2025-02-06 19:52:22,059 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,059 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941069349] [2025-02-06 19:52:22,059 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,059 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,062 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:22,065 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:22,065 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,065 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,112 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,113 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,113 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941069349] [2025-02-06 19:52:22,113 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941069349] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,113 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,113 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:52:22,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [638236820] [2025-02-06 19:52:22,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,116 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,116 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,116 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,116 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,117 INFO L87 Difference]: Start difference. First operand 680 states and 911 transitions. cyclomatic complexity: 235 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,144 INFO L93 Difference]: Finished difference Result 977 states and 1295 transitions. [2025-02-06 19:52:22,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 977 states and 1295 transitions. [2025-02-06 19:52:22,149 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 942 [2025-02-06 19:52:22,152 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 977 states to 977 states and 1295 transitions. [2025-02-06 19:52:22,153 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 977 [2025-02-06 19:52:22,153 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 977 [2025-02-06 19:52:22,153 INFO L73 IsDeterministic]: Start isDeterministic. Operand 977 states and 1295 transitions. [2025-02-06 19:52:22,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 977 states and 1295 transitions. [2025-02-06 19:52:22,156 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 977 states and 1295 transitions. [2025-02-06 19:52:22,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 977 to 689. [2025-02-06 19:52:22,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 689 states, 689 states have (on average 1.3309143686502176) internal successors, (917), 688 states have internal predecessors, (917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 689 states to 689 states and 917 transitions. [2025-02-06 19:52:22,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 689 states and 917 transitions. [2025-02-06 19:52:22,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,168 INFO L432 stractBuchiCegarLoop]: Abstraction has 689 states and 917 transitions. [2025-02-06 19:52:22,168 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 19:52:22,168 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 689 states and 917 transitions. [2025-02-06 19:52:22,170 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 658 [2025-02-06 19:52:22,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,171 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,171 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,171 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:22,171 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:22,172 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,172 INFO L85 PathProgramCache]: Analyzing trace with hash 9339653, now seen corresponding path program 2 times [2025-02-06 19:52:22,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764082944] [2025-02-06 19:52:22,172 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:22,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,175 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,177 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,177 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:22,177 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,177 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,178 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,179 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,180 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,180 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,182 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,182 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,183 INFO L85 PathProgramCache]: Analyzing trace with hash -2078177521, now seen corresponding path program 1 times [2025-02-06 19:52:22,183 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,183 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1525017675] [2025-02-06 19:52:22,183 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,183 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,186 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-02-06 19:52:22,188 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-02-06 19:52:22,188 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1525017675] [2025-02-06 19:52:22,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1525017675] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:52:22,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1079104631] [2025-02-06 19:52:22,212 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,213 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,213 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:52:22,213 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:52:22,213 INFO L87 Difference]: Start difference. First operand 689 states and 917 transitions. cyclomatic complexity: 230 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,247 INFO L93 Difference]: Finished difference Result 745 states and 973 transitions. [2025-02-06 19:52:22,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 745 states and 973 transitions. [2025-02-06 19:52:22,251 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 714 [2025-02-06 19:52:22,253 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 745 states to 745 states and 973 transitions. [2025-02-06 19:52:22,254 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 745 [2025-02-06 19:52:22,254 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 745 [2025-02-06 19:52:22,254 INFO L73 IsDeterministic]: Start isDeterministic. Operand 745 states and 973 transitions. [2025-02-06 19:52:22,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 745 states and 973 transitions. [2025-02-06 19:52:22,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 745 states and 973 transitions. [2025-02-06 19:52:22,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 745 to 713. [2025-02-06 19:52:22,263 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 713 states, 713 states have (on average 1.3197755960729314) internal successors, (941), 712 states have internal predecessors, (941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 713 states to 713 states and 941 transitions. [2025-02-06 19:52:22,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 713 states and 941 transitions. [2025-02-06 19:52:22,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:22,266 INFO L432 stractBuchiCegarLoop]: Abstraction has 713 states and 941 transitions. [2025-02-06 19:52:22,266 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 19:52:22,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 713 states and 941 transitions. [2025-02-06 19:52:22,268 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 682 [2025-02-06 19:52:22,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,269 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,269 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,269 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:22,269 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:22,270 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,270 INFO L85 PathProgramCache]: Analyzing trace with hash 9339653, now seen corresponding path program 3 times [2025-02-06 19:52:22,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457712779] [2025-02-06 19:52:22,270 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 19:52:22,270 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,274 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,276 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,276 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 19:52:22,276 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,276 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,277 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,279 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,279 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,282 INFO L85 PathProgramCache]: Analyzing trace with hash 865234777, now seen corresponding path program 1 times [2025-02-06 19:52:22,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412788656] [2025-02-06 19:52:22,282 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,286 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-06 19:52:22,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-06 19:52:22,289 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,289 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1412788656] [2025-02-06 19:52:22,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1412788656] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,321 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-02-06 19:52:22,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942773630] [2025-02-06 19:52:22,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,322 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,322 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,322 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-02-06 19:52:22,322 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-02-06 19:52:22,322 INFO L87 Difference]: Start difference. First operand 713 states and 941 transitions. cyclomatic complexity: 230 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,373 INFO L93 Difference]: Finished difference Result 731 states and 948 transitions. [2025-02-06 19:52:22,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 731 states and 948 transitions. [2025-02-06 19:52:22,376 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 700 [2025-02-06 19:52:22,379 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 731 states to 731 states and 948 transitions. [2025-02-06 19:52:22,379 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 731 [2025-02-06 19:52:22,379 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 731 [2025-02-06 19:52:22,379 INFO L73 IsDeterministic]: Start isDeterministic. Operand 731 states and 948 transitions. [2025-02-06 19:52:22,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 731 states and 948 transitions. [2025-02-06 19:52:22,381 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 731 states and 948 transitions. [2025-02-06 19:52:22,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 731 to 731. [2025-02-06 19:52:22,387 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 731 states, 731 states have (on average 1.2968536251709986) internal successors, (948), 730 states have internal predecessors, (948), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 731 states to 731 states and 948 transitions. [2025-02-06 19:52:22,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 731 states and 948 transitions. [2025-02-06 19:52:22,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-02-06 19:52:22,390 INFO L432 stractBuchiCegarLoop]: Abstraction has 731 states and 948 transitions. [2025-02-06 19:52:22,390 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 19:52:22,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 731 states and 948 transitions. [2025-02-06 19:52:22,392 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 700 [2025-02-06 19:52:22,392 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,393 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" [2025-02-06 19:52:22,393 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~m_st~0);" "assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-02-06 19:52:22,394 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,394 INFO L85 PathProgramCache]: Analyzing trace with hash 9339653, now seen corresponding path program 4 times [2025-02-06 19:52:22,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619726293] [2025-02-06 19:52:22,394 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 19:52:22,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,398 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 27 statements into 2 equivalence classes. [2025-02-06 19:52:22,400 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,400 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 19:52:22,400 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,400 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,401 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-02-06 19:52:22,402 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-02-06 19:52:22,402 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,402 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,405 INFO L85 PathProgramCache]: Analyzing trace with hash 798228024, now seen corresponding path program 1 times [2025-02-06 19:52:22,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917789012] [2025-02-06 19:52:22,405 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,409 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-06 19:52:22,410 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-06 19:52:22,411 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,411 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917789012] [2025-02-06 19:52:22,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917789012] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,423 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,423 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-06 19:52:22,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1737016784] [2025-02-06 19:52:22,423 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,423 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 19:52:22,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,424 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,424 INFO L87 Difference]: Start difference. First operand 731 states and 948 transitions. cyclomatic complexity: 219 Second operand has 3 states, 3 states have (on average 14.333333333333334) internal successors, (43), 3 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,466 INFO L93 Difference]: Finished difference Result 973 states and 1234 transitions. [2025-02-06 19:52:22,466 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 973 states and 1234 transitions. [2025-02-06 19:52:22,470 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 942 [2025-02-06 19:52:22,473 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 973 states to 973 states and 1234 transitions. [2025-02-06 19:52:22,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 973 [2025-02-06 19:52:22,474 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 973 [2025-02-06 19:52:22,474 INFO L73 IsDeterministic]: Start isDeterministic. Operand 973 states and 1234 transitions. [2025-02-06 19:52:22,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 973 states and 1234 transitions. [2025-02-06 19:52:22,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 973 states and 1234 transitions. [2025-02-06 19:52:22,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 973 to 949. [2025-02-06 19:52:22,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 949 states, 949 states have (on average 1.2718651211801897) internal successors, (1207), 948 states have internal predecessors, (1207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 949 states to 949 states and 1207 transitions. [2025-02-06 19:52:22,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 949 states and 1207 transitions. [2025-02-06 19:52:22,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,487 INFO L432 stractBuchiCegarLoop]: Abstraction has 949 states and 1207 transitions. [2025-02-06 19:52:22,487 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 19:52:22,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 949 states and 1207 transitions. [2025-02-06 19:52:22,490 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 918 [2025-02-06 19:52:22,490 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,490 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,491 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-02-06 19:52:22,491 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume !(0 == ~t1_st~0);" [2025-02-06 19:52:22,491 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,491 INFO L85 PathProgramCache]: Analyzing trace with hash 385478692, now seen corresponding path program 1 times [2025-02-06 19:52:22,491 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,491 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [100468319] [2025-02-06 19:52:22,492 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,494 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:22,496 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:22,496 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,496 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,496 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,497 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:22,498 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:22,498 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,498 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,501 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,501 INFO L85 PathProgramCache]: Analyzing trace with hash -951991143, now seen corresponding path program 1 times [2025-02-06 19:52:22,501 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,501 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1160739816] [2025-02-06 19:52:22,501 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,503 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:52:22,504 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:52:22,504 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,504 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,505 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-02-06 19:52:22,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-02-06 19:52:22,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,506 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,507 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,507 INFO L85 PathProgramCache]: Analyzing trace with hash -36428548, now seen corresponding path program 1 times [2025-02-06 19:52:22,507 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,507 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151694828] [2025-02-06 19:52:22,507 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,510 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-02-06 19:52:22,512 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-02-06 19:52:22,512 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,512 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 19:52:22,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 19:52:22,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 19:52:22,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [151694828] [2025-02-06 19:52:22,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [151694828] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 19:52:22,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 19:52:22,527 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 19:52:22,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [596118835] [2025-02-06 19:52:22,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 19:52:22,561 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 19:52:22,562 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-02-06 19:52:22,562 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-02-06 19:52:22,562 INFO L87 Difference]: Start difference. First operand 949 states and 1207 transitions. cyclomatic complexity: 262 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 19:52:22,588 INFO L93 Difference]: Finished difference Result 1515 states and 1900 transitions. [2025-02-06 19:52:22,588 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1515 states and 1900 transitions. [2025-02-06 19:52:22,594 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1483 [2025-02-06 19:52:22,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1515 states to 1515 states and 1900 transitions. [2025-02-06 19:52:22,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1515 [2025-02-06 19:52:22,600 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1515 [2025-02-06 19:52:22,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1515 states and 1900 transitions. [2025-02-06 19:52:22,601 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 19:52:22,601 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1515 states and 1900 transitions. [2025-02-06 19:52:22,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1515 states and 1900 transitions. [2025-02-06 19:52:22,612 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1515 to 1381. [2025-02-06 19:52:22,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1381 states, 1381 states have (on average 1.2657494569152787) internal successors, (1748), 1380 states have internal predecessors, (1748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 19:52:22,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1381 states to 1381 states and 1748 transitions. [2025-02-06 19:52:22,617 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1381 states and 1748 transitions. [2025-02-06 19:52:22,618 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-02-06 19:52:22,618 INFO L432 stractBuchiCegarLoop]: Abstraction has 1381 states and 1748 transitions. [2025-02-06 19:52:22,618 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 19:52:22,618 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1381 states and 1748 transitions. [2025-02-06 19:52:22,622 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 1349 [2025-02-06 19:52:22,622 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 19:52:22,623 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 19:52:22,623 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,623 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 19:52:22,623 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~E_1~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~E_1~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" [2025-02-06 19:52:22,623 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp~0#1;" "assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp_ndt_1~0#1);" "havoc eval_~tmp_ndt_1~0#1;" "assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp_ndt_2~0#1);" "havoc eval_~tmp_ndt_2~0#1;" [2025-02-06 19:52:22,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,624 INFO L85 PathProgramCache]: Analyzing trace with hash 385478692, now seen corresponding path program 2 times [2025-02-06 19:52:22,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097540983] [2025-02-06 19:52:22,624 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 19:52:22,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,627 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:22,629 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:22,629 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 19:52:22,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,629 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,630 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:22,631 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:22,631 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,631 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,634 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,634 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,634 INFO L85 PathProgramCache]: Analyzing trace with hash -35450876, now seen corresponding path program 1 times [2025-02-06 19:52:22,634 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,634 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464364032] [2025-02-06 19:52:22,634 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,634 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,636 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-02-06 19:52:22,637 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-02-06 19:52:22,637 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,637 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,637 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,638 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-02-06 19:52:22,638 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-02-06 19:52:22,639 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,640 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,640 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 19:52:22,640 INFO L85 PathProgramCache]: Analyzing trace with hash -648092761, now seen corresponding path program 1 times [2025-02-06 19:52:22,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 19:52:22,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [429234357] [2025-02-06 19:52:22,640 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 19:52:22,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 19:52:22,643 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:52:22,645 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:52:22,645 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,645 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,645 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:22,646 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-02-06 19:52:22,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-02-06 19:52:22,648 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:22,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:22,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 19:52:22,997 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:23,000 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:23,000 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,000 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,001 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 19:52:23,005 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-02-06 19:52:23,008 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-02-06 19:52:23,008 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 19:52:23,008 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 19:52:23,057 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 06.02 07:52:23 BoogieIcfgContainer [2025-02-06 19:52:23,057 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-02-06 19:52:23,058 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-02-06 19:52:23,058 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-02-06 19:52:23,058 INFO L274 PluginConnector]: Witness Printer initialized [2025-02-06 19:52:23,059 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 07:52:20" (3/4) ... [2025-02-06 19:52:23,060 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-02-06 19:52:23,114 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-02-06 19:52:23,114 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-02-06 19:52:23,115 INFO L158 Benchmark]: Toolchain (without parser) took 3026.22ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 123.5MB in the beginning and 311.6MB in the end (delta: -188.0MB). Peak memory consumption was 8.9MB. Max. memory is 16.1GB. [2025-02-06 19:52:23,115 INFO L158 Benchmark]: CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 118.2MB. There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:23,115 INFO L158 Benchmark]: CACSL2BoogieTranslator took 209.23ms. Allocated memory is still 167.8MB. Free memory was 122.6MB in the beginning and 110.0MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:52:23,115 INFO L158 Benchmark]: Boogie Procedure Inliner took 36.39ms. Allocated memory is still 167.8MB. Free memory was 110.0MB in the beginning and 108.0MB in the end (delta: 2.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-02-06 19:52:23,115 INFO L158 Benchmark]: Boogie Preprocessor took 33.69ms. Allocated memory is still 167.8MB. Free memory was 108.0MB in the beginning and 107.1MB in the end (delta: 908.6kB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:23,116 INFO L158 Benchmark]: IcfgBuilder took 411.22ms. Allocated memory is still 167.8MB. Free memory was 107.1MB in the beginning and 83.7MB in the end (delta: 23.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-02-06 19:52:23,116 INFO L158 Benchmark]: BuchiAutomizer took 2271.03ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 83.7MB in the beginning and 316.2MB in the end (delta: -232.5MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:23,116 INFO L158 Benchmark]: Witness Printer took 56.42ms. Allocated memory is still 369.1MB. Free memory was 316.2MB in the beginning and 311.6MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. [2025-02-06 19:52:23,117 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.18ms. Allocated memory is still 201.3MB. Free memory is still 118.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 209.23ms. Allocated memory is still 167.8MB. Free memory was 122.6MB in the beginning and 110.0MB in the end (delta: 12.6MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 36.39ms. Allocated memory is still 167.8MB. Free memory was 110.0MB in the beginning and 108.0MB in the end (delta: 2.0MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 33.69ms. Allocated memory is still 167.8MB. Free memory was 108.0MB in the beginning and 107.1MB in the end (delta: 908.6kB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 411.22ms. Allocated memory is still 167.8MB. Free memory was 107.1MB in the beginning and 83.7MB in the end (delta: 23.4MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 2271.03ms. Allocated memory was 167.8MB in the beginning and 369.1MB in the end (delta: 201.3MB). Free memory was 83.7MB in the beginning and 316.2MB in the end (delta: -232.5MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 56.42ms. Allocated memory is still 369.1MB. Free memory was 316.2MB in the beginning and 311.6MB in the end (delta: 4.7MB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 1381 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.2s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 1.3s. Construction of modules took 0.2s. Büchi inclusion checks took 0.5s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 12 MinimizatonAttempts, 589 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1609 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1609 mSDsluCounter, 4786 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2593 mSDsCounter, 84 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 342 IncrementalHoareTripleChecker+Invalid, 426 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 84 mSolverCounterUnsat, 2193 mSDtfsCounter, 342 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI4 SFLT0 conc1 concLT0 SILN0 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE !(\read(tmp_ndt_1)) [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE !(\read(tmp_ndt_2)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-02-06 19:52:23,142 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)