./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_nondet_test1-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version c00e63dc Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_nondet_test1-1.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash fdc85b042221b41aa26e62667e19ce1f6c246be9a2cb4f81fe8b15c8429db160 --- Real Ultimate output --- This is Ultimate 0.3.0-?-c00e63d-m [2025-02-06 20:13:53,872 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-06 20:13:53,930 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-06 20:13:53,935 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-06 20:13:53,936 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-06 20:13:53,936 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-06 20:13:53,956 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-06 20:13:53,957 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-06 20:13:53,958 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-06 20:13:53,958 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-06 20:13:53,958 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-06 20:13:53,958 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * Use SBE=true [2025-02-06 20:13:53,959 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-06 20:13:53,959 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-06 20:13:53,960 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-06 20:13:53,960 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-06 20:13:53,961 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-06 20:13:53,961 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-06 20:13:53,961 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-06 20:13:53,962 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-06 20:13:53,962 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> fdc85b042221b41aa26e62667e19ce1f6c246be9a2cb4f81fe8b15c8429db160 [2025-02-06 20:13:54,199 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-06 20:13:54,208 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-06 20:13:54,211 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-06 20:13:54,212 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-06 20:13:54,212 INFO L274 PluginConnector]: CDTParser initialized [2025-02-06 20:13:54,214 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_OAT_nondet_test1-1.i [2025-02-06 20:13:55,405 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a46912653/211b34c55e6a43728cfc78b7be0362d6/FLAGd0e3dde56 [2025-02-06 20:13:55,715 INFO L384 CDTParser]: Found 1 translation units. [2025-02-06 20:13:55,715 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_OAT_nondet_test1-1.i [2025-02-06 20:13:55,732 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a46912653/211b34c55e6a43728cfc78b7be0362d6/FLAGd0e3dde56 [2025-02-06 20:13:55,749 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/a46912653/211b34c55e6a43728cfc78b7be0362d6 [2025-02-06 20:13:55,758 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-06 20:13:55,760 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-06 20:13:55,761 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-06 20:13:55,761 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-06 20:13:55,764 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-06 20:13:55,765 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 08:13:55" (1/1) ... [2025-02-06 20:13:55,765 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2f7a3495 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:55, skipping insertion in model container [2025-02-06 20:13:55,765 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 06.02 08:13:55" (1/1) ... [2025-02-06 20:13:55,798 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-06 20:13:56,128 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 20:13:56,143 INFO L200 MainTranslator]: Completed pre-run [2025-02-06 20:13:56,208 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-06 20:13:56,231 INFO L204 MainTranslator]: Completed translation [2025-02-06 20:13:56,231 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56 WrapperNode [2025-02-06 20:13:56,232 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-06 20:13:56,232 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-06 20:13:56,232 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-06 20:13:56,232 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-06 20:13:56,237 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,255 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,287 INFO L138 Inliner]: procedures = 176, calls = 170, calls flagged for inlining = 4, calls inlined = 4, statements flattened = 773 [2025-02-06 20:13:56,287 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-06 20:13:56,288 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-06 20:13:56,288 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-06 20:13:56,288 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-06 20:13:56,296 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,297 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,307 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,347 INFO L175 MemorySlicer]: Split 158 memory accesses to 2 slices as follows [2, 156]. 99 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 42 writes are split as follows [0, 42]. [2025-02-06 20:13:56,347 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,348 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,369 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,371 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,374 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,376 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,383 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-06 20:13:56,384 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-06 20:13:56,384 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-06 20:13:56,384 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-06 20:13:56,386 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (1/1) ... [2025-02-06 20:13:56,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-06 20:13:56,399 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-06 20:13:56,411 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-06 20:13:56,417 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-02-06 20:13:56,433 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-02-06 20:13:56,433 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-02-06 20:13:56,433 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-06 20:13:56,433 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-06 20:13:56,548 INFO L257 CfgBuilder]: Building ICFG [2025-02-06 20:13:56,549 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-06 20:13:57,265 INFO L? ?]: Removed 195 outVars from TransFormulas that were not future-live. [2025-02-06 20:13:57,265 INFO L308 CfgBuilder]: Performing block encoding [2025-02-06 20:13:57,308 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-06 20:13:57,309 INFO L337 CfgBuilder]: Removed 1 assume(true) statements. [2025-02-06 20:13:57,309 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 08:13:57 BoogieIcfgContainer [2025-02-06 20:13:57,309 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-06 20:13:57,311 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-06 20:13:57,311 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-06 20:13:57,315 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-06 20:13:57,315 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 20:13:57,315 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 06.02 08:13:55" (1/3) ... [2025-02-06 20:13:57,317 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@210e6848 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 08:13:57, skipping insertion in model container [2025-02-06 20:13:57,317 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 20:13:57,318 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 06.02 08:13:56" (2/3) ... [2025-02-06 20:13:57,318 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@210e6848 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 06.02 08:13:57, skipping insertion in model container [2025-02-06 20:13:57,318 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-06 20:13:57,319 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 06.02 08:13:57" (3/3) ... [2025-02-06 20:13:57,320 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_OAT_nondet_test1-1.i [2025-02-06 20:13:57,360 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-06 20:13:57,360 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-06 20:13:57,360 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-06 20:13:57,360 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-06 20:13:57,360 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-06 20:13:57,360 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-06 20:13:57,360 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-06 20:13:57,360 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-06 20:13:57,365 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 207 states, 202 states have (on average 1.5940594059405941) internal successors, (322), 202 states have internal predecessors, (322), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:13:57,388 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 194 [2025-02-06 20:13:57,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:13:57,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:13:57,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:13:57,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-02-06 20:13:57,393 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-06 20:13:57,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 207 states, 202 states have (on average 1.5940594059405941) internal successors, (322), 202 states have internal predecessors, (322), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:13:57,399 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 194 [2025-02-06 20:13:57,399 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:13:57,399 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:13:57,400 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:13:57,400 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1] [2025-02-06 20:13:57,404 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:13:57,406 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume !true;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:13:57,410 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:57,410 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 1 times [2025-02-06 20:13:57,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:57,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1305402606] [2025-02-06 20:13:57,415 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:13:57,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:57,470 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:57,474 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:57,474 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:57,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:57,475 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:13:57,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:57,486 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:57,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:57,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:57,502 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:13:57,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:57,505 INFO L85 PathProgramCache]: Analyzing trace with hash 363527287, now seen corresponding path program 1 times [2025-02-06 20:13:57,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:57,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830600961] [2025-02-06 20:13:57,505 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:13:57,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:57,515 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-02-06 20:13:57,517 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-02-06 20:13:57,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:57,518 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:13:57,551 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:13:57,551 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:13:57,551 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [830600961] [2025-02-06 20:13:57,552 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [830600961] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:13:57,552 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:13:57,552 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-06 20:13:57,552 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [372255487] [2025-02-06 20:13:57,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:13:57,555 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:13:57,556 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:13:57,580 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-02-06 20:13:57,581 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-02-06 20:13:57,582 INFO L87 Difference]: Start difference. First operand has 207 states, 202 states have (on average 1.5940594059405941) internal successors, (322), 202 states have internal predecessors, (322), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 2.5) internal successors, (5), 2 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:13:57,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:13:57,642 INFO L93 Difference]: Finished difference Result 206 states and 294 transitions. [2025-02-06 20:13:57,643 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 206 states and 294 transitions. [2025-02-06 20:13:57,650 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 194 [2025-02-06 20:13:57,659 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 206 states to 200 states and 288 transitions. [2025-02-06 20:13:57,660 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 200 [2025-02-06 20:13:57,662 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 200 [2025-02-06 20:13:57,664 INFO L73 IsDeterministic]: Start isDeterministic. Operand 200 states and 288 transitions. [2025-02-06 20:13:57,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:13:57,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 200 states and 288 transitions. [2025-02-06 20:13:57,677 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 200 states and 288 transitions. [2025-02-06 20:13:57,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 200 to 200. [2025-02-06 20:13:57,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 200 states, 196 states have (on average 1.4387755102040816) internal successors, (282), 195 states have internal predecessors, (282), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:13:57,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 288 transitions. [2025-02-06 20:13:57,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 200 states and 288 transitions. [2025-02-06 20:13:57,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-02-06 20:13:57,699 INFO L432 stractBuchiCegarLoop]: Abstraction has 200 states and 288 transitions. [2025-02-06 20:13:57,700 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-06 20:13:57,700 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 200 states and 288 transitions. [2025-02-06 20:13:57,701 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 194 [2025-02-06 20:13:57,701 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:13:57,701 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:13:57,703 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:13:57,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:13:57,704 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:13:57,705 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem29#1 := read~int#1(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem29#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem30#1 := read~int#1(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem30#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem31#1 := read~int#1(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem31#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem32#1 := read~int#1(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem32#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem33#1 := read~int#1(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem33#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem34#1 := read~int#1(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem34#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem35#1 := read~int#1(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem35#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem35#1 % 256 % 4294967296 else main_#t~mem35#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:13:57,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:57,708 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 2 times [2025-02-06 20:13:57,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:57,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812994675] [2025-02-06 20:13:57,709 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 20:13:57,709 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:57,717 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:57,720 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:57,721 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:13:57,721 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:57,721 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:13:57,724 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:57,728 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:57,730 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:57,730 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:57,734 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:13:57,734 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:57,734 INFO L85 PathProgramCache]: Analyzing trace with hash 1844331495, now seen corresponding path program 1 times [2025-02-06 20:13:57,734 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:57,734 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1172736789] [2025-02-06 20:13:57,735 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:13:57,735 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:57,771 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-02-06 20:13:57,793 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-02-06 20:13:57,793 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:57,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:13:58,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:13:58,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:13:58,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1172736789] [2025-02-06 20:13:58,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1172736789] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:13:58,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:13:58,115 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 20:13:58,115 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [775193125] [2025-02-06 20:13:58,115 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:13:58,116 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:13:58,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:13:58,118 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 20:13:58,118 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 20:13:58,118 INFO L87 Difference]: Start difference. First operand 200 states and 288 transitions. cyclomatic complexity: 91 Second operand has 4 states, 4 states have (on average 18.5) internal successors, (74), 4 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:13:58,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:13:58,246 INFO L93 Difference]: Finished difference Result 203 states and 284 transitions. [2025-02-06 20:13:58,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 203 states and 284 transitions. [2025-02-06 20:13:58,247 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 197 [2025-02-06 20:13:58,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 203 states to 203 states and 284 transitions. [2025-02-06 20:13:58,249 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 203 [2025-02-06 20:13:58,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 203 [2025-02-06 20:13:58,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 203 states and 284 transitions. [2025-02-06 20:13:58,251 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:13:58,251 INFO L218 hiAutomatonCegarLoop]: Abstraction has 203 states and 284 transitions. [2025-02-06 20:13:58,254 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 203 states and 284 transitions. [2025-02-06 20:13:58,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 203 to 200. [2025-02-06 20:13:58,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 200 states, 196 states have (on average 1.403061224489796) internal successors, (275), 195 states have internal predecessors, (275), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:13:58,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 200 states to 200 states and 281 transitions. [2025-02-06 20:13:58,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 200 states and 281 transitions. [2025-02-06 20:13:58,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 20:13:58,263 INFO L432 stractBuchiCegarLoop]: Abstraction has 200 states and 281 transitions. [2025-02-06 20:13:58,263 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-06 20:13:58,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 200 states and 281 transitions. [2025-02-06 20:13:58,264 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 194 [2025-02-06 20:13:58,264 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:13:58,264 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:13:58,265 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:13:58,265 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:13:58,265 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:13:58,265 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:13:58,267 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:58,267 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 3 times [2025-02-06 20:13:58,267 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:58,267 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250019215] [2025-02-06 20:13:58,267 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 20:13:58,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:58,275 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:58,276 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:58,276 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 20:13:58,276 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:58,276 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:13:58,278 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:58,279 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:58,279 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:58,279 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:58,283 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:13:58,283 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:58,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1525512338, now seen corresponding path program 1 times [2025-02-06 20:13:58,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:58,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333186778] [2025-02-06 20:13:58,284 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:13:58,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:58,314 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 74 statements into 1 equivalence classes. [2025-02-06 20:13:58,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 74 of 74 statements. [2025-02-06 20:13:58,514 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:58,515 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:13:58,931 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:13:58,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:13:58,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333186778] [2025-02-06 20:13:58,932 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333186778] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:13:58,932 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:13:58,932 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-02-06 20:13:58,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1419337515] [2025-02-06 20:13:58,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:13:58,933 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:13:58,933 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:13:58,934 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-02-06 20:13:58,934 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-02-06 20:13:58,934 INFO L87 Difference]: Start difference. First operand 200 states and 281 transitions. cyclomatic complexity: 84 Second operand has 6 states, 6 states have (on average 12.333333333333334) internal successors, (74), 6 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:13:59,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:13:59,550 INFO L93 Difference]: Finished difference Result 234 states and 324 transitions. [2025-02-06 20:13:59,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 234 states and 324 transitions. [2025-02-06 20:13:59,552 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 228 [2025-02-06 20:13:59,554 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 234 states to 234 states and 324 transitions. [2025-02-06 20:13:59,556 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 234 [2025-02-06 20:13:59,556 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 234 [2025-02-06 20:13:59,556 INFO L73 IsDeterministic]: Start isDeterministic. Operand 234 states and 324 transitions. [2025-02-06 20:13:59,557 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:13:59,559 INFO L218 hiAutomatonCegarLoop]: Abstraction has 234 states and 324 transitions. [2025-02-06 20:13:59,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 234 states and 324 transitions. [2025-02-06 20:13:59,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 234 to 229. [2025-02-06 20:13:59,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229 states, 225 states have (on average 1.3822222222222222) internal successors, (311), 224 states have internal predecessors, (311), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:13:59,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 317 transitions. [2025-02-06 20:13:59,568 INFO L240 hiAutomatonCegarLoop]: Abstraction has 229 states and 317 transitions. [2025-02-06 20:13:59,569 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-06 20:13:59,571 INFO L432 stractBuchiCegarLoop]: Abstraction has 229 states and 317 transitions. [2025-02-06 20:13:59,571 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-06 20:13:59,571 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229 states and 317 transitions. [2025-02-06 20:13:59,572 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 223 [2025-02-06 20:13:59,573 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:13:59,573 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:13:59,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:13:59,576 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:13:59,576 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:13:59,576 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise40#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:13:59,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:59,577 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 4 times [2025-02-06 20:13:59,577 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:59,577 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [318411592] [2025-02-06 20:13:59,577 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 20:13:59,577 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:59,586 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 20:13:59,587 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:59,587 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 20:13:59,587 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:59,587 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:13:59,590 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:13:59,591 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:13:59,591 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:59,591 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:13:59,596 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:13:59,597 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:13:59,597 INFO L85 PathProgramCache]: Analyzing trace with hash 589169009, now seen corresponding path program 1 times [2025-02-06 20:13:59,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:13:59,597 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1277651927] [2025-02-06 20:13:59,597 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:13:59,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:13:59,634 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-02-06 20:13:59,807 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-02-06 20:13:59,807 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:13:59,807 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:00,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:00,035 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:00,035 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1277651927] [2025-02-06 20:14:00,035 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1277651927] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:00,035 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:00,035 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-06 20:14:00,035 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673735373] [2025-02-06 20:14:00,036 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:00,036 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:00,036 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:00,036 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-06 20:14:00,036 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-06 20:14:00,036 INFO L87 Difference]: Start difference. First operand 229 states and 317 transitions. cyclomatic complexity: 91 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:00,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:00,262 INFO L93 Difference]: Finished difference Result 238 states and 330 transitions. [2025-02-06 20:14:00,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 238 states and 330 transitions. [2025-02-06 20:14:00,263 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 232 [2025-02-06 20:14:00,265 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 238 states to 238 states and 330 transitions. [2025-02-06 20:14:00,265 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 238 [2025-02-06 20:14:00,265 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 238 [2025-02-06 20:14:00,265 INFO L73 IsDeterministic]: Start isDeterministic. Operand 238 states and 330 transitions. [2025-02-06 20:14:00,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:00,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 238 states and 330 transitions. [2025-02-06 20:14:00,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 238 states and 330 transitions. [2025-02-06 20:14:00,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 238 to 230. [2025-02-06 20:14:00,270 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 230 states, 226 states have (on average 1.3805309734513274) internal successors, (312), 225 states have internal predecessors, (312), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:00,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 318 transitions. [2025-02-06 20:14:00,271 INFO L240 hiAutomatonCegarLoop]: Abstraction has 230 states and 318 transitions. [2025-02-06 20:14:00,271 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-06 20:14:00,272 INFO L432 stractBuchiCegarLoop]: Abstraction has 230 states and 318 transitions. [2025-02-06 20:14:00,272 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-06 20:14:00,272 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 230 states and 318 transitions. [2025-02-06 20:14:00,273 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 224 [2025-02-06 20:14:00,273 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:00,273 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:00,273 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:00,273 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:00,274 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:00,274 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:00,274 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:00,274 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 5 times [2025-02-06 20:14:00,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:00,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [478340156] [2025-02-06 20:14:00,274 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 20:14:00,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:00,283 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:00,284 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:00,284 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:00,284 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:00,284 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:00,285 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:00,286 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:00,286 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:00,286 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:00,289 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:00,290 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:00,290 INFO L85 PathProgramCache]: Analyzing trace with hash -2063359094, now seen corresponding path program 1 times [2025-02-06 20:14:00,290 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:00,290 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477157841] [2025-02-06 20:14:00,290 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:00,290 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:00,320 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-02-06 20:14:00,337 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-02-06 20:14:00,337 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:00,337 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:00,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:00,544 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:00,544 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477157841] [2025-02-06 20:14:00,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477157841] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:00,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:00,545 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 20:14:00,545 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [890488103] [2025-02-06 20:14:00,545 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:00,545 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:00,545 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:00,545 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-06 20:14:00,545 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-06 20:14:00,545 INFO L87 Difference]: Start difference. First operand 230 states and 318 transitions. cyclomatic complexity: 91 Second operand has 7 states, 7 states have (on average 10.714285714285714) internal successors, (75), 7 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:01,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:01,095 INFO L93 Difference]: Finished difference Result 242 states and 335 transitions. [2025-02-06 20:14:01,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 242 states and 335 transitions. [2025-02-06 20:14:01,097 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236 [2025-02-06 20:14:01,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 242 states to 242 states and 335 transitions. [2025-02-06 20:14:01,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 242 [2025-02-06 20:14:01,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 242 [2025-02-06 20:14:01,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 335 transitions. [2025-02-06 20:14:01,099 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:01,099 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 335 transitions. [2025-02-06 20:14:01,099 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 335 transitions. [2025-02-06 20:14:01,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 239. [2025-02-06 20:14:01,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 239 states, 235 states have (on average 1.3829787234042554) internal successors, (325), 234 states have internal predecessors, (325), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:01,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 331 transitions. [2025-02-06 20:14:01,103 INFO L240 hiAutomatonCegarLoop]: Abstraction has 239 states and 331 transitions. [2025-02-06 20:14:01,104 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-06 20:14:01,104 INFO L432 stractBuchiCegarLoop]: Abstraction has 239 states and 331 transitions. [2025-02-06 20:14:01,104 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-06 20:14:01,104 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 239 states and 331 transitions. [2025-02-06 20:14:01,105 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 233 [2025-02-06 20:14:01,105 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:01,105 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:01,106 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:01,106 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:01,106 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:01,106 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:01,107 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:01,107 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 6 times [2025-02-06 20:14:01,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:01,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514487916] [2025-02-06 20:14:01,107 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 20:14:01,107 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:01,111 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:01,112 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:01,112 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 20:14:01,112 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:01,112 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:01,113 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:01,114 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:01,114 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:01,114 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:01,116 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:01,117 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:01,117 INFO L85 PathProgramCache]: Analyzing trace with hash -198398933, now seen corresponding path program 1 times [2025-02-06 20:14:01,117 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:01,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1174891537] [2025-02-06 20:14:01,117 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:01,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:01,154 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-02-06 20:14:01,167 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-02-06 20:14:01,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:01,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:01,354 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:01,354 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:01,354 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1174891537] [2025-02-06 20:14:01,354 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1174891537] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:01,354 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:01,354 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-02-06 20:14:01,354 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1439507940] [2025-02-06 20:14:01,354 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:01,355 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:01,355 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:01,355 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-02-06 20:14:01,355 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-02-06 20:14:01,355 INFO L87 Difference]: Start difference. First operand 239 states and 331 transitions. cyclomatic complexity: 95 Second operand has 6 states, 6 states have (on average 12.666666666666666) internal successors, (76), 6 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:01,740 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:01,740 INFO L93 Difference]: Finished difference Result 242 states and 334 transitions. [2025-02-06 20:14:01,741 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 242 states and 334 transitions. [2025-02-06 20:14:01,742 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236 [2025-02-06 20:14:01,743 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 242 states to 242 states and 334 transitions. [2025-02-06 20:14:01,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 242 [2025-02-06 20:14:01,743 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 242 [2025-02-06 20:14:01,743 INFO L73 IsDeterministic]: Start isDeterministic. Operand 242 states and 334 transitions. [2025-02-06 20:14:01,744 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:01,744 INFO L218 hiAutomatonCegarLoop]: Abstraction has 242 states and 334 transitions. [2025-02-06 20:14:01,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 242 states and 334 transitions. [2025-02-06 20:14:01,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 242 to 242. [2025-02-06 20:14:01,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 242 states, 238 states have (on average 1.3781512605042017) internal successors, (328), 237 states have internal predecessors, (328), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:01,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 334 transitions. [2025-02-06 20:14:01,748 INFO L240 hiAutomatonCegarLoop]: Abstraction has 242 states and 334 transitions. [2025-02-06 20:14:01,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-06 20:14:01,749 INFO L432 stractBuchiCegarLoop]: Abstraction has 242 states and 334 transitions. [2025-02-06 20:14:01,749 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-06 20:14:01,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 242 states and 334 transitions. [2025-02-06 20:14:01,749 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 236 [2025-02-06 20:14:01,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:01,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:01,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:01,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:01,750 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:01,750 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:01,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:01,752 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 7 times [2025-02-06 20:14:01,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:01,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [441005486] [2025-02-06 20:14:01,752 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 20:14:01,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:01,756 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:01,756 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:01,756 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:01,756 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:01,756 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:01,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:01,758 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:01,758 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:01,758 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:01,760 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:01,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:01,761 INFO L85 PathProgramCache]: Analyzing trace with hash 438263623, now seen corresponding path program 1 times [2025-02-06 20:14:01,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:01,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564585498] [2025-02-06 20:14:01,761 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:01,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:01,795 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-02-06 20:14:01,815 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-02-06 20:14:01,816 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:01,816 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:02,089 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:02,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:02,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564585498] [2025-02-06 20:14:02,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564585498] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:02,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:02,090 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-06 20:14:02,090 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715462569] [2025-02-06 20:14:02,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:02,090 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:02,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:02,090 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-06 20:14:02,090 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-02-06 20:14:02,091 INFO L87 Difference]: Start difference. First operand 242 states and 334 transitions. cyclomatic complexity: 95 Second operand has 9 states, 9 states have (on average 8.444444444444445) internal successors, (76), 9 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:02,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:02,831 INFO L93 Difference]: Finished difference Result 256 states and 352 transitions. [2025-02-06 20:14:02,831 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 256 states and 352 transitions. [2025-02-06 20:14:02,832 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 250 [2025-02-06 20:14:02,833 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 256 states to 256 states and 352 transitions. [2025-02-06 20:14:02,834 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 256 [2025-02-06 20:14:02,834 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 256 [2025-02-06 20:14:02,834 INFO L73 IsDeterministic]: Start isDeterministic. Operand 256 states and 352 transitions. [2025-02-06 20:14:02,834 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:02,834 INFO L218 hiAutomatonCegarLoop]: Abstraction has 256 states and 352 transitions. [2025-02-06 20:14:02,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states and 352 transitions. [2025-02-06 20:14:02,843 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 250. [2025-02-06 20:14:02,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 250 states, 246 states have (on average 1.3739837398373984) internal successors, (338), 245 states have internal predecessors, (338), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:02,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 344 transitions. [2025-02-06 20:14:02,845 INFO L240 hiAutomatonCegarLoop]: Abstraction has 250 states and 344 transitions. [2025-02-06 20:14:02,847 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-02-06 20:14:02,848 INFO L432 stractBuchiCegarLoop]: Abstraction has 250 states and 344 transitions. [2025-02-06 20:14:02,848 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-06 20:14:02,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 250 states and 344 transitions. [2025-02-06 20:14:02,849 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 244 [2025-02-06 20:14:02,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:02,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:02,849 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:02,849 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:02,849 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:02,849 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:02,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:02,850 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 8 times [2025-02-06 20:14:02,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:02,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1113494319] [2025-02-06 20:14:02,850 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 20:14:02,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:02,856 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:02,857 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:02,857 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:02,857 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:02,857 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:02,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:02,859 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:02,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:02,859 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:02,862 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:02,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:02,862 INFO L85 PathProgramCache]: Analyzing trace with hash -478957809, now seen corresponding path program 1 times [2025-02-06 20:14:02,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:02,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [240566529] [2025-02-06 20:14:02,862 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:02,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:02,886 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-02-06 20:14:02,936 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-02-06 20:14:02,936 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:02,936 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:03,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:03,139 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:03,139 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [240566529] [2025-02-06 20:14:03,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [240566529] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:03,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:03,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 20:14:03,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425176796] [2025-02-06 20:14:03,140 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:03,140 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:03,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:03,140 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-06 20:14:03,140 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-06 20:14:03,140 INFO L87 Difference]: Start difference. First operand 250 states and 344 transitions. cyclomatic complexity: 97 Second operand has 7 states, 7 states have (on average 11.0) internal successors, (77), 7 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:03,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:03,685 INFO L93 Difference]: Finished difference Result 257 states and 353 transitions. [2025-02-06 20:14:03,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 257 states and 353 transitions. [2025-02-06 20:14:03,686 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 251 [2025-02-06 20:14:03,687 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 257 states to 257 states and 353 transitions. [2025-02-06 20:14:03,687 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 257 [2025-02-06 20:14:03,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 257 [2025-02-06 20:14:03,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 257 states and 353 transitions. [2025-02-06 20:14:03,689 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:03,689 INFO L218 hiAutomatonCegarLoop]: Abstraction has 257 states and 353 transitions. [2025-02-06 20:14:03,690 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states and 353 transitions. [2025-02-06 20:14:03,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 250. [2025-02-06 20:14:03,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 250 states, 246 states have (on average 1.3739837398373984) internal successors, (338), 245 states have internal predecessors, (338), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:03,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 344 transitions. [2025-02-06 20:14:03,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 250 states and 344 transitions. [2025-02-06 20:14:03,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-06 20:14:03,697 INFO L432 stractBuchiCegarLoop]: Abstraction has 250 states and 344 transitions. [2025-02-06 20:14:03,697 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-06 20:14:03,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 250 states and 344 transitions. [2025-02-06 20:14:03,697 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 244 [2025-02-06 20:14:03,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:03,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:03,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:03,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:03,698 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:03,698 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:03,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:03,700 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 9 times [2025-02-06 20:14:03,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:03,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509570055] [2025-02-06 20:14:03,700 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 20:14:03,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:03,704 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:03,705 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:03,705 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 20:14:03,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:03,705 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:03,708 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:03,708 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:03,708 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:03,708 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:03,712 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:03,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:03,712 INFO L85 PathProgramCache]: Analyzing trace with hash -142376320, now seen corresponding path program 1 times [2025-02-06 20:14:03,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:03,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1186657899] [2025-02-06 20:14:03,712 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:03,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:03,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-02-06 20:14:03,845 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-02-06 20:14:03,845 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:03,845 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:04,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:04,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:04,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1186657899] [2025-02-06 20:14:04,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1186657899] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:04,291 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:04,291 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-06 20:14:04,291 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [957309647] [2025-02-06 20:14:04,291 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:04,291 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:04,291 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:04,291 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-06 20:14:04,291 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-02-06 20:14:04,292 INFO L87 Difference]: Start difference. First operand 250 states and 344 transitions. cyclomatic complexity: 97 Second operand has 13 states, 13 states have (on average 5.923076923076923) internal successors, (77), 13 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:05,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:05,535 INFO L93 Difference]: Finished difference Result 348 states and 484 transitions. [2025-02-06 20:14:05,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 348 states and 484 transitions. [2025-02-06 20:14:05,537 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 342 [2025-02-06 20:14:05,540 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 348 states to 348 states and 484 transitions. [2025-02-06 20:14:05,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 348 [2025-02-06 20:14:05,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 348 [2025-02-06 20:14:05,541 INFO L73 IsDeterministic]: Start isDeterministic. Operand 348 states and 484 transitions. [2025-02-06 20:14:05,542 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:05,542 INFO L218 hiAutomatonCegarLoop]: Abstraction has 348 states and 484 transitions. [2025-02-06 20:14:05,542 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 348 states and 484 transitions. [2025-02-06 20:14:05,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 348 to 256. [2025-02-06 20:14:05,545 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 256 states, 252 states have (on average 1.373015873015873) internal successors, (346), 251 states have internal predecessors, (346), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:05,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 352 transitions. [2025-02-06 20:14:05,546 INFO L240 hiAutomatonCegarLoop]: Abstraction has 256 states and 352 transitions. [2025-02-06 20:14:05,547 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-02-06 20:14:05,547 INFO L432 stractBuchiCegarLoop]: Abstraction has 256 states and 352 transitions. [2025-02-06 20:14:05,547 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-06 20:14:05,547 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 256 states and 352 transitions. [2025-02-06 20:14:05,548 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 250 [2025-02-06 20:14:05,548 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:05,548 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:05,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:05,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:05,549 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:05,549 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:05,549 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:05,550 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 10 times [2025-02-06 20:14:05,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:05,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1245561167] [2025-02-06 20:14:05,550 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 20:14:05,550 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:05,553 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 20:14:05,554 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:05,554 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 20:14:05,554 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:05,554 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:05,555 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:05,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:05,556 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:05,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:05,558 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:05,559 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:05,559 INFO L85 PathProgramCache]: Analyzing trace with hash 156235178, now seen corresponding path program 1 times [2025-02-06 20:14:05,559 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:05,559 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303872499] [2025-02-06 20:14:05,559 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:05,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:05,595 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-02-06 20:14:05,679 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-02-06 20:14:05,679 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:05,680 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:06,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:06,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:06,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1303872499] [2025-02-06 20:14:06,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1303872499] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:06,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:06,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-02-06 20:14:06,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [369053542] [2025-02-06 20:14:06,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:06,014 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:06,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:06,014 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-02-06 20:14:06,015 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-02-06 20:14:06,015 INFO L87 Difference]: Start difference. First operand 256 states and 352 transitions. cyclomatic complexity: 99 Second operand has 11 states, 11 states have (on average 7.090909090909091) internal successors, (78), 11 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:07,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:07,251 INFO L93 Difference]: Finished difference Result 328 states and 450 transitions. [2025-02-06 20:14:07,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 328 states and 450 transitions. [2025-02-06 20:14:07,254 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 322 [2025-02-06 20:14:07,256 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 328 states to 328 states and 450 transitions. [2025-02-06 20:14:07,256 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 328 [2025-02-06 20:14:07,257 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 328 [2025-02-06 20:14:07,257 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328 states and 450 transitions. [2025-02-06 20:14:07,260 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:07,260 INFO L218 hiAutomatonCegarLoop]: Abstraction has 328 states and 450 transitions. [2025-02-06 20:14:07,260 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states and 450 transitions. [2025-02-06 20:14:07,265 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 259. [2025-02-06 20:14:07,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 259 states, 255 states have (on average 1.3725490196078431) internal successors, (350), 254 states have internal predecessors, (350), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:07,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 356 transitions. [2025-02-06 20:14:07,267 INFO L240 hiAutomatonCegarLoop]: Abstraction has 259 states and 356 transitions. [2025-02-06 20:14:07,267 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-02-06 20:14:07,268 INFO L432 stractBuchiCegarLoop]: Abstraction has 259 states and 356 transitions. [2025-02-06 20:14:07,268 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-06 20:14:07,268 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 259 states and 356 transitions. [2025-02-06 20:14:07,269 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 253 [2025-02-06 20:14:07,269 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:07,269 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:07,270 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:07,270 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:07,270 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:07,270 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:07,271 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:07,271 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 11 times [2025-02-06 20:14:07,271 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:07,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1898384702] [2025-02-06 20:14:07,271 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 20:14:07,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:07,276 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:07,276 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:07,276 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:07,276 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:07,276 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:07,278 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:07,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:07,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:07,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:07,281 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:07,282 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:07,282 INFO L85 PathProgramCache]: Analyzing trace with hash 674979459, now seen corresponding path program 1 times [2025-02-06 20:14:07,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:07,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1985831744] [2025-02-06 20:14:07,282 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:07,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:07,311 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-02-06 20:14:07,397 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-02-06 20:14:07,398 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:07,398 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:07,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:07,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:07,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1985831744] [2025-02-06 20:14:07,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1985831744] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:07,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:07,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-06 20:14:07,790 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [73362640] [2025-02-06 20:14:07,790 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:07,791 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:07,791 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:07,792 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-06 20:14:07,792 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-02-06 20:14:07,792 INFO L87 Difference]: Start difference. First operand 259 states and 356 transitions. cyclomatic complexity: 100 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:08,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:08,921 INFO L93 Difference]: Finished difference Result 352 states and 488 transitions. [2025-02-06 20:14:08,921 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 352 states and 488 transitions. [2025-02-06 20:14:08,923 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 346 [2025-02-06 20:14:08,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 352 states to 352 states and 488 transitions. [2025-02-06 20:14:08,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 352 [2025-02-06 20:14:08,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 352 [2025-02-06 20:14:08,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 352 states and 488 transitions. [2025-02-06 20:14:08,925 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:08,925 INFO L218 hiAutomatonCegarLoop]: Abstraction has 352 states and 488 transitions. [2025-02-06 20:14:08,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 352 states and 488 transitions. [2025-02-06 20:14:08,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 352 to 260. [2025-02-06 20:14:08,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 260 states, 256 states have (on average 1.375) internal successors, (352), 255 states have internal predecessors, (352), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:08,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 260 states to 260 states and 358 transitions. [2025-02-06 20:14:08,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 260 states and 358 transitions. [2025-02-06 20:14:08,932 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-02-06 20:14:08,932 INFO L432 stractBuchiCegarLoop]: Abstraction has 260 states and 358 transitions. [2025-02-06 20:14:08,932 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-06 20:14:08,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 260 states and 358 transitions. [2025-02-06 20:14:08,933 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 254 [2025-02-06 20:14:08,933 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:08,933 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:08,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:08,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:08,933 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:08,933 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:08,935 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:08,935 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 12 times [2025-02-06 20:14:08,935 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:08,935 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [485010608] [2025-02-06 20:14:08,935 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 20:14:08,935 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:08,940 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:08,940 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:08,940 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 20:14:08,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:08,940 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:08,941 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:08,942 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:08,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:08,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:08,945 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:08,945 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:08,945 INFO L85 PathProgramCache]: Analyzing trace with hash -1939002980, now seen corresponding path program 1 times [2025-02-06 20:14:08,946 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:08,946 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [26213407] [2025-02-06 20:14:08,946 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:08,946 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:08,966 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-02-06 20:14:09,022 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-02-06 20:14:09,023 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:09,023 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:09,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:09,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:09,600 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [26213407] [2025-02-06 20:14:09,600 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [26213407] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:09,600 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:09,600 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-06 20:14:09,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1490669943] [2025-02-06 20:14:09,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:09,602 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:09,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:09,603 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-06 20:14:09,603 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-02-06 20:14:09,603 INFO L87 Difference]: Start difference. First operand 260 states and 358 transitions. cyclomatic complexity: 101 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:10,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:10,167 INFO L93 Difference]: Finished difference Result 252 states and 346 transitions. [2025-02-06 20:14:10,167 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 252 states and 346 transitions. [2025-02-06 20:14:10,168 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 246 [2025-02-06 20:14:10,169 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 252 states to 252 states and 346 transitions. [2025-02-06 20:14:10,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252 [2025-02-06 20:14:10,170 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252 [2025-02-06 20:14:10,170 INFO L73 IsDeterministic]: Start isDeterministic. Operand 252 states and 346 transitions. [2025-02-06 20:14:10,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:10,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 252 states and 346 transitions. [2025-02-06 20:14:10,171 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 252 states and 346 transitions. [2025-02-06 20:14:10,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 252 to 250. [2025-02-06 20:14:10,173 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 250 states, 246 states have (on average 1.3699186991869918) internal successors, (337), 245 states have internal predecessors, (337), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:10,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 250 states to 250 states and 343 transitions. [2025-02-06 20:14:10,174 INFO L240 hiAutomatonCegarLoop]: Abstraction has 250 states and 343 transitions. [2025-02-06 20:14:10,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-02-06 20:14:10,174 INFO L432 stractBuchiCegarLoop]: Abstraction has 250 states and 343 transitions. [2025-02-06 20:14:10,175 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-06 20:14:10,175 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 250 states and 343 transitions. [2025-02-06 20:14:10,175 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 244 [2025-02-06 20:14:10,175 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:10,176 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:10,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:10,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:10,176 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:10,176 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:10,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:10,177 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 13 times [2025-02-06 20:14:10,177 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:10,177 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [68931964] [2025-02-06 20:14:10,177 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 20:14:10,177 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:10,181 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:10,182 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:10,182 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:10,182 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:10,182 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:10,183 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:10,184 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:10,184 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:10,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:10,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:10,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:10,187 INFO L85 PathProgramCache]: Analyzing trace with hash 188958916, now seen corresponding path program 1 times [2025-02-06 20:14:10,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:10,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [140474809] [2025-02-06 20:14:10,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:10,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:10,207 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-02-06 20:14:10,221 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-02-06 20:14:10,222 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:10,222 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:10,402 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:10,403 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:10,403 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [140474809] [2025-02-06 20:14:10,403 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [140474809] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:10,403 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:10,403 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-06 20:14:10,403 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373896323] [2025-02-06 20:14:10,403 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:10,403 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:10,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:10,404 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-06 20:14:10,404 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-02-06 20:14:10,404 INFO L87 Difference]: Start difference. First operand 250 states and 343 transitions. cyclomatic complexity: 96 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:10,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:10,819 INFO L93 Difference]: Finished difference Result 263 states and 359 transitions. [2025-02-06 20:14:10,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 263 states and 359 transitions. [2025-02-06 20:14:10,820 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 257 [2025-02-06 20:14:10,821 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 263 states to 263 states and 359 transitions. [2025-02-06 20:14:10,821 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 263 [2025-02-06 20:14:10,822 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 263 [2025-02-06 20:14:10,822 INFO L73 IsDeterministic]: Start isDeterministic. Operand 263 states and 359 transitions. [2025-02-06 20:14:10,822 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:10,822 INFO L218 hiAutomatonCegarLoop]: Abstraction has 263 states and 359 transitions. [2025-02-06 20:14:10,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states and 359 transitions. [2025-02-06 20:14:10,824 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 253. [2025-02-06 20:14:10,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253 states, 249 states have (on average 1.3694779116465863) internal successors, (341), 248 states have internal predecessors, (341), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:10,825 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253 states to 253 states and 347 transitions. [2025-02-06 20:14:10,826 INFO L240 hiAutomatonCegarLoop]: Abstraction has 253 states and 347 transitions. [2025-02-06 20:14:10,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-02-06 20:14:10,828 INFO L432 stractBuchiCegarLoop]: Abstraction has 253 states and 347 transitions. [2025-02-06 20:14:10,828 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-06 20:14:10,828 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253 states and 347 transitions. [2025-02-06 20:14:10,829 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 247 [2025-02-06 20:14:10,829 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:10,829 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:10,829 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:10,830 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:10,830 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:10,830 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:10,830 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:10,830 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 14 times [2025-02-06 20:14:10,830 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:10,830 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893309732] [2025-02-06 20:14:10,830 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 20:14:10,831 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:10,834 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:10,834 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:10,835 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:10,835 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:10,835 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:10,836 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:10,836 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:10,836 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:10,836 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:10,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:10,840 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:10,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1984904094, now seen corresponding path program 1 times [2025-02-06 20:14:10,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:10,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14359254] [2025-02-06 20:14:10,840 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:10,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:10,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-02-06 20:14:10,883 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-02-06 20:14:10,883 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:10,883 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:11,050 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:11,050 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:11,050 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [14359254] [2025-02-06 20:14:11,050 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [14359254] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:11,050 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:11,050 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-06 20:14:11,051 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1984962803] [2025-02-06 20:14:11,051 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:11,051 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:11,051 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:11,051 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-06 20:14:11,051 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-02-06 20:14:11,051 INFO L87 Difference]: Start difference. First operand 253 states and 347 transitions. cyclomatic complexity: 97 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:11,739 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:11,739 INFO L93 Difference]: Finished difference Result 273 states and 373 transitions. [2025-02-06 20:14:11,739 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 273 states and 373 transitions. [2025-02-06 20:14:11,740 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 267 [2025-02-06 20:14:11,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 273 states to 273 states and 373 transitions. [2025-02-06 20:14:11,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 273 [2025-02-06 20:14:11,742 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 273 [2025-02-06 20:14:11,742 INFO L73 IsDeterministic]: Start isDeterministic. Operand 273 states and 373 transitions. [2025-02-06 20:14:11,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:11,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 273 states and 373 transitions. [2025-02-06 20:14:11,742 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 273 states and 373 transitions. [2025-02-06 20:14:11,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 273 to 253. [2025-02-06 20:14:11,745 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 253 states, 249 states have (on average 1.3694779116465863) internal successors, (341), 248 states have internal predecessors, (341), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:11,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 253 states to 253 states and 347 transitions. [2025-02-06 20:14:11,746 INFO L240 hiAutomatonCegarLoop]: Abstraction has 253 states and 347 transitions. [2025-02-06 20:14:11,746 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 20:14:11,747 INFO L432 stractBuchiCegarLoop]: Abstraction has 253 states and 347 transitions. [2025-02-06 20:14:11,747 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-06 20:14:11,747 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 253 states and 347 transitions. [2025-02-06 20:14:11,748 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 247 [2025-02-06 20:14:11,748 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:11,748 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:11,748 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:11,748 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:11,749 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:11,749 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:11,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:11,749 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 15 times [2025-02-06 20:14:11,749 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:11,749 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808982563] [2025-02-06 20:14:11,749 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 20:14:11,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:11,753 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:11,754 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:11,754 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 20:14:11,754 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:11,754 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:11,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:11,759 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:11,759 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:11,759 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:11,761 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:11,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:11,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1837692902, now seen corresponding path program 1 times [2025-02-06 20:14:11,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:11,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826678116] [2025-02-06 20:14:11,764 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:11,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:11,785 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:11,801 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:11,801 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:11,801 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:12,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:12,002 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:12,002 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826678116] [2025-02-06 20:14:12,003 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826678116] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:12,003 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:12,003 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-06 20:14:12,003 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1007990543] [2025-02-06 20:14:12,003 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:12,003 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:12,003 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:12,003 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-06 20:14:12,003 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-02-06 20:14:12,003 INFO L87 Difference]: Start difference. First operand 253 states and 347 transitions. cyclomatic complexity: 97 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:12,702 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:12,703 INFO L93 Difference]: Finished difference Result 269 states and 368 transitions. [2025-02-06 20:14:12,703 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 269 states and 368 transitions. [2025-02-06 20:14:12,704 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 263 [2025-02-06 20:14:12,705 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 269 states to 269 states and 368 transitions. [2025-02-06 20:14:12,705 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 269 [2025-02-06 20:14:12,705 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 269 [2025-02-06 20:14:12,705 INFO L73 IsDeterministic]: Start isDeterministic. Operand 269 states and 368 transitions. [2025-02-06 20:14:12,706 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:12,706 INFO L218 hiAutomatonCegarLoop]: Abstraction has 269 states and 368 transitions. [2025-02-06 20:14:12,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states and 368 transitions. [2025-02-06 20:14:12,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 263. [2025-02-06 20:14:12,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 263 states, 259 states have (on average 1.3629343629343629) internal successors, (353), 258 states have internal predecessors, (353), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:12,709 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 263 states to 263 states and 359 transitions. [2025-02-06 20:14:12,709 INFO L240 hiAutomatonCegarLoop]: Abstraction has 263 states and 359 transitions. [2025-02-06 20:14:12,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 20:14:12,710 INFO L432 stractBuchiCegarLoop]: Abstraction has 263 states and 359 transitions. [2025-02-06 20:14:12,710 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-06 20:14:12,710 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 263 states and 359 transitions. [2025-02-06 20:14:12,710 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 257 [2025-02-06 20:14:12,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:12,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:12,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:12,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:12,711 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:12,711 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:12,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:12,711 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 16 times [2025-02-06 20:14:12,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:12,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540408769] [2025-02-06 20:14:12,712 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 20:14:12,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:12,715 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 20:14:12,716 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:12,716 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 20:14:12,716 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:12,716 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:12,717 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:12,718 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:12,718 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:12,718 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:12,720 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:12,721 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:12,721 INFO L85 PathProgramCache]: Analyzing trace with hash 181282284, now seen corresponding path program 1 times [2025-02-06 20:14:12,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:12,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1011363348] [2025-02-06 20:14:12,721 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:12,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:12,769 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:12,796 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:12,796 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:12,796 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:12,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:12,977 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:12,977 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1011363348] [2025-02-06 20:14:12,977 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1011363348] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:12,977 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:12,977 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 20:14:12,977 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1304293671] [2025-02-06 20:14:12,977 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:12,978 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:12,978 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:12,978 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-06 20:14:12,978 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-06 20:14:12,978 INFO L87 Difference]: Start difference. First operand 263 states and 359 transitions. cyclomatic complexity: 99 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:13,429 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:13,430 INFO L93 Difference]: Finished difference Result 268 states and 365 transitions. [2025-02-06 20:14:13,430 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 268 states and 365 transitions. [2025-02-06 20:14:13,431 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 262 [2025-02-06 20:14:13,432 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 268 states to 268 states and 365 transitions. [2025-02-06 20:14:13,432 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 268 [2025-02-06 20:14:13,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 268 [2025-02-06 20:14:13,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 268 states and 365 transitions. [2025-02-06 20:14:13,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:13,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 268 states and 365 transitions. [2025-02-06 20:14:13,433 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states and 365 transitions. [2025-02-06 20:14:13,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 267. [2025-02-06 20:14:13,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 267 states, 263 states have (on average 1.361216730038023) internal successors, (358), 262 states have internal predecessors, (358), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:13,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 267 states to 267 states and 364 transitions. [2025-02-06 20:14:13,437 INFO L240 hiAutomatonCegarLoop]: Abstraction has 267 states and 364 transitions. [2025-02-06 20:14:13,437 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-06 20:14:13,438 INFO L432 stractBuchiCegarLoop]: Abstraction has 267 states and 364 transitions. [2025-02-06 20:14:13,438 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-06 20:14:13,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 267 states and 364 transitions. [2025-02-06 20:14:13,438 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 261 [2025-02-06 20:14:13,438 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:13,438 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:13,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:13,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:13,439 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:13,439 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:13,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:13,440 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 17 times [2025-02-06 20:14:13,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:13,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [398502094] [2025-02-06 20:14:13,441 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 20:14:13,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:13,444 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:13,445 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:13,445 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:13,445 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:13,445 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:13,446 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:13,447 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:13,447 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:13,447 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:13,450 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:13,450 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:13,450 INFO L85 PathProgramCache]: Analyzing trace with hash 945598333, now seen corresponding path program 1 times [2025-02-06 20:14:13,450 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:13,450 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [278362552] [2025-02-06 20:14:13,450 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:13,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:13,471 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:13,580 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:13,580 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:13,580 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:13,983 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:13,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:13,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [278362552] [2025-02-06 20:14:13,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [278362552] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:13,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:13,984 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-06 20:14:13,984 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589261384] [2025-02-06 20:14:13,984 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:13,984 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:13,984 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:13,984 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-06 20:14:13,985 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-02-06 20:14:13,985 INFO L87 Difference]: Start difference. First operand 267 states and 364 transitions. cyclomatic complexity: 100 Second operand has 13 states, 13 states have (on average 6.076923076923077) internal successors, (79), 13 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:14,690 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:14,690 INFO L93 Difference]: Finished difference Result 322 states and 444 transitions. [2025-02-06 20:14:14,690 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 322 states and 444 transitions. [2025-02-06 20:14:14,691 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 316 [2025-02-06 20:14:14,692 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 322 states to 322 states and 444 transitions. [2025-02-06 20:14:14,692 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 322 [2025-02-06 20:14:14,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 322 [2025-02-06 20:14:14,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 322 states and 444 transitions. [2025-02-06 20:14:14,693 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:14,693 INFO L218 hiAutomatonCegarLoop]: Abstraction has 322 states and 444 transitions. [2025-02-06 20:14:14,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states and 444 transitions. [2025-02-06 20:14:14,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 275. [2025-02-06 20:14:14,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 275 states, 271 states have (on average 1.3616236162361623) internal successors, (369), 270 states have internal predecessors, (369), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:14,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 275 states to 275 states and 375 transitions. [2025-02-06 20:14:14,697 INFO L240 hiAutomatonCegarLoop]: Abstraction has 275 states and 375 transitions. [2025-02-06 20:14:14,697 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-02-06 20:14:14,697 INFO L432 stractBuchiCegarLoop]: Abstraction has 275 states and 375 transitions. [2025-02-06 20:14:14,697 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-06 20:14:14,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 275 states and 375 transitions. [2025-02-06 20:14:14,698 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 269 [2025-02-06 20:14:14,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:14,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:14,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:14,699 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:14,699 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:14,699 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:14,699 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:14,699 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 18 times [2025-02-06 20:14:14,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:14,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [578231104] [2025-02-06 20:14:14,700 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 20:14:14,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:14,703 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:14,703 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:14,703 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 20:14:14,703 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:14,703 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:14,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:14,705 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:14,705 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:14,705 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:14,707 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:14,708 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:14,708 INFO L85 PathProgramCache]: Analyzing trace with hash 204712761, now seen corresponding path program 1 times [2025-02-06 20:14:14,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:14,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2085286150] [2025-02-06 20:14:14,708 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:14,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:14,727 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:14,765 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:14,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:14,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:15,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:15,062 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:15,062 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2085286150] [2025-02-06 20:14:15,062 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2085286150] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:15,063 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:15,063 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-06 20:14:15,063 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505006418] [2025-02-06 20:14:15,063 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:15,063 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:15,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:15,064 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-06 20:14:15,064 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-02-06 20:14:15,065 INFO L87 Difference]: Start difference. First operand 275 states and 375 transitions. cyclomatic complexity: 103 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:15,824 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:15,824 INFO L93 Difference]: Finished difference Result 284 states and 384 transitions. [2025-02-06 20:14:15,824 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 284 states and 384 transitions. [2025-02-06 20:14:15,825 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 278 [2025-02-06 20:14:15,826 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 284 states to 284 states and 384 transitions. [2025-02-06 20:14:15,826 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 284 [2025-02-06 20:14:15,826 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 284 [2025-02-06 20:14:15,826 INFO L73 IsDeterministic]: Start isDeterministic. Operand 284 states and 384 transitions. [2025-02-06 20:14:15,827 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:15,827 INFO L218 hiAutomatonCegarLoop]: Abstraction has 284 states and 384 transitions. [2025-02-06 20:14:15,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states and 384 transitions. [2025-02-06 20:14:15,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 278. [2025-02-06 20:14:15,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 278 states, 274 states have (on average 1.3576642335766422) internal successors, (372), 273 states have internal predecessors, (372), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:15,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 378 transitions. [2025-02-06 20:14:15,831 INFO L240 hiAutomatonCegarLoop]: Abstraction has 278 states and 378 transitions. [2025-02-06 20:14:15,833 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 20:14:15,833 INFO L432 stractBuchiCegarLoop]: Abstraction has 278 states and 378 transitions. [2025-02-06 20:14:15,833 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-06 20:14:15,833 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 278 states and 378 transitions. [2025-02-06 20:14:15,834 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 272 [2025-02-06 20:14:15,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:15,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:15,835 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:15,835 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:15,835 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:15,835 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:15,835 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:15,835 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 19 times [2025-02-06 20:14:15,835 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:15,836 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131550398] [2025-02-06 20:14:15,836 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 20:14:15,836 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:15,840 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:15,840 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:15,840 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:15,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:15,841 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:15,842 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:15,842 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:15,842 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:15,842 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:15,845 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:15,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:15,846 INFO L85 PathProgramCache]: Analyzing trace with hash 1154818728, now seen corresponding path program 1 times [2025-02-06 20:14:15,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:15,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118938388] [2025-02-06 20:14:15,846 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:15,846 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:15,867 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:15,916 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:15,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:15,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:16,117 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:16,117 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:16,117 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2118938388] [2025-02-06 20:14:16,118 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2118938388] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:16,118 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:16,118 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-06 20:14:16,118 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1181750655] [2025-02-06 20:14:16,118 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:16,118 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:16,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:16,119 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-06 20:14:16,119 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-06 20:14:16,119 INFO L87 Difference]: Start difference. First operand 278 states and 378 transitions. cyclomatic complexity: 103 Second operand has 7 states, 7 states have (on average 11.285714285714286) internal successors, (79), 7 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:16,565 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:16,565 INFO L93 Difference]: Finished difference Result 282 states and 381 transitions. [2025-02-06 20:14:16,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 282 states and 381 transitions. [2025-02-06 20:14:16,566 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 276 [2025-02-06 20:14:16,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 282 states to 282 states and 381 transitions. [2025-02-06 20:14:16,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282 [2025-02-06 20:14:16,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282 [2025-02-06 20:14:16,567 INFO L73 IsDeterministic]: Start isDeterministic. Operand 282 states and 381 transitions. [2025-02-06 20:14:16,567 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:16,567 INFO L218 hiAutomatonCegarLoop]: Abstraction has 282 states and 381 transitions. [2025-02-06 20:14:16,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states and 381 transitions. [2025-02-06 20:14:16,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 278. [2025-02-06 20:14:16,570 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 278 states, 274 states have (on average 1.354014598540146) internal successors, (371), 273 states have internal predecessors, (371), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:16,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 377 transitions. [2025-02-06 20:14:16,571 INFO L240 hiAutomatonCegarLoop]: Abstraction has 278 states and 377 transitions. [2025-02-06 20:14:16,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-06 20:14:16,572 INFO L432 stractBuchiCegarLoop]: Abstraction has 278 states and 377 transitions. [2025-02-06 20:14:16,572 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-06 20:14:16,572 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 278 states and 377 transitions. [2025-02-06 20:14:16,574 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 272 [2025-02-06 20:14:16,574 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:16,574 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:16,574 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:16,574 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:16,575 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:16,575 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise41#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:16,575 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:16,575 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 20 times [2025-02-06 20:14:16,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:16,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1947552957] [2025-02-06 20:14:16,575 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 20:14:16,575 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:16,579 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:16,580 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:16,580 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:16,580 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:16,580 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:16,581 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:16,581 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:16,581 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:16,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:16,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:16,585 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:16,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1127550968, now seen corresponding path program 1 times [2025-02-06 20:14:16,585 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:16,585 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966705556] [2025-02-06 20:14:16,585 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:16,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:16,607 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-06 20:14:16,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-06 20:14:16,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:16,630 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:16,830 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:16,830 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:16,830 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1966705556] [2025-02-06 20:14:16,830 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1966705556] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:16,830 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:16,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-06 20:14:16,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1408225017] [2025-02-06 20:14:16,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:16,831 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:16,831 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:16,831 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-06 20:14:16,831 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-02-06 20:14:16,831 INFO L87 Difference]: Start difference. First operand 278 states and 377 transitions. cyclomatic complexity: 102 Second operand has 10 states, 10 states have (on average 7.9) internal successors, (79), 10 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:17,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:17,527 INFO L93 Difference]: Finished difference Result 292 states and 396 transitions. [2025-02-06 20:14:17,527 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 292 states and 396 transitions. [2025-02-06 20:14:17,528 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 286 [2025-02-06 20:14:17,530 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 292 states to 292 states and 396 transitions. [2025-02-06 20:14:17,530 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 292 [2025-02-06 20:14:17,530 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 292 [2025-02-06 20:14:17,530 INFO L73 IsDeterministic]: Start isDeterministic. Operand 292 states and 396 transitions. [2025-02-06 20:14:17,530 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:17,530 INFO L218 hiAutomatonCegarLoop]: Abstraction has 292 states and 396 transitions. [2025-02-06 20:14:17,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states and 396 transitions. [2025-02-06 20:14:17,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 278. [2025-02-06 20:14:17,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 278 states, 274 states have (on average 1.354014598540146) internal successors, (371), 273 states have internal predecessors, (371), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:17,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 278 states to 278 states and 377 transitions. [2025-02-06 20:14:17,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 278 states and 377 transitions. [2025-02-06 20:14:17,539 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 20:14:17,539 INFO L432 stractBuchiCegarLoop]: Abstraction has 278 states and 377 transitions. [2025-02-06 20:14:17,539 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-06 20:14:17,539 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 278 states and 377 transitions. [2025-02-06 20:14:17,540 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 272 [2025-02-06 20:14:17,540 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:17,540 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:17,541 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:17,541 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:17,541 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:17,541 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:17,542 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:17,542 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 21 times [2025-02-06 20:14:17,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:17,542 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1225801977] [2025-02-06 20:14:17,542 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-06 20:14:17,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:17,546 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:17,546 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:17,546 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-06 20:14:17,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:17,546 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:17,547 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:17,548 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:17,548 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:17,548 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:17,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:17,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:17,551 INFO L85 PathProgramCache]: Analyzing trace with hash -619008033, now seen corresponding path program 1 times [2025-02-06 20:14:17,551 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:17,551 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372743543] [2025-02-06 20:14:17,551 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:17,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:17,573 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:17,764 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:17,764 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:17,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:18,312 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:18,313 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:18,313 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372743543] [2025-02-06 20:14:18,313 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372743543] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:18,313 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:18,313 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [18] imperfect sequences [] total 18 [2025-02-06 20:14:18,314 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357730216] [2025-02-06 20:14:18,314 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:18,314 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:18,314 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:18,314 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2025-02-06 20:14:18,315 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=265, Unknown=0, NotChecked=0, Total=306 [2025-02-06 20:14:18,315 INFO L87 Difference]: Start difference. First operand 278 states and 377 transitions. cyclomatic complexity: 102 Second operand has 18 states, 18 states have (on average 4.444444444444445) internal successors, (80), 18 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:20,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:20,127 INFO L93 Difference]: Finished difference Result 390 states and 538 transitions. [2025-02-06 20:14:20,127 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390 states and 538 transitions. [2025-02-06 20:14:20,128 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 384 [2025-02-06 20:14:20,130 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390 states to 390 states and 538 transitions. [2025-02-06 20:14:20,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 390 [2025-02-06 20:14:20,130 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 390 [2025-02-06 20:14:20,130 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390 states and 538 transitions. [2025-02-06 20:14:20,130 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:20,130 INFO L218 hiAutomatonCegarLoop]: Abstraction has 390 states and 538 transitions. [2025-02-06 20:14:20,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390 states and 538 transitions. [2025-02-06 20:14:20,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390 to 291. [2025-02-06 20:14:20,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 291 states, 287 states have (on average 1.3554006968641115) internal successors, (389), 286 states have internal predecessors, (389), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:20,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 291 states to 291 states and 395 transitions. [2025-02-06 20:14:20,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 291 states and 395 transitions. [2025-02-06 20:14:20,138 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2025-02-06 20:14:20,138 INFO L432 stractBuchiCegarLoop]: Abstraction has 291 states and 395 transitions. [2025-02-06 20:14:20,138 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-02-06 20:14:20,138 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 291 states and 395 transitions. [2025-02-06 20:14:20,139 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 285 [2025-02-06 20:14:20,140 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:20,140 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:20,140 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:20,141 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:20,141 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:20,141 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:20,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:20,142 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 22 times [2025-02-06 20:14:20,142 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:20,142 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679258727] [2025-02-06 20:14:20,142 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-06 20:14:20,142 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:20,147 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-02-06 20:14:20,148 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:20,148 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-06 20:14:20,148 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:20,148 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:20,149 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:20,150 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:20,150 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:20,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:20,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:20,153 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:20,153 INFO L85 PathProgramCache]: Analyzing trace with hash 1723440191, now seen corresponding path program 1 times [2025-02-06 20:14:20,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:20,154 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649867239] [2025-02-06 20:14:20,154 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:20,154 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:20,178 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:20,230 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:20,230 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:20,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:20,734 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:20,734 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:20,734 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649867239] [2025-02-06 20:14:20,734 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649867239] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:20,734 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:20,734 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [17] imperfect sequences [] total 17 [2025-02-06 20:14:20,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693443164] [2025-02-06 20:14:20,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:20,735 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:20,735 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:20,735 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-02-06 20:14:20,735 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2025-02-06 20:14:20,736 INFO L87 Difference]: Start difference. First operand 291 states and 395 transitions. cyclomatic complexity: 107 Second operand has 17 states, 17 states have (on average 4.705882352941177) internal successors, (80), 17 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:21,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:21,767 INFO L93 Difference]: Finished difference Result 309 states and 422 transitions. [2025-02-06 20:14:21,767 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 309 states and 422 transitions. [2025-02-06 20:14:21,768 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 303 [2025-02-06 20:14:21,769 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 309 states to 309 states and 422 transitions. [2025-02-06 20:14:21,769 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 309 [2025-02-06 20:14:21,769 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 309 [2025-02-06 20:14:21,769 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 422 transitions. [2025-02-06 20:14:21,770 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:21,770 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309 states and 422 transitions. [2025-02-06 20:14:21,770 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 422 transitions. [2025-02-06 20:14:21,772 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 296. [2025-02-06 20:14:21,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 296 states, 292 states have (on average 1.356164383561644) internal successors, (396), 291 states have internal predecessors, (396), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:21,773 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 296 states to 296 states and 402 transitions. [2025-02-06 20:14:21,773 INFO L240 hiAutomatonCegarLoop]: Abstraction has 296 states and 402 transitions. [2025-02-06 20:14:21,774 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-02-06 20:14:21,774 INFO L432 stractBuchiCegarLoop]: Abstraction has 296 states and 402 transitions. [2025-02-06 20:14:21,774 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-02-06 20:14:21,774 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 296 states and 402 transitions. [2025-02-06 20:14:21,775 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 290 [2025-02-06 20:14:21,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:21,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:21,775 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:21,775 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:21,775 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:21,775 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:21,776 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:21,776 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 23 times [2025-02-06 20:14:21,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:21,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [581889315] [2025-02-06 20:14:21,776 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-06 20:14:21,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:21,780 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:21,780 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:21,781 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:21,781 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:21,781 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:21,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:21,783 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:21,783 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:21,783 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:21,786 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:21,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:21,787 INFO L85 PathProgramCache]: Analyzing trace with hash 42455334, now seen corresponding path program 1 times [2025-02-06 20:14:21,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:21,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2007629979] [2025-02-06 20:14:21,787 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:21,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:21,807 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:21,862 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:21,862 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:21,862 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:22,212 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:22,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:22,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2007629979] [2025-02-06 20:14:22,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2007629979] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:22,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:22,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-06 20:14:22,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333018016] [2025-02-06 20:14:22,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:22,213 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:22,213 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:22,213 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-06 20:14:22,213 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-02-06 20:14:22,213 INFO L87 Difference]: Start difference. First operand 296 states and 402 transitions. cyclomatic complexity: 109 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:22,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:22,891 INFO L93 Difference]: Finished difference Result 306 states and 415 transitions. [2025-02-06 20:14:22,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 306 states and 415 transitions. [2025-02-06 20:14:22,892 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 300 [2025-02-06 20:14:22,893 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 306 states to 306 states and 415 transitions. [2025-02-06 20:14:22,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 306 [2025-02-06 20:14:22,896 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 306 [2025-02-06 20:14:22,896 INFO L73 IsDeterministic]: Start isDeterministic. Operand 306 states and 415 transitions. [2025-02-06 20:14:22,896 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:22,896 INFO L218 hiAutomatonCegarLoop]: Abstraction has 306 states and 415 transitions. [2025-02-06 20:14:22,896 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states and 415 transitions. [2025-02-06 20:14:22,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 301. [2025-02-06 20:14:22,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 301 states, 297 states have (on average 1.3569023569023568) internal successors, (403), 296 states have internal predecessors, (403), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:22,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 301 states to 301 states and 409 transitions. [2025-02-06 20:14:22,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 301 states and 409 transitions. [2025-02-06 20:14:22,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-02-06 20:14:22,901 INFO L432 stractBuchiCegarLoop]: Abstraction has 301 states and 409 transitions. [2025-02-06 20:14:22,901 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-02-06 20:14:22,901 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 301 states and 409 transitions. [2025-02-06 20:14:22,902 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 295 [2025-02-06 20:14:22,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:22,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:22,902 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:22,902 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:22,903 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:22,903 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise40#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise42#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:22,903 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:22,903 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 24 times [2025-02-06 20:14:22,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:22,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023557957] [2025-02-06 20:14:22,903 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-06 20:14:22,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:22,908 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:22,909 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:22,909 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-06 20:14:22,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:22,909 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:22,910 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:22,911 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:22,911 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:22,911 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:22,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:22,914 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:22,914 INFO L85 PathProgramCache]: Analyzing trace with hash -476288947, now seen corresponding path program 1 times [2025-02-06 20:14:22,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:22,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [582730825] [2025-02-06 20:14:22,915 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:22,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:22,934 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:22,972 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:22,972 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:22,972 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:23,127 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:23,128 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:23,128 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [582730825] [2025-02-06 20:14:23,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [582730825] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:23,128 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:23,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-02-06 20:14:23,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1351144142] [2025-02-06 20:14:23,128 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:23,128 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:23,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:23,128 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-02-06 20:14:23,128 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2025-02-06 20:14:23,128 INFO L87 Difference]: Start difference. First operand 301 states and 409 transitions. cyclomatic complexity: 111 Second operand has 8 states, 8 states have (on average 10.0) internal successors, (80), 8 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:35,412 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 12.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-02-06 20:14:35,561 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:35,561 INFO L93 Difference]: Finished difference Result 397 states and 545 transitions. [2025-02-06 20:14:35,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 397 states and 545 transitions. [2025-02-06 20:14:35,562 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 391 [2025-02-06 20:14:35,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 397 states to 397 states and 545 transitions. [2025-02-06 20:14:35,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 397 [2025-02-06 20:14:35,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 397 [2025-02-06 20:14:35,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 397 states and 545 transitions. [2025-02-06 20:14:35,564 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:35,564 INFO L218 hiAutomatonCegarLoop]: Abstraction has 397 states and 545 transitions. [2025-02-06 20:14:35,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 397 states and 545 transitions. [2025-02-06 20:14:35,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 397 to 307. [2025-02-06 20:14:35,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 307 states, 303 states have (on average 1.3564356435643565) internal successors, (411), 302 states have internal predecessors, (411), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:35,570 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 417 transitions. [2025-02-06 20:14:35,570 INFO L240 hiAutomatonCegarLoop]: Abstraction has 307 states and 417 transitions. [2025-02-06 20:14:35,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-02-06 20:14:35,570 INFO L432 stractBuchiCegarLoop]: Abstraction has 307 states and 417 transitions. [2025-02-06 20:14:35,570 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-02-06 20:14:35,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 307 states and 417 transitions. [2025-02-06 20:14:35,571 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 301 [2025-02-06 20:14:35,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:35,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:35,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:35,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:35,572 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:35,572 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise40#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise41#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise42#1;assume main_#t~bitwise42#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:35,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:35,572 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 25 times [2025-02-06 20:14:35,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:35,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2094916106] [2025-02-06 20:14:35,572 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-06 20:14:35,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:35,576 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:35,576 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:35,576 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:35,576 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:35,577 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:35,577 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:35,578 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:35,578 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:35,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:35,581 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:35,581 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:35,581 INFO L85 PathProgramCache]: Analyzing trace with hash -1536231214, now seen corresponding path program 1 times [2025-02-06 20:14:35,581 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:35,581 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1633987774] [2025-02-06 20:14:35,582 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:35,582 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:35,603 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:35,661 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:35,661 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:35,661 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:35,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-06 20:14:35,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-06 20:14:35,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1633987774] [2025-02-06 20:14:35,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1633987774] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-06 20:14:35,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-06 20:14:35,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-06 20:14:35,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [500267740] [2025-02-06 20:14:35,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-06 20:14:35,947 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-06 20:14:35,947 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-06 20:14:35,947 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-06 20:14:35,947 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-02-06 20:14:35,948 INFO L87 Difference]: Start difference. First operand 307 states and 417 transitions. cyclomatic complexity: 113 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-06 20:14:36,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-06 20:14:36,576 INFO L93 Difference]: Finished difference Result 319 states and 434 transitions. [2025-02-06 20:14:36,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 434 transitions. [2025-02-06 20:14:36,577 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 313 [2025-02-06 20:14:36,578 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 319 states and 434 transitions. [2025-02-06 20:14:36,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 319 [2025-02-06 20:14:36,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 319 [2025-02-06 20:14:36,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 319 states and 434 transitions. [2025-02-06 20:14:36,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-06 20:14:36,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 319 states and 434 transitions. [2025-02-06 20:14:36,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states and 434 transitions. [2025-02-06 20:14:36,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 311. [2025-02-06 20:14:36,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 311 states, 307 states have (on average 1.3550488599348534) internal successors, (416), 306 states have internal predecessors, (416), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-06 20:14:36,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 422 transitions. [2025-02-06 20:14:36,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 311 states and 422 transitions. [2025-02-06 20:14:36,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-06 20:14:36,585 INFO L432 stractBuchiCegarLoop]: Abstraction has 311 states and 422 transitions. [2025-02-06 20:14:36,585 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-02-06 20:14:36,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 311 states and 422 transitions. [2025-02-06 20:14:36,585 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 305 [2025-02-06 20:14:36,585 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-06 20:14:36,585 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-06 20:14:36,586 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-06 20:14:36,586 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-06 20:14:36,586 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(11, 2);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset, main_#t~nondet5#1, main_#t~mem6#1, main_#t~mem8#1, main_#t~mem7#1, main_#t~mem9#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem11#1, main_#t~mem13#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem15#1, main_#t~mem17#1, main_#t~mem18#1, main_#t~bitwise19#1, main_#t~bitwise20#1, main_#t~bitwise21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~switch28#1, main_#t~mem29#1, main_#t~mem30#1, main_#t~mem31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~bitwise40#1, main_#t~bitwise41#1, main_#t~bitwise42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc49#1.base, main_#t~malloc49#1.offset, main_#t~mem50#1.base, main_#t~mem50#1.offset, main_#t~mem51#1.base, main_#t~mem51#1.offset, main_#t~memset~res52#1.base, main_#t~memset~res52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~mem55#1.base, main_#t~mem55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~malloc58#1.base, main_#t~malloc58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~mem61#1.base, main_#t~mem61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~memset~res65#1.base, main_#t~memset~res65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~mem68#1.base, main_#t~mem68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1.base, main_#t~mem73#1.offset, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1, main_#t~post76#1, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~bitwise79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1.base, main_#t~mem81#1.offset, main_#t~mem82#1, main_#t~post83#1, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1.base, main_#t~mem85#1.offset, main_#t~mem86#1.base, main_#t~mem86#1.offset, main_#t~mem88#1, main_#t~mem87#1, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1, main_#t~short91#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~malloc94#1.base, main_#t~malloc94#1.offset, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~memset~res97#1.base, main_#t~memset~res97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem102#1, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1, main_#t~bitwise103#1, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem107#1, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~bitwise108#1, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1.base, main_#t~mem114#1.offset, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem118#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1, main_#t~bitwise119#1, main_#t~mem120#1, main_#t~pre121#1, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem123#1, main_#t~mem124#1.base, main_#t~mem124#1.offset, main_#t~mem125#1, main_#t~post126#1, main_#t~mem130#1, main_#t~mem128#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem129#1, main_#t~mem131#1, main_#t~post132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~post136#1, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem140#1, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1, main_#t~post143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1.base, main_#t~mem146#1.offset, main_#t~mem149#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1, main_#t~ite152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem155#1.base, main_#t~mem155#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~post156#1, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~sum~0#1;havoc main_~i~0#1;havoc main_~user~0#1.base, main_~user~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;main_~sum~0#1 := 0;main_~i~0#1 := 0;" [2025-02-06 20:14:36,586 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < 10;call main_#t~malloc4#1.base, main_#t~malloc4#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc4#1.base, main_#t~malloc4#1.offset;havoc main_#t~malloc4#1.base, main_#t~malloc4#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call write~int#1(main_~i~0#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call write~int#1(main_#t~nondet5#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~nondet5#1;call main_#t~mem6#1 := read~int#1(main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);main_~sum~0#1 := main_~sum~0#1 + main_#t~mem6#1;havoc main_#t~mem6#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch28#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch28#1;" "main_#t~switch28#1 := main_#t~switch28#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem36#1 := read~int#1(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem37#1 := read~int#1(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem37#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem38#1 := read~int#1(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem38#1 % 256 % 4294967296);" "main_#t~switch28#1 := main_#t~switch28#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch28#1;call main_#t~mem39#1 := read~int#1(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem39#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem39#1 % 256 % 4294967296 else main_#t~mem39#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~switch28#1;havoc main_#t~mem29#1;havoc main_#t~mem30#1;havoc main_#t~mem31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise40#1;assume main_#t~bitwise40#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise40#1;havoc main_#t~bitwise40#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise41#1;assume main_#t~bitwise41#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise41#1;havoc main_#t~bitwise41#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise42#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise42#1;havoc main_#t~bitwise42#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#1(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#1(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem66#1.base, main_#t~mem66#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem66#1.base, main_#t~mem66#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem66#1.base, main_#t~mem66#1.offset;" "assume true;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem67#1.base, main_#t~mem67#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem68#1.base, main_#t~mem68#1.offset := read~$Pointer$#1(main_#t~mem67#1.base, 16 + main_#t~mem67#1.offset, 4);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem70#1 := read~int#1(main_#t~mem69#1.base, 20 + main_#t~mem69#1.offset, 4);call write~$Pointer$#1(main_#t~mem68#1.base, main_#t~mem68#1.offset - main_#t~mem70#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem67#1.base, main_#t~mem67#1.offset;havoc main_#t~mem68#1.base, main_#t~mem68#1.offset;havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;havoc main_#t~mem70#1;call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#1(main_#t~mem71#1.base, 16 + main_#t~mem71#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem72#1.base, 8 + main_#t~mem72#1.offset, 4);havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;call main_#t~mem73#1.base, main_#t~mem73#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem73#1.base, 16 + main_#t~mem73#1.offset, 4);havoc main_#t~mem73#1.base, main_#t~mem73#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1 := read~int#1(main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);main_#t~post76#1 := main_#t~mem75#1;call write~int#1(1 + main_#t~post76#1, main_#t~mem74#1.base, 12 + main_#t~mem74#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1;havoc main_#t~post76#1;" "assume true;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#1(main_#t~mem77#1.base, 4 + main_#t~mem77#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem78#1 - 1) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise79#1;havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~bitwise79#1;" "assume !false;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#1(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1.base, main_#t~mem81#1.offset := read~$Pointer$#1(main_#t~mem80#1.base, main_#t~mem80#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem81#1.base, main_#t~mem81#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1.base, main_#t~mem81#1.offset;call main_#t~mem82#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post83#1 := main_#t~mem82#1;call write~int#1(1 + main_#t~post83#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem82#1;havoc main_#t~post83#1;call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_#t~mem84#1.base, main_#t~mem84#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call write~$Pointer$#1(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem85#1.base, main_#t~mem85#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem85#1.base != 0 || main_#t~mem85#1.offset != 0;havoc main_#t~mem85#1.base, main_#t~mem85#1.offset;call main_#t~mem86#1.base, main_#t~mem86#1.offset := read~$Pointer$#1(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem86#1.base, 12 + main_#t~mem86#1.offset, 4);havoc main_#t~mem86#1.base, main_#t~mem86#1.offset;" "call write~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem88#1 := read~int#1(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem87#1 := read~int#1(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short91#1 := main_#t~mem88#1 % 4294967296 >= 10 * (1 + main_#t~mem87#1) % 4294967296;" "assume main_#t~short91#1;call main_#t~mem89#1.base, main_#t~mem89#1.offset := read~$Pointer$#1(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem90#1 := read~int#1(main_#t~mem89#1.base, 36 + main_#t~mem89#1.offset, 4);main_#t~short91#1 := 0 == main_#t~mem90#1 % 4294967296;" "assume !main_#t~short91#1;havoc main_#t~mem88#1;havoc main_#t~mem87#1;havoc main_#t~mem89#1.base, main_#t~mem89#1.offset;havoc main_#t~mem90#1;havoc main_#t~short91#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "main_#t~post156#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post156#1;havoc main_#t~post156#1;" [2025-02-06 20:14:36,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:36,587 INFO L85 PathProgramCache]: Analyzing trace with hash 12256, now seen corresponding path program 26 times [2025-02-06 20:14:36,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:36,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1875561242] [2025-02-06 20:14:36,587 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-06 20:14:36,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:36,590 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:36,590 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:36,590 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-06 20:14:36,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:36,590 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-06 20:14:36,592 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-06 20:14:36,592 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-06 20:14:36,592 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:36,592 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-06 20:14:36,600 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-06 20:14:36,600 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-06 20:14:36,600 INFO L85 PathProgramCache]: Analyzing trace with hash 595995455, now seen corresponding path program 1 times [2025-02-06 20:14:36,600 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-06 20:14:36,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254678053] [2025-02-06 20:14:36,600 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-06 20:14:36,601 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-06 20:14:36,620 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-06 20:14:36,651 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-06 20:14:36,651 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-06 20:14:36,651 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-06 20:14:48,313 WARN L286 SmtUtils]: Spent 11.43s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-02-06 20:14:54,592 WARN L286 SmtUtils]: Spent 6.28s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-02-06 20:15:06,614 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 39 (called from [L 388] de.uni_freiburg.informatik.ultimate.lib.modelcheckerutils.smt.predicates.PredicateUnifier.getOrConstructPredicate) [2025-02-06 20:15:18,624 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 26 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)