./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/bist_cell.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 551b0097 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/bist_cell.cil.c -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 --- Real Ultimate output --- This is Ultimate 0.3.0-?-551b009-m [2025-01-10 07:51:10,305 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-01-10 07:51:10,384 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-01-10 07:51:10,390 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-01-10 07:51:10,390 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-01-10 07:51:10,420 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-01-10 07:51:10,421 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-01-10 07:51:10,421 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-01-10 07:51:10,421 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-01-10 07:51:10,422 INFO L153 SettingsManager]: * Use memory slicer=true [2025-01-10 07:51:10,422 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-01-10 07:51:10,423 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-01-10 07:51:10,423 INFO L153 SettingsManager]: * Use SBE=true [2025-01-10 07:51:10,423 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-01-10 07:51:10,423 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-01-10 07:51:10,423 INFO L153 SettingsManager]: * Use old map elimination=false [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-01-10 07:51:10,424 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * sizeof long=4 [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * sizeof long double=12 [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-01-10 07:51:10,424 INFO L153 SettingsManager]: * Use constant arrays=true [2025-01-10 07:51:10,425 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2025-01-10 07:51:10,425 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-01-10 07:51:10,425 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-01-10 07:51:10,425 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-01-10 07:51:10,425 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-01-10 07:51:10,425 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> de455e90ef2ae1a82fb7a87bbcdb07831c7ef68e47976e1b2868a3e9de47a0a2 [2025-01-10 07:51:10,728 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-01-10 07:51:10,736 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-01-10 07:51:10,739 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-01-10 07:51:10,740 INFO L270 PluginConnector]: Initializing CDTParser... [2025-01-10 07:51:10,740 INFO L274 PluginConnector]: CDTParser initialized [2025-01-10 07:51:10,741 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/bist_cell.cil.c [2025-01-10 07:51:12,001 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/14163cb42/df1d92b85f42405b95545f5d638574fc/FLAG7d3f10a17 [2025-01-10 07:51:12,314 INFO L384 CDTParser]: Found 1 translation units. [2025-01-10 07:51:12,315 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/systemc/bist_cell.cil.c [2025-01-10 07:51:12,327 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/14163cb42/df1d92b85f42405b95545f5d638574fc/FLAG7d3f10a17 [2025-01-10 07:51:12,347 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/14163cb42/df1d92b85f42405b95545f5d638574fc [2025-01-10 07:51:12,351 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-01-10 07:51:12,353 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-01-10 07:51:12,354 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:12,354 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-01-10 07:51:12,358 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-01-10 07:51:12,359 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,360 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@418b241a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12, skipping insertion in model container [2025-01-10 07:51:12,361 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,389 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-01-10 07:51:12,585 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:12,600 INFO L200 MainTranslator]: Completed pre-run [2025-01-10 07:51:12,642 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-01-10 07:51:12,659 INFO L204 MainTranslator]: Completed translation [2025-01-10 07:51:12,661 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12 WrapperNode [2025-01-10 07:51:12,661 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-01-10 07:51:12,662 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:12,662 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-01-10 07:51:12,662 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-01-10 07:51:12,668 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,676 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,697 INFO L138 Inliner]: procedures = 30, calls = 31, calls flagged for inlining = 26, calls inlined = 32, statements flattened = 339 [2025-01-10 07:51:12,697 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-01-10 07:51:12,698 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-01-10 07:51:12,698 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-01-10 07:51:12,698 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-01-10 07:51:12,704 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,705 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,707 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,728 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-01-10 07:51:12,729 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,729 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,734 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,735 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,741 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,743 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,744 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,748 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-01-10 07:51:12,749 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2025-01-10 07:51:12,749 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2025-01-10 07:51:12,749 INFO L274 PluginConnector]: RCFGBuilder initialized [2025-01-10 07:51:12,750 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (1/1) ... [2025-01-10 07:51:12,755 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:12,767 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:12,781 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:12,789 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-01-10 07:51:12,808 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-01-10 07:51:12,808 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-01-10 07:51:12,808 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-01-10 07:51:12,808 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-01-10 07:51:12,868 INFO L234 CfgBuilder]: Building ICFG [2025-01-10 07:51:12,869 INFO L260 CfgBuilder]: Building CFG for each procedure with an implementation [2025-01-10 07:51:13,247 INFO L? ?]: Removed 36 outVars from TransFormulas that were not future-live. [2025-01-10 07:51:13,247 INFO L283 CfgBuilder]: Performing block encoding [2025-01-10 07:51:13,259 INFO L307 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-01-10 07:51:13,259 INFO L312 CfgBuilder]: Removed 2 assume(true) statements. [2025-01-10 07:51:13,259 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:13 BoogieIcfgContainer [2025-01-10 07:51:13,260 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2025-01-10 07:51:13,260 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-01-10 07:51:13,260 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-01-10 07:51:13,265 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-01-10 07:51:13,265 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:13,266 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 10.01 07:51:12" (1/3) ... [2025-01-10 07:51:13,267 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e041612 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:13, skipping insertion in model container [2025-01-10 07:51:13,267 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:13,267 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 10.01 07:51:12" (2/3) ... [2025-01-10 07:51:13,267 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7e041612 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 10.01 07:51:13, skipping insertion in model container [2025-01-10 07:51:13,267 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-01-10 07:51:13,267 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:13" (3/3) ... [2025-01-10 07:51:13,268 INFO L363 chiAutomizerObserver]: Analyzing ICFG bist_cell.cil.c [2025-01-10 07:51:13,323 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-01-10 07:51:13,323 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-01-10 07:51:13,323 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-01-10 07:51:13,323 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-01-10 07:51:13,323 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-01-10 07:51:13,324 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-01-10 07:51:13,324 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-01-10 07:51:13,324 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-01-10 07:51:13,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 124 states, 123 states have (on average 1.5772357723577235) internal successors, (194), 123 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:13,352 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:13,353 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:13,353 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:13,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,362 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-01-10 07:51:13,363 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 124 states, 123 states have (on average 1.5772357723577235) internal successors, (194), 123 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:13,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:13,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:13,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:13,371 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,371 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,376 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:13,377 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:13,381 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:13,382 INFO L85 PathProgramCache]: Analyzing trace with hash -1345002148, now seen corresponding path program 1 times [2025-01-10 07:51:13,388 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:13,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1503964162] [2025-01-10 07:51:13,389 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:13,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:13,455 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-01-10 07:51:13,472 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-01-10 07:51:13,473 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:13,473 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:13,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:13,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:13,586 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1503964162] [2025-01-10 07:51:13,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1503964162] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:13,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:13,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:13,588 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [931512167] [2025-01-10 07:51:13,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:13,592 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:13,594 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:13,595 INFO L85 PathProgramCache]: Analyzing trace with hash -902133627, now seen corresponding path program 1 times [2025-01-10 07:51:13,595 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:13,595 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1821574613] [2025-01-10 07:51:13,595 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:13,595 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:13,608 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 33 statements into 1 equivalence classes. [2025-01-10 07:51:13,610 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 33 of 33 statements. [2025-01-10 07:51:13,613 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:13,613 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:13,631 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:13,631 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:13,631 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1821574613] [2025-01-10 07:51:13,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1821574613] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:13,631 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:13,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:13,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124359869] [2025-01-10 07:51:13,632 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:13,633 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:13,635 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:13,662 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:13,662 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:13,665 INFO L87 Difference]: Start difference. First operand has 124 states, 123 states have (on average 1.5772357723577235) internal successors, (194), 123 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:13,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:13,705 INFO L93 Difference]: Finished difference Result 122 states and 188 transitions. [2025-01-10 07:51:13,709 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 122 states and 188 transitions. [2025-01-10 07:51:13,711 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:13,722 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 122 states to 115 states and 181 transitions. [2025-01-10 07:51:13,724 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-01-10 07:51:13,725 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-01-10 07:51:13,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 181 transitions. [2025-01-10 07:51:13,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:13,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 181 transitions. [2025-01-10 07:51:13,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 181 transitions. [2025-01-10 07:51:13,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2025-01-10 07:51:13,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.5739130434782609) internal successors, (181), 114 states have internal predecessors, (181), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:13,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 181 transitions. [2025-01-10 07:51:13,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 181 transitions. [2025-01-10 07:51:13,762 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:13,765 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 181 transitions. [2025-01-10 07:51:13,765 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-01-10 07:51:13,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 181 transitions. [2025-01-10 07:51:13,770 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:13,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:13,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:13,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:13,772 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume !(~b0_val~0 != ~b0_val_t~0);" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:13,772 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:13,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:13,775 INFO L85 PathProgramCache]: Analyzing trace with hash -1840469421, now seen corresponding path program 1 times [2025-01-10 07:51:13,776 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:13,776 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1568787626] [2025-01-10 07:51:13,776 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:13,776 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:13,790 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-01-10 07:51:13,806 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-01-10 07:51:13,807 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:13,807 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:13,939 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:13,940 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:13,940 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1568787626] [2025-01-10 07:51:13,940 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1568787626] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:13,940 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:13,940 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:13,940 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [828443925] [2025-01-10 07:51:13,940 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:13,941 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:13,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:13,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1263709366, now seen corresponding path program 1 times [2025-01-10 07:51:13,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:13,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658307087] [2025-01-10 07:51:13,942 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:13,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:13,950 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:13,957 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:13,958 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:13,958 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,045 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658307087] [2025-01-10 07:51:14,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658307087] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:14,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2122955453] [2025-01-10 07:51:14,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,046 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:14,046 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:14,046 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:14,046 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:14,047 INFO L87 Difference]: Start difference. First operand 115 states and 181 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:14,078 INFO L93 Difference]: Finished difference Result 115 states and 180 transitions. [2025-01-10 07:51:14,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 180 transitions. [2025-01-10 07:51:14,079 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 180 transitions. [2025-01-10 07:51:14,081 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-01-10 07:51:14,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-01-10 07:51:14,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 180 transitions. [2025-01-10 07:51:14,082 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:14,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 180 transitions. [2025-01-10 07:51:14,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 180 transitions. [2025-01-10 07:51:14,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2025-01-10 07:51:14,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.565217391304348) internal successors, (180), 114 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 180 transitions. [2025-01-10 07:51:14,087 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 180 transitions. [2025-01-10 07:51:14,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:14,089 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 180 transitions. [2025-01-10 07:51:14,089 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-01-10 07:51:14,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 180 transitions. [2025-01-10 07:51:14,090 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:14,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:14,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,091 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:14,092 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:14,093 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,093 INFO L85 PathProgramCache]: Analyzing trace with hash 531269841, now seen corresponding path program 1 times [2025-01-10 07:51:14,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,093 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255122602] [2025-01-10 07:51:14,093 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:14,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,101 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-01-10 07:51:14,107 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-01-10 07:51:14,107 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,108 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255122602] [2025-01-10 07:51:14,147 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255122602] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,147 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,147 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:14,147 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224099656] [2025-01-10 07:51:14,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,148 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:14,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,148 INFO L85 PathProgramCache]: Analyzing trace with hash 1263709366, now seen corresponding path program 2 times [2025-01-10 07:51:14,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148576242] [2025-01-10 07:51:14,148 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:14,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,162 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,173 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,174 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:14,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,216 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,217 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1148576242] [2025-01-10 07:51:14,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1148576242] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:14,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1297283928] [2025-01-10 07:51:14,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,218 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:14,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:14,220 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:14,220 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:14,220 INFO L87 Difference]: Start difference. First operand 115 states and 180 transitions. cyclomatic complexity: 66 Second operand has 3 states, 3 states have (on average 10.333333333333334) internal successors, (31), 3 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:14,246 INFO L93 Difference]: Finished difference Result 115 states and 179 transitions. [2025-01-10 07:51:14,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 179 transitions. [2025-01-10 07:51:14,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,248 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 179 transitions. [2025-01-10 07:51:14,248 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-01-10 07:51:14,249 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-01-10 07:51:14,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 179 transitions. [2025-01-10 07:51:14,249 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:14,249 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 179 transitions. [2025-01-10 07:51:14,250 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 179 transitions. [2025-01-10 07:51:14,253 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2025-01-10 07:51:14,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.5565217391304347) internal successors, (179), 114 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,254 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 179 transitions. [2025-01-10 07:51:14,254 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 179 transitions. [2025-01-10 07:51:14,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:14,255 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 179 transitions. [2025-01-10 07:51:14,255 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-01-10 07:51:14,255 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 179 transitions. [2025-01-10 07:51:14,256 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:14,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:14,257 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,257 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,258 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume !(~b1_val~0 != ~b1_val_t~0);" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:14,258 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:14,258 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,258 INFO L85 PathProgramCache]: Analyzing trace with hash 1296388927, now seen corresponding path program 1 times [2025-01-10 07:51:14,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1831779559] [2025-01-10 07:51:14,259 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:14,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,265 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:14,268 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:14,268 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,352 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,352 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1831779559] [2025-01-10 07:51:14,352 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1831779559] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,352 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,352 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:14,352 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1879446131] [2025-01-10 07:51:14,352 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,352 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:14,353 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,353 INFO L85 PathProgramCache]: Analyzing trace with hash 1263709366, now seen corresponding path program 3 times [2025-01-10 07:51:14,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [828216152] [2025-01-10 07:51:14,353 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:14,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,363 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,371 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,372 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:14,372 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,422 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [828216152] [2025-01-10 07:51:14,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [828216152] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:14,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [620604823] [2025-01-10 07:51:14,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,424 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:14,424 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:14,424 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:14,425 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:14,425 INFO L87 Difference]: Start difference. First operand 115 states and 179 transitions. cyclomatic complexity: 65 Second operand has 4 states, 4 states have (on average 8.5) internal successors, (34), 4 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:14,479 INFO L93 Difference]: Finished difference Result 115 states and 178 transitions. [2025-01-10 07:51:14,479 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 178 transitions. [2025-01-10 07:51:14,481 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,482 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 178 transitions. [2025-01-10 07:51:14,484 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-01-10 07:51:14,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-01-10 07:51:14,484 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 178 transitions. [2025-01-10 07:51:14,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:14,485 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 178 transitions. [2025-01-10 07:51:14,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 178 transitions. [2025-01-10 07:51:14,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2025-01-10 07:51:14,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.5478260869565217) internal successors, (178), 114 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 178 transitions. [2025-01-10 07:51:14,490 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 178 transitions. [2025-01-10 07:51:14,490 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:14,491 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 178 transitions. [2025-01-10 07:51:14,491 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-01-10 07:51:14,491 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 178 transitions. [2025-01-10 07:51:14,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,495 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:14,495 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:14,496 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,496 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,497 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:14,497 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:14,497 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,497 INFO L85 PathProgramCache]: Analyzing trace with hash 1234349313, now seen corresponding path program 1 times [2025-01-10 07:51:14,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [876573600] [2025-01-10 07:51:14,497 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:14,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 34 statements into 1 equivalence classes. [2025-01-10 07:51:14,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 34 of 34 statements. [2025-01-10 07:51:14,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,538 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,539 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,539 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [876573600] [2025-01-10 07:51:14,539 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [876573600] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,539 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,540 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:14,540 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980156369] [2025-01-10 07:51:14,540 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,540 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:14,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,540 INFO L85 PathProgramCache]: Analyzing trace with hash 1263709366, now seen corresponding path program 4 times [2025-01-10 07:51:14,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,540 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1537813862] [2025-01-10 07:51:14,541 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:51:14,541 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,549 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 37 statements into 2 equivalence classes. [2025-01-10 07:51:14,552 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,552 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-01-10 07:51:14,552 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1537813862] [2025-01-10 07:51:14,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1537813862] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,597 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:14,597 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256400107] [2025-01-10 07:51:14,597 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,598 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:14,598 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:14,598 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:14,599 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:14,599 INFO L87 Difference]: Start difference. First operand 115 states and 178 transitions. cyclomatic complexity: 64 Second operand has 3 states, 3 states have (on average 11.333333333333334) internal successors, (34), 3 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:14,616 INFO L93 Difference]: Finished difference Result 115 states and 177 transitions. [2025-01-10 07:51:14,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 115 states and 177 transitions. [2025-01-10 07:51:14,617 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 115 states to 115 states and 177 transitions. [2025-01-10 07:51:14,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 115 [2025-01-10 07:51:14,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 115 [2025-01-10 07:51:14,619 INFO L73 IsDeterministic]: Start isDeterministic. Operand 115 states and 177 transitions. [2025-01-10 07:51:14,620 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:14,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 115 states and 177 transitions. [2025-01-10 07:51:14,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states and 177 transitions. [2025-01-10 07:51:14,629 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 115. [2025-01-10 07:51:14,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 115 states, 115 states have (on average 1.5391304347826087) internal successors, (177), 114 states have internal predecessors, (177), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 115 states to 115 states and 177 transitions. [2025-01-10 07:51:14,630 INFO L240 hiAutomatonCegarLoop]: Abstraction has 115 states and 177 transitions. [2025-01-10 07:51:14,631 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:14,632 INFO L432 stractBuchiCegarLoop]: Abstraction has 115 states and 177 transitions. [2025-01-10 07:51:14,632 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-01-10 07:51:14,632 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 115 states and 177 transitions. [2025-01-10 07:51:14,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 69 [2025-01-10 07:51:14,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:14,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:14,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,634 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume !(~d0_val~0 != ~d0_val_t~0);" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:14,634 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:14,635 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,635 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 1 times [2025-01-10 07:51:14,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550357549] [2025-01-10 07:51:14,635 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:14,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,652 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,653 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,653 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550357549] [2025-01-10 07:51:14,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550357549] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,736 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,736 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:14,736 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [445465590] [2025-01-10 07:51:14,736 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,737 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:14,738 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1263709366, now seen corresponding path program 5 times [2025-01-10 07:51:14,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [471906001] [2025-01-10 07:51:14,739 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:51:14,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,756 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,761 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,761 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:14,761 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,806 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [471906001] [2025-01-10 07:51:14,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [471906001] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,807 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,807 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-01-10 07:51:14,807 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855263527] [2025-01-10 07:51:14,807 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,810 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:14,810 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:14,811 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-01-10 07:51:14,811 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-01-10 07:51:14,812 INFO L87 Difference]: Start difference. First operand 115 states and 177 transitions. cyclomatic complexity: 63 Second operand has 5 states, 5 states have (on average 7.4) internal successors, (37), 5 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:14,852 INFO L93 Difference]: Finished difference Result 120 states and 182 transitions. [2025-01-10 07:51:14,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 182 transitions. [2025-01-10 07:51:14,853 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 74 [2025-01-10 07:51:14,854 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 120 states and 182 transitions. [2025-01-10 07:51:14,854 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 120 [2025-01-10 07:51:14,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 120 [2025-01-10 07:51:14,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 120 states and 182 transitions. [2025-01-10 07:51:14,855 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-01-10 07:51:14,855 INFO L218 hiAutomatonCegarLoop]: Abstraction has 120 states and 182 transitions. [2025-01-10 07:51:14,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 120 states and 182 transitions. [2025-01-10 07:51:14,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 120 to 118. [2025-01-10 07:51:14,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118 states, 118 states have (on average 1.5254237288135593) internal successors, (180), 117 states have internal predecessors, (180), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:14,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 180 transitions. [2025-01-10 07:51:14,866 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118 states and 180 transitions. [2025-01-10 07:51:14,866 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:14,868 INFO L432 stractBuchiCegarLoop]: Abstraction has 118 states and 180 transitions. [2025-01-10 07:51:14,869 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-01-10 07:51:14,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118 states and 180 transitions. [2025-01-10 07:51:14,870 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 72 [2025-01-10 07:51:14,870 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:14,870 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:14,871 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,871 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:14,871 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume !(~d0_val~0 != ~d0_val_t~0);" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-01-10 07:51:14,871 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume !(0 == ~comp_m1_st~0);exists_runnable_thread_~__retres1~1#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp___0~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~b0_req_up~0);" "assume !(1 == ~b1_req_up~0);" "assume !(1 == ~d0_req_up~0);" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume 0 == ~z_ev~0;~z_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume 1 == ~z_ev~0;~z_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "stop_simulation_#t~ret7#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret7#1;havoc stop_simulation_#t~ret7#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret8#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret7#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret8#1;havoc start_simulation_#t~ret8#1;" "assume !(0 != start_simulation_~tmp~3#1);" [2025-01-10 07:51:14,875 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,875 INFO L85 PathProgramCache]: Analyzing trace with hash -2115080082, now seen corresponding path program 2 times [2025-01-10 07:51:14,875 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1544703004] [2025-01-10 07:51:14,875 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:14,876 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,882 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,886 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,888 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:14,889 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:14,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:14,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:14,932 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1544703004] [2025-01-10 07:51:14,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1544703004] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:14,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:14,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:14,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1855997789] [2025-01-10 07:51:14,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:14,933 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:14,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:14,934 INFO L85 PathProgramCache]: Analyzing trace with hash 419703864, now seen corresponding path program 1 times [2025-01-10 07:51:14,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:14,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239490881] [2025-01-10 07:51:14,934 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:14,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:14,939 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,945 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,946 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,946 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:14,946 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:14,948 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:14,953 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:14,953 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:14,953 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:14,976 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:15,384 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:51:15,385 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:51:15,386 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:51:15,386 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:51:15,386 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-01-10 07:51:15,386 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:15,386 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:51:15,386 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:51:15,386 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration7_Loop [2025-01-10 07:51:15,386 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:51:15,388 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:51:15,403 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,410 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,416 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,422 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,438 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,443 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,460 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,466 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,472 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,474 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,477 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,484 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,486 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,488 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,491 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,687 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:51:15,687 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-01-10 07:51:15,689 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:15,689 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:15,692 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:15,695 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-01-10 07:51:15,696 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:51:15,696 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:51:15,712 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-01-10 07:51:15,713 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-01-10 07:51:15,720 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-01-10 07:51:15,720 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:15,721 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:15,722 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:15,723 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-01-10 07:51:15,725 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-01-10 07:51:15,725 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:51:15,745 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-01-10 07:51:15,745 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:15,745 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:15,747 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:15,749 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-01-10 07:51:15,750 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-01-10 07:51:15,750 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-01-10 07:51:15,773 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-01-10 07:51:15,781 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-01-10 07:51:15,781 INFO L204 LassoAnalysis]: Preferences: [2025-01-10 07:51:15,781 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-01-10 07:51:15,781 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-01-10 07:51:15,781 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-01-10 07:51:15,781 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-01-10 07:51:15,781 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:15,781 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-01-10 07:51:15,781 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-01-10 07:51:15,781 INFO L132 ssoRankerPreferences]: Filename of dumped script: bist_cell.cil.c_Iteration7_Loop [2025-01-10 07:51:15,781 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-01-10 07:51:15,781 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-01-10 07:51:15,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,874 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:15,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-01-10 07:51:16,067 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-01-10 07:51:16,071 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-01-10 07:51:16,072 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:16,072 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:16,074 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:16,077 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-01-10 07:51:16,078 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:51:16,091 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:51:16,091 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:51:16,092 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:51:16,092 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:51:16,092 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:51:16,097 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:51:16,098 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:51:16,102 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:51:16,109 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-01-10 07:51:16,110 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:16,110 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:16,112 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:16,116 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-01-10 07:51:16,116 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:51:16,128 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:51:16,129 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:51:16,129 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:51:16,129 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:51:16,129 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:51:16,130 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:51:16,130 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:51:16,131 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:51:16,139 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-01-10 07:51:16,139 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:16,139 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:16,142 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:16,144 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-01-10 07:51:16,145 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:51:16,157 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:51:16,158 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:51:16,158 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:51:16,158 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:51:16,158 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:51:16,159 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:51:16,159 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:51:16,162 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-01-10 07:51:16,170 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-01-10 07:51:16,171 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:16,171 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:16,173 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:16,176 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-01-10 07:51:16,177 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-01-10 07:51:16,190 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-01-10 07:51:16,190 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-01-10 07:51:16,190 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-01-10 07:51:16,190 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-01-10 07:51:16,190 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-01-10 07:51:16,192 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-01-10 07:51:16,192 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-01-10 07:51:16,197 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-01-10 07:51:16,200 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-01-10 07:51:16,202 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-01-10 07:51:16,204 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-01-10 07:51:16,204 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-01-10 07:51:16,209 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-01-10 07:51:16,213 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-01-10 07:51:16,213 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-01-10 07:51:16,218 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-01-10 07:51:16,218 INFO L474 LassoAnalysis]: Proved termination. [2025-01-10 07:51:16,218 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~d1_ev~0) = -1*~d1_ev~0 + 1 Supporting invariants [] [2025-01-10 07:51:16,228 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2025-01-10 07:51:16,230 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-01-10 07:51:16,256 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,271 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:16,291 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:16,291 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,294 INFO L256 TraceCheckSpWp]: Trace formula consists of 170 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-01-10 07:51:16,295 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:51:16,371 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-01-10 07:51:16,384 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-01-10 07:51:16,384 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,384 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,385 INFO L256 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-01-10 07:51:16,386 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-01-10 07:51:16,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:16,517 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-01-10 07:51:16,519 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 118 states and 180 transitions. cyclomatic complexity: 63 Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,588 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 118 states and 180 transitions. cyclomatic complexity: 63. Second operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 268 states and 416 transitions. Complement of second has 5 states. [2025-01-10 07:51:16,610 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-01-10 07:51:16,612 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 14.8) internal successors, (74), 5 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 181 transitions. [2025-01-10 07:51:16,615 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 37 letters. Loop has 37 letters. [2025-01-10 07:51:16,618 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-01-10 07:51:16,619 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:51:16,619 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 74 letters. Loop has 37 letters. [2025-01-10 07:51:16,619 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:51:16,620 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 181 transitions. Stem has 37 letters. Loop has 74 letters. [2025-01-10 07:51:16,622 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-01-10 07:51:16,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 268 states and 416 transitions. [2025-01-10 07:51:16,626 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 144 [2025-01-10 07:51:16,628 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 268 states to 268 states and 416 transitions. [2025-01-10 07:51:16,628 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191 [2025-01-10 07:51:16,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 194 [2025-01-10 07:51:16,629 INFO L73 IsDeterministic]: Start isDeterministic. Operand 268 states and 416 transitions. [2025-01-10 07:51:16,629 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:16,629 INFO L218 hiAutomatonCegarLoop]: Abstraction has 268 states and 416 transitions. [2025-01-10 07:51:16,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 268 states and 416 transitions. [2025-01-10 07:51:16,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 268 to 265. [2025-01-10 07:51:16,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 265 states, 265 states have (on average 1.558490566037736) internal successors, (413), 264 states have internal predecessors, (413), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,641 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 413 transitions. [2025-01-10 07:51:16,641 INFO L240 hiAutomatonCegarLoop]: Abstraction has 265 states and 413 transitions. [2025-01-10 07:51:16,641 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:16,645 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:16,645 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:16,645 INFO L87 Difference]: Start difference. First operand 265 states and 413 transitions. Second operand has 4 states, 4 states have (on average 9.25) internal successors, (37), 4 states have internal predecessors, (37), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:16,680 INFO L93 Difference]: Finished difference Result 265 states and 412 transitions. [2025-01-10 07:51:16,680 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 265 states and 412 transitions. [2025-01-10 07:51:16,685 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 144 [2025-01-10 07:51:16,686 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 265 states to 265 states and 412 transitions. [2025-01-10 07:51:16,686 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 191 [2025-01-10 07:51:16,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 191 [2025-01-10 07:51:16,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 265 states and 412 transitions. [2025-01-10 07:51:16,687 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:16,687 INFO L218 hiAutomatonCegarLoop]: Abstraction has 265 states and 412 transitions. [2025-01-10 07:51:16,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states and 412 transitions. [2025-01-10 07:51:16,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 265. [2025-01-10 07:51:16,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 265 states, 265 states have (on average 1.5547169811320756) internal successors, (412), 264 states have internal predecessors, (412), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,696 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 412 transitions. [2025-01-10 07:51:16,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 265 states and 412 transitions. [2025-01-10 07:51:16,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:16,697 INFO L432 stractBuchiCegarLoop]: Abstraction has 265 states and 412 transitions. [2025-01-10 07:51:16,697 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-01-10 07:51:16,697 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 265 states and 412 transitions. [2025-01-10 07:51:16,699 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 144 [2025-01-10 07:51:16,699 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:16,699 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:16,699 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,700 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,700 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:16,700 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume !(0 == ~comp_m1_st~0);" [2025-01-10 07:51:16,700 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,700 INFO L85 PathProgramCache]: Analyzing trace with hash -1205012526, now seen corresponding path program 1 times [2025-01-10 07:51:16,700 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,700 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588472432] [2025-01-10 07:51:16,700 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:16,702 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,708 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-01-10 07:51:16,712 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-01-10 07:51:16,712 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,712 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,739 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:16,739 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:16,739 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [588472432] [2025-01-10 07:51:16,739 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [588472432] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:16,739 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:16,740 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:16,740 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [963678104] [2025-01-10 07:51:16,740 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:16,740 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:16,740 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,740 INFO L85 PathProgramCache]: Analyzing trace with hash -1930668783, now seen corresponding path program 1 times [2025-01-10 07:51:16,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1051560185] [2025-01-10 07:51:16,740 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:16,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,742 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-01-10 07:51:16,743 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-01-10 07:51:16,743 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:16,751 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:16,751 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1051560185] [2025-01-10 07:51:16,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1051560185] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:16,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:16,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-01-10 07:51:16,751 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1198613271] [2025-01-10 07:51:16,751 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:16,752 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-01-10 07:51:16,752 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:16,752 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:16,752 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:16,752 INFO L87 Difference]: Start difference. First operand 265 states and 412 transitions. cyclomatic complexity: 150 Second operand has 3 states, 2 states have (on average 3.0) internal successors, (6), 3 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:16,783 INFO L93 Difference]: Finished difference Result 342 states and 525 transitions. [2025-01-10 07:51:16,783 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 525 transitions. [2025-01-10 07:51:16,785 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:16,789 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 525 transitions. [2025-01-10 07:51:16,789 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 249 [2025-01-10 07:51:16,790 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 249 [2025-01-10 07:51:16,790 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 525 transitions. [2025-01-10 07:51:16,790 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:16,790 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 525 transitions. [2025-01-10 07:51:16,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 525 transitions. [2025-01-10 07:51:16,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2025-01-10 07:51:16,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 342 states have (on average 1.5350877192982457) internal successors, (525), 341 states have internal predecessors, (525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 525 transitions. [2025-01-10 07:51:16,798 INFO L240 hiAutomatonCegarLoop]: Abstraction has 342 states and 525 transitions. [2025-01-10 07:51:16,799 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:16,800 INFO L432 stractBuchiCegarLoop]: Abstraction has 342 states and 525 transitions. [2025-01-10 07:51:16,800 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-01-10 07:51:16,800 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 525 transitions. [2025-01-10 07:51:16,802 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:16,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:16,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:16,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,804 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume !(1 == ~d1_req_up~0);" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:16,805 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:16,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,805 INFO L85 PathProgramCache]: Analyzing trace with hash -387364076, now seen corresponding path program 1 times [2025-01-10 07:51:16,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1392165721] [2025-01-10 07:51:16,805 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:16,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,811 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 38 statements into 1 equivalence classes. [2025-01-10 07:51:16,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 38 of 38 statements. [2025-01-10 07:51:16,814 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,814 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,847 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:16,847 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:16,847 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1392165721] [2025-01-10 07:51:16,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1392165721] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:16,847 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:16,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:16,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998491842] [2025-01-10 07:51:16,847 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:16,848 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:16,848 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,848 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 1 times [2025-01-10 07:51:16,848 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,848 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [457565229] [2025-01-10 07:51:16,848 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:16,848 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,850 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:16,852 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:16,852 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,853 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:16,853 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:16,853 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:16,854 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:16,854 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,854 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:16,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:16,882 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:16,883 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:16,883 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:16,883 INFO L87 Difference]: Start difference. First operand 342 states and 525 transitions. cyclomatic complexity: 186 Second operand has 3 states, 3 states have (on average 12.666666666666666) internal successors, (38), 3 states have internal predecessors, (38), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,893 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:16,893 INFO L93 Difference]: Finished difference Result 342 states and 524 transitions. [2025-01-10 07:51:16,894 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 524 transitions. [2025-01-10 07:51:16,896 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:16,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 524 transitions. [2025-01-10 07:51:16,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 249 [2025-01-10 07:51:16,898 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 249 [2025-01-10 07:51:16,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 524 transitions. [2025-01-10 07:51:16,899 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:16,899 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 524 transitions. [2025-01-10 07:51:16,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 524 transitions. [2025-01-10 07:51:16,903 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2025-01-10 07:51:16,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 342 states have (on average 1.5321637426900585) internal successors, (524), 341 states have internal predecessors, (524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:16,907 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 524 transitions. [2025-01-10 07:51:16,907 INFO L240 hiAutomatonCegarLoop]: Abstraction has 342 states and 524 transitions. [2025-01-10 07:51:16,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:16,911 INFO L432 stractBuchiCegarLoop]: Abstraction has 342 states and 524 transitions. [2025-01-10 07:51:16,911 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-01-10 07:51:16,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 524 transitions. [2025-01-10 07:51:16,913 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:16,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:16,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:16,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:16,914 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume !(~d1_val~0 != ~d1_val_t~0);" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:16,914 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:16,915 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1708940444, now seen corresponding path program 1 times [2025-01-10 07:51:16,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [689043147] [2025-01-10 07:51:16,915 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:16,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,921 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:16,923 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:16,923 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,923 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:16,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:16,968 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:16,968 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [689043147] [2025-01-10 07:51:16,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [689043147] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:16,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:16,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:16,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [501544240] [2025-01-10 07:51:16,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:16,968 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:16,968 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:16,969 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 2 times [2025-01-10 07:51:16,969 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:16,969 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700415597] [2025-01-10 07:51:16,969 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:16,969 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:16,971 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:16,971 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:16,971 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:16,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:16,971 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:16,972 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:16,973 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:16,973 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:16,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:16,974 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:16,996 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:16,996 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:16,996 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:16,996 INFO L87 Difference]: Start difference. First operand 342 states and 524 transitions. cyclomatic complexity: 185 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,031 INFO L93 Difference]: Finished difference Result 342 states and 523 transitions. [2025-01-10 07:51:17,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 342 states and 523 transitions. [2025-01-10 07:51:17,034 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:17,036 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 342 states to 342 states and 523 transitions. [2025-01-10 07:51:17,036 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 249 [2025-01-10 07:51:17,036 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 249 [2025-01-10 07:51:17,036 INFO L73 IsDeterministic]: Start isDeterministic. Operand 342 states and 523 transitions. [2025-01-10 07:51:17,037 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,037 INFO L218 hiAutomatonCegarLoop]: Abstraction has 342 states and 523 transitions. [2025-01-10 07:51:17,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 342 states and 523 transitions. [2025-01-10 07:51:17,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 342 to 342. [2025-01-10 07:51:17,042 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 342 states, 342 states have (on average 1.5292397660818713) internal successors, (523), 341 states have internal predecessors, (523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 342 states to 342 states and 523 transitions. [2025-01-10 07:51:17,043 INFO L240 hiAutomatonCegarLoop]: Abstraction has 342 states and 523 transitions. [2025-01-10 07:51:17,044 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-01-10 07:51:17,044 INFO L432 stractBuchiCegarLoop]: Abstraction has 342 states and 523 transitions. [2025-01-10 07:51:17,044 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-01-10 07:51:17,044 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 342 states and 523 transitions. [2025-01-10 07:51:17,048 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:17,048 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,048 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,049 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,049 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,049 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~comp_m1_i~0;~comp_m1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume !(0 != activate_threads_~tmp~1#1);" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,049 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,049 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,049 INFO L85 PathProgramCache]: Analyzing trace with hash 1568391834, now seen corresponding path program 1 times [2025-01-10 07:51:17,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [109162952] [2025-01-10 07:51:17,049 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,058 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,060 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,060 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,060 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,125 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,125 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,125 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [109162952] [2025-01-10 07:51:17,125 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [109162952] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,126 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-01-10 07:51:17,126 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [552345960] [2025-01-10 07:51:17,126 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,126 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,127 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 3 times [2025-01-10 07:51:17,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1410862355] [2025-01-10 07:51:17,127 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:17,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,129 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,130 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,130 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:17,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,130 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,131 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,132 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,132 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,132 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,154 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,155 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-01-10 07:51:17,155 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-01-10 07:51:17,155 INFO L87 Difference]: Start difference. First operand 342 states and 523 transitions. cyclomatic complexity: 184 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,177 INFO L93 Difference]: Finished difference Result 328 states and 498 transitions. [2025-01-10 07:51:17,177 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 328 states and 498 transitions. [2025-01-10 07:51:17,179 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:17,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 328 states to 328 states and 498 transitions. [2025-01-10 07:51:17,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 235 [2025-01-10 07:51:17,183 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 235 [2025-01-10 07:51:17,183 INFO L73 IsDeterministic]: Start isDeterministic. Operand 328 states and 498 transitions. [2025-01-10 07:51:17,183 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,183 INFO L218 hiAutomatonCegarLoop]: Abstraction has 328 states and 498 transitions. [2025-01-10 07:51:17,183 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 328 states and 498 transitions. [2025-01-10 07:51:17,193 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 328 to 328. [2025-01-10 07:51:17,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 328 states, 328 states have (on average 1.5182926829268293) internal successors, (498), 327 states have internal predecessors, (498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,199 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 328 states to 328 states and 498 transitions. [2025-01-10 07:51:17,199 INFO L240 hiAutomatonCegarLoop]: Abstraction has 328 states and 498 transitions. [2025-01-10 07:51:17,200 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-01-10 07:51:17,201 INFO L432 stractBuchiCegarLoop]: Abstraction has 328 states and 498 transitions. [2025-01-10 07:51:17,201 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-01-10 07:51:17,201 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 328 states and 498 transitions. [2025-01-10 07:51:17,203 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 180 [2025-01-10 07:51:17,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,205 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~b0_ev~0);" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,206 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,206 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,206 INFO L85 PathProgramCache]: Analyzing trace with hash 70685014, now seen corresponding path program 1 times [2025-01-10 07:51:17,206 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198699574] [2025-01-10 07:51:17,207 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,212 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,214 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,214 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,214 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,238 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,238 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,238 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198699574] [2025-01-10 07:51:17,238 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198699574] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,238 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,238 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,238 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462295792] [2025-01-10 07:51:17,239 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,239 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,239 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,239 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 4 times [2025-01-10 07:51:17,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265714235] [2025-01-10 07:51:17,239 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:51:17,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,242 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 7 statements into 2 equivalence classes. [2025-01-10 07:51:17,243 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,244 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:51:17,244 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,244 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,245 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,247 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,247 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,247 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,249 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,274 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,274 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,275 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,275 INFO L87 Difference]: Start difference. First operand 328 states and 498 transitions. cyclomatic complexity: 173 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,302 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,302 INFO L93 Difference]: Finished difference Result 388 states and 580 transitions. [2025-01-10 07:51:17,302 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388 states and 580 transitions. [2025-01-10 07:51:17,305 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 220 [2025-01-10 07:51:17,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388 states to 388 states and 580 transitions. [2025-01-10 07:51:17,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 275 [2025-01-10 07:51:17,308 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 275 [2025-01-10 07:51:17,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388 states and 580 transitions. [2025-01-10 07:51:17,308 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,308 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388 states and 580 transitions. [2025-01-10 07:51:17,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388 states and 580 transitions. [2025-01-10 07:51:17,315 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388 to 388. [2025-01-10 07:51:17,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 388 states, 388 states have (on average 1.4948453608247423) internal successors, (580), 387 states have internal predecessors, (580), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 388 states to 388 states and 580 transitions. [2025-01-10 07:51:17,318 INFO L240 hiAutomatonCegarLoop]: Abstraction has 388 states and 580 transitions. [2025-01-10 07:51:17,318 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,319 INFO L432 stractBuchiCegarLoop]: Abstraction has 388 states and 580 transitions. [2025-01-10 07:51:17,319 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-01-10 07:51:17,319 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 388 states and 580 transitions. [2025-01-10 07:51:17,321 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 220 [2025-01-10 07:51:17,321 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,322 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,322 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,323 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume !(0 == ~b1_ev~0);" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,323 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,323 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,323 INFO L85 PathProgramCache]: Analyzing trace with hash 2064829720, now seen corresponding path program 1 times [2025-01-10 07:51:17,323 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,323 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1398557059] [2025-01-10 07:51:17,324 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,329 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,332 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,332 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,332 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1398557059] [2025-01-10 07:51:17,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1398557059] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,357 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461687366] [2025-01-10 07:51:17,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,357 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,357 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 5 times [2025-01-10 07:51:17,357 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888063738] [2025-01-10 07:51:17,358 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-01-10 07:51:17,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,360 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,361 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,361 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:17,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,361 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,363 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,363 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,363 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,366 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,391 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,391 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,391 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,391 INFO L87 Difference]: Start difference. First operand 388 states and 580 transitions. cyclomatic complexity: 195 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,420 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,420 INFO L93 Difference]: Finished difference Result 487 states and 715 transitions. [2025-01-10 07:51:17,420 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 487 states and 715 transitions. [2025-01-10 07:51:17,424 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 286 [2025-01-10 07:51:17,426 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 487 states to 487 states and 715 transitions. [2025-01-10 07:51:17,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 341 [2025-01-10 07:51:17,427 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 341 [2025-01-10 07:51:17,427 INFO L73 IsDeterministic]: Start isDeterministic. Operand 487 states and 715 transitions. [2025-01-10 07:51:17,427 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,427 INFO L218 hiAutomatonCegarLoop]: Abstraction has 487 states and 715 transitions. [2025-01-10 07:51:17,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 487 states and 715 transitions. [2025-01-10 07:51:17,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 487 to 487. [2025-01-10 07:51:17,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 487 states, 487 states have (on average 1.4681724845995894) internal successors, (715), 486 states have internal predecessors, (715), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 487 states to 487 states and 715 transitions. [2025-01-10 07:51:17,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 487 states and 715 transitions. [2025-01-10 07:51:17,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,439 INFO L432 stractBuchiCegarLoop]: Abstraction has 487 states and 715 transitions. [2025-01-10 07:51:17,439 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-01-10 07:51:17,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 487 states and 715 transitions. [2025-01-10 07:51:17,442 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 286 [2025-01-10 07:51:17,442 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,442 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,442 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,442 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume !(0 == ~d0_ev~0);" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,442 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,443 INFO L85 PathProgramCache]: Analyzing trace with hash -641789674, now seen corresponding path program 1 times [2025-01-10 07:51:17,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [262069655] [2025-01-10 07:51:17,443 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,449 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,456 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,456 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,474 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,474 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,474 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [262069655] [2025-01-10 07:51:17,474 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [262069655] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,474 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,474 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,475 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24775669] [2025-01-10 07:51:17,475 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,477 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,477 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 6 times [2025-01-10 07:51:17,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [14567369] [2025-01-10 07:51:17,477 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-01-10 07:51:17,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,480 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,481 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,482 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-01-10 07:51:17,482 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,482 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,484 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,484 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,485 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,507 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,507 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,507 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,508 INFO L87 Difference]: Start difference. First operand 487 states and 715 transitions. cyclomatic complexity: 231 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,532 INFO L93 Difference]: Finished difference Result 640 states and 920 transitions. [2025-01-10 07:51:17,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 640 states and 920 transitions. [2025-01-10 07:51:17,536 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2025-01-10 07:51:17,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 640 states to 640 states and 920 transitions. [2025-01-10 07:51:17,539 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 443 [2025-01-10 07:51:17,540 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 443 [2025-01-10 07:51:17,540 INFO L73 IsDeterministic]: Start isDeterministic. Operand 640 states and 920 transitions. [2025-01-10 07:51:17,540 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,540 INFO L218 hiAutomatonCegarLoop]: Abstraction has 640 states and 920 transitions. [2025-01-10 07:51:17,541 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states and 920 transitions. [2025-01-10 07:51:17,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 640. [2025-01-10 07:51:17,549 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 640 states, 640 states have (on average 1.4375) internal successors, (920), 639 states have internal predecessors, (920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 640 states to 640 states and 920 transitions. [2025-01-10 07:51:17,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 640 states and 920 transitions. [2025-01-10 07:51:17,552 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,553 INFO L432 stractBuchiCegarLoop]: Abstraction has 640 states and 920 transitions. [2025-01-10 07:51:17,553 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-01-10 07:51:17,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 640 states and 920 transitions. [2025-01-10 07:51:17,557 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 388 [2025-01-10 07:51:17,557 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,557 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,559 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~b0_ev~0);" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,559 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,560 INFO L85 PathProgramCache]: Analyzing trace with hash 379278680, now seen corresponding path program 1 times [2025-01-10 07:51:17,560 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,560 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267718364] [2025-01-10 07:51:17,560 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,560 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,568 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,568 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,587 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,587 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267718364] [2025-01-10 07:51:17,587 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267718364] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,587 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,587 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,587 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794993827] [2025-01-10 07:51:17,587 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,587 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,587 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,587 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 7 times [2025-01-10 07:51:17,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [631034459] [2025-01-10 07:51:17,588 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-01-10 07:51:17,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,589 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,591 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,591 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,591 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,591 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,592 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,593 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,593 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,593 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,594 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,616 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,616 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,616 INFO L87 Difference]: Start difference. First operand 640 states and 920 transitions. cyclomatic complexity: 283 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,639 INFO L93 Difference]: Finished difference Result 689 states and 983 transitions. [2025-01-10 07:51:17,639 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 689 states and 983 transitions. [2025-01-10 07:51:17,644 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2025-01-10 07:51:17,647 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 689 states to 689 states and 983 transitions. [2025-01-10 07:51:17,647 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 474 [2025-01-10 07:51:17,649 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 474 [2025-01-10 07:51:17,649 INFO L73 IsDeterministic]: Start isDeterministic. Operand 689 states and 983 transitions. [2025-01-10 07:51:17,649 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,649 INFO L218 hiAutomatonCegarLoop]: Abstraction has 689 states and 983 transitions. [2025-01-10 07:51:17,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 689 states and 983 transitions. [2025-01-10 07:51:17,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 689 to 689. [2025-01-10 07:51:17,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 689 states, 689 states have (on average 1.4267053701015966) internal successors, (983), 688 states have internal predecessors, (983), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,661 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 689 states to 689 states and 983 transitions. [2025-01-10 07:51:17,661 INFO L240 hiAutomatonCegarLoop]: Abstraction has 689 states and 983 transitions. [2025-01-10 07:51:17,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,662 INFO L432 stractBuchiCegarLoop]: Abstraction has 689 states and 983 transitions. [2025-01-10 07:51:17,662 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-01-10 07:51:17,662 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 689 states and 983 transitions. [2025-01-10 07:51:17,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 422 [2025-01-10 07:51:17,665 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,665 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,665 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,665 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,666 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume !(1 == ~b1_ev~0);" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,666 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,666 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,666 INFO L85 PathProgramCache]: Analyzing trace with hash -1395728682, now seen corresponding path program 1 times [2025-01-10 07:51:17,666 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,666 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [556472488] [2025-01-10 07:51:17,666 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,671 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,673 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,674 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,674 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,689 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [556472488] [2025-01-10 07:51:17,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [556472488] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,690 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,690 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,690 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2087497855] [2025-01-10 07:51:17,690 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,691 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,691 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,691 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 8 times [2025-01-10 07:51:17,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2071271795] [2025-01-10 07:51:17,691 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-01-10 07:51:17,691 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,696 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,697 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,697 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-01-10 07:51:17,697 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,697 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,698 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,698 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,700 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,700 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,703 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,727 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,727 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,728 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,728 INFO L87 Difference]: Start difference. First operand 689 states and 983 transitions. cyclomatic complexity: 297 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,752 INFO L93 Difference]: Finished difference Result 778 states and 1107 transitions. [2025-01-10 07:51:17,752 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 778 states and 1107 transitions. [2025-01-10 07:51:17,757 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 480 [2025-01-10 07:51:17,761 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 778 states to 778 states and 1107 transitions. [2025-01-10 07:51:17,761 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 532 [2025-01-10 07:51:17,761 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 532 [2025-01-10 07:51:17,761 INFO L73 IsDeterministic]: Start isDeterministic. Operand 778 states and 1107 transitions. [2025-01-10 07:51:17,762 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,762 INFO L218 hiAutomatonCegarLoop]: Abstraction has 778 states and 1107 transitions. [2025-01-10 07:51:17,763 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 778 states and 1107 transitions. [2025-01-10 07:51:17,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 778 to 778. [2025-01-10 07:51:17,802 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 778 states, 778 states have (on average 1.422879177377892) internal successors, (1107), 777 states have internal predecessors, (1107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 1107 transitions. [2025-01-10 07:51:17,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 778 states and 1107 transitions. [2025-01-10 07:51:17,805 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,806 INFO L432 stractBuchiCegarLoop]: Abstraction has 778 states and 1107 transitions. [2025-01-10 07:51:17,806 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-01-10 07:51:17,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 778 states and 1107 transitions. [2025-01-10 07:51:17,809 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 480 [2025-01-10 07:51:17,809 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,809 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,810 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,810 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume !(1 == ~d0_ev~0);" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,810 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,810 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,810 INFO L85 PathProgramCache]: Analyzing trace with hash -1452986984, now seen corresponding path program 1 times [2025-01-10 07:51:17,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1069024004] [2025-01-10 07:51:17,811 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,815 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,817 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,818 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,818 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-01-10 07:51:17,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-01-10 07:51:17,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-01-10 07:51:17,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1069024004] [2025-01-10 07:51:17,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1069024004] provided 1 perfect and 0 imperfect interpolant sequences [2025-01-10 07:51:17,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-01-10 07:51:17,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-01-10 07:51:17,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [435739540] [2025-01-10 07:51:17,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-01-10 07:51:17,837 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-01-10 07:51:17,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,837 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 9 times [2025-01-10 07:51:17,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1895156788] [2025-01-10 07:51:17,837 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-01-10 07:51:17,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,839 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,840 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,840 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-01-10 07:51:17,840 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,840 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,841 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,841 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,841 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,841 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,843 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-01-10 07:51:17,867 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-01-10 07:51:17,867 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-01-10 07:51:17,868 INFO L87 Difference]: Start difference. First operand 778 states and 1107 transitions. cyclomatic complexity: 332 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-01-10 07:51:17,895 INFO L93 Difference]: Finished difference Result 941 states and 1339 transitions. [2025-01-10 07:51:17,895 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 941 states and 1339 transitions. [2025-01-10 07:51:17,902 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 586 [2025-01-10 07:51:17,907 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 941 states to 941 states and 1339 transitions. [2025-01-10 07:51:17,907 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 638 [2025-01-10 07:51:17,907 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 638 [2025-01-10 07:51:17,908 INFO L73 IsDeterministic]: Start isDeterministic. Operand 941 states and 1339 transitions. [2025-01-10 07:51:17,908 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-01-10 07:51:17,908 INFO L218 hiAutomatonCegarLoop]: Abstraction has 941 states and 1339 transitions. [2025-01-10 07:51:17,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 941 states and 1339 transitions. [2025-01-10 07:51:17,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 941 to 941. [2025-01-10 07:51:17,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 941 states, 941 states have (on average 1.4229543039319872) internal successors, (1339), 940 states have internal predecessors, (1339), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-01-10 07:51:17,924 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 941 states to 941 states and 1339 transitions. [2025-01-10 07:51:17,924 INFO L240 hiAutomatonCegarLoop]: Abstraction has 941 states and 1339 transitions. [2025-01-10 07:51:17,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-01-10 07:51:17,925 INFO L432 stractBuchiCegarLoop]: Abstraction has 941 states and 1339 transitions. [2025-01-10 07:51:17,925 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-01-10 07:51:17,925 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 941 states and 1339 transitions. [2025-01-10 07:51:17,929 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 586 [2025-01-10 07:51:17,929 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-01-10 07:51:17,929 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-01-10 07:51:17,930 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,930 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-01-10 07:51:17,930 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(16, 2);call #Ultimate.allocInit(12, 3);~b0_val~0 := 0;~b0_val_t~0 := 0;~b0_ev~0 := 0;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_val_t~0 := 0;~b1_ev~0 := 0;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_val_t~0 := 0;~d0_ev~0 := 0;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_val_t~0 := 0;~d1_ev~0 := 0;~d1_req_up~0 := 0;~z_val~0 := 0;~z_val_t~0 := 0;~z_ev~0 := 0;~z_req_up~0 := 0;~comp_m1_st~0 := 0;~comp_m1_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~2#1;havoc main_~__retres1~2#1;assume { :begin_inline_init_model } true;~b0_val~0 := 0;~b0_ev~0 := 2;~b0_req_up~0 := 0;~b1_val~0 := 0;~b1_ev~0 := 2;~b1_req_up~0 := 0;~d0_val~0 := 0;~d0_ev~0 := 2;~d0_req_up~0 := 0;~d1_val~0 := 0;~d1_ev~0 := 2;~d1_req_up~0 := 0;~z_val~0 := 0;~z_ev~0 := 2;~z_req_up~0 := 0;~b0_val_t~0 := 1;~b0_req_up~0 := 1;~b1_val_t~0 := 1;~b1_req_up~0 := 1;~d0_val_t~0 := 1;~d0_req_up~0 := 1;~d1_val_t~0 := 1;~d1_req_up~0 := 1;~comp_m1_i~0 := 0;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret8#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume 1 == ~b0_req_up~0;assume { :begin_inline_update_b0 } true;" "assume ~b0_val~0 != ~b0_val_t~0;~b0_val~0 := ~b0_val_t~0;~b0_ev~0 := 0;" "~b0_req_up~0 := 0;" "assume { :end_inline_update_b0 } true;" "assume 1 == ~b1_req_up~0;assume { :begin_inline_update_b1 } true;" "assume ~b1_val~0 != ~b1_val_t~0;~b1_val~0 := ~b1_val_t~0;~b1_ev~0 := 0;" "~b1_req_up~0 := 0;" "assume { :end_inline_update_b1 } true;" "assume 1 == ~d0_req_up~0;assume { :begin_inline_update_d0 } true;" "assume ~d0_val~0 != ~d0_val_t~0;~d0_val~0 := ~d0_val_t~0;~d0_ev~0 := 0;" "~d0_req_up~0 := 0;" "assume { :end_inline_update_d0 } true;" "assume 1 == ~d1_req_up~0;assume { :begin_inline_update_d1 } true;" "assume ~d1_val~0 != ~d1_val_t~0;~d1_val~0 := ~d1_val_t~0;~d1_ev~0 := 0;" "~d1_req_up~0 := 0;" "assume { :end_inline_update_d1 } true;" "assume !(1 == ~z_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~comp_m1_i~0);~comp_m1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~b0_ev~0;~b0_ev~0 := 1;" "assume 0 == ~b1_ev~0;~b1_ev~0 := 1;" "assume 0 == ~d0_ev~0;~d0_ev~0 := 1;" "assume 0 == ~d1_ev~0;~d1_ev~0 := 1;" "assume !(0 == ~z_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;havoc activate_threads_~tmp~1#1;assume { :begin_inline_is_method1_triggered } true;havoc is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;havoc is_method1_triggered_~__retres1~0#1;" "assume 1 == ~b0_ev~0;is_method1_triggered_~__retres1~0#1 := 1;" "is_method1_triggered_#res#1 := is_method1_triggered_~__retres1~0#1;" "activate_threads_#t~ret6#1 := is_method1_triggered_#res#1;havoc is_method1_triggered_~__retres1~0#1;assume { :end_inline_is_method1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret6#1;havoc activate_threads_#t~ret6#1;" "assume 0 != activate_threads_~tmp~1#1;~comp_m1_st~0 := 0;" "havoc activate_threads_#t~ret6#1, activate_threads_~tmp~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~b0_ev~0;~b0_ev~0 := 2;" "assume 1 == ~b1_ev~0;~b1_ev~0 := 2;" "assume 1 == ~d0_ev~0;~d0_ev~0 := 2;" "assume 1 == ~d1_ev~0;~d1_ev~0 := 2;" "assume !(1 == ~z_ev~0);" "assume { :end_inline_reset_delta_events } true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp~0#1, eval_~tmp___0~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;" [2025-01-10 07:51:17,930 INFO L754 eck$LassoCheckResult]: Loop: "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;havoc exists_runnable_thread_~__retres1~1#1;" "assume 0 == ~comp_m1_st~0;exists_runnable_thread_~__retres1~1#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~1#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~1#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___0~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume 0 != eval_~tmp___0~0#1;" "assume 0 == ~comp_m1_st~0;havoc eval_#t~nondet5#1;eval_~tmp~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1;" "assume !(0 != eval_~tmp~0#1);" [2025-01-10 07:51:17,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,930 INFO L85 PathProgramCache]: Analyzing trace with hash -1454834026, now seen corresponding path program 1 times [2025-01-10 07:51:17,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1938137240] [2025-01-10 07:51:17,931 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,931 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,941 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,941 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,941 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,941 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,944 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:17,947 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:17,947 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,947 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,955 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,955 INFO L85 PathProgramCache]: Analyzing trace with hash 278808011, now seen corresponding path program 10 times [2025-01-10 07:51:17,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,956 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1916013760] [2025-01-10 07:51:17,956 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-01-10 07:51:17,956 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,960 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 7 statements into 2 equivalence classes. [2025-01-10 07:51:17,961 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,961 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-01-10 07:51:17,961 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,961 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,962 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-01-10 07:51:17,962 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-01-10 07:51:17,962 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,964 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:17,965 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-01-10 07:51:17,965 INFO L85 PathProgramCache]: Analyzing trace with hash -957700714, now seen corresponding path program 1 times [2025-01-10 07:51:17,965 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-01-10 07:51:17,965 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1220391305] [2025-01-10 07:51:17,965 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-01-10 07:51:17,965 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-01-10 07:51:17,971 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-01-10 07:51:17,973 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-01-10 07:51:17,973 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,973 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:17,975 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-01-10 07:51:17,979 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-01-10 07:51:17,979 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:17,979 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:17,990 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-01-10 07:51:18,956 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:18,961 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:18,962 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:18,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:18,962 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-01-10 07:51:18,971 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-01-10 07:51:18,976 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-01-10 07:51:18,977 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-01-10 07:51:18,977 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-01-10 07:51:19,079 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 10.01 07:51:19 BoogieIcfgContainer [2025-01-10 07:51:19,080 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-01-10 07:51:19,080 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-01-10 07:51:19,080 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-01-10 07:51:19,080 INFO L274 PluginConnector]: Witness Printer initialized [2025-01-10 07:51:19,081 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 10.01 07:51:13" (3/4) ... [2025-01-10 07:51:19,084 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-01-10 07:51:19,157 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-01-10 07:51:19,158 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-01-10 07:51:19,158 INFO L158 Benchmark]: Toolchain (without parser) took 6805.99ms. Allocated memory was 142.6MB in the beginning and 176.2MB in the end (delta: 33.6MB). Free memory was 113.4MB in the beginning and 116.6MB in the end (delta: -3.3MB). Peak memory consumption was 28.2MB. Max. memory is 16.1GB. [2025-01-10 07:51:19,158 INFO L158 Benchmark]: CDTParser took 0.29ms. Allocated memory is still 201.3MB. Free memory is still 124.0MB. There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:19,159 INFO L158 Benchmark]: CACSL2BoogieTranslator took 307.75ms. Allocated memory is still 142.6MB. Free memory was 112.9MB in the beginning and 100.1MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:19,159 INFO L158 Benchmark]: Boogie Procedure Inliner took 35.03ms. Allocated memory is still 142.6MB. Free memory was 100.1MB in the beginning and 97.8MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:19,159 INFO L158 Benchmark]: Boogie Preprocessor took 50.91ms. Allocated memory is still 142.6MB. Free memory was 97.8MB in the beginning and 95.8MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:19,159 INFO L158 Benchmark]: RCFGBuilder took 510.31ms. Allocated memory is still 142.6MB. Free memory was 95.8MB in the beginning and 72.6MB in the end (delta: 23.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-01-10 07:51:19,160 INFO L158 Benchmark]: BuchiAutomizer took 5819.44ms. Allocated memory was 142.6MB in the beginning and 176.2MB in the end (delta: 33.6MB). Free memory was 72.6MB in the beginning and 123.4MB in the end (delta: -50.8MB). There was no memory consumed. Max. memory is 16.1GB. [2025-01-10 07:51:19,160 INFO L158 Benchmark]: Witness Printer took 77.39ms. Allocated memory is still 176.2MB. Free memory was 123.4MB in the beginning and 116.6MB in the end (delta: 6.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-01-10 07:51:19,161 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.29ms. Allocated memory is still 201.3MB. Free memory is still 124.0MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 307.75ms. Allocated memory is still 142.6MB. Free memory was 112.9MB in the beginning and 100.1MB in the end (delta: 12.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 35.03ms. Allocated memory is still 142.6MB. Free memory was 100.1MB in the beginning and 97.8MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 50.91ms. Allocated memory is still 142.6MB. Free memory was 97.8MB in the beginning and 95.8MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. * RCFGBuilder took 510.31ms. Allocated memory is still 142.6MB. Free memory was 95.8MB in the beginning and 72.6MB in the end (delta: 23.2MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5819.44ms. Allocated memory was 142.6MB in the beginning and 176.2MB in the end (delta: 33.6MB). Free memory was 72.6MB in the beginning and 123.4MB in the end (delta: -50.8MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 77.39ms. Allocated memory is still 176.2MB. Free memory was 123.4MB in the beginning and 116.6MB in the end (delta: 6.8MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 18 terminating modules (17 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function (((long long) -1 * d1_ev) + 1) and consists of 3 locations. 17 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 941 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 5.6s and 18 iterations. TraceHistogramMax:1. Analysis of lassos took 4.2s. Construction of modules took 0.2s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 3. Minimization of det autom 6. Minimization of nondet autom 12. Automata minimization 0.2s AutomataMinimizationTime, 18 MinimizatonAttempts, 5 StatesRemovedByMinimization, 2 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 584 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 583 mSDsluCounter, 6756 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3607 mSDsCounter, 47 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 226 IncrementalHoareTripleChecker+Invalid, 273 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 47 mSolverCounterUnsat, 3149 mSDtfsCounter, 226 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN9 SILU0 SILI7 SILT1 lasso0 LassoPreprocessingBenchmarks: Lassos: inital59 mio100 ax100 hnf100 lsp15 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq188 hnf94 smp100 dnf137 smp100 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 30ms VariablesStem: 0 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 0 MotzkinApplications: 2 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 1 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 1]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 1]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int b0_val ; [L25] int b0_val_t ; [L26] int b0_ev ; [L27] int b0_req_up ; [L28] int b1_val ; [L29] int b1_val_t ; [L30] int b1_ev ; [L31] int b1_req_up ; [L32] int d0_val ; [L33] int d0_val_t ; [L34] int d0_ev ; [L35] int d0_req_up ; [L36] int d1_val ; [L37] int d1_val_t ; [L38] int d1_ev ; [L39] int d1_req_up ; [L40] int z_val ; [L41] int z_val_t ; [L42] int z_ev ; [L43] int z_req_up ; [L44] int comp_m1_st ; [L45] int comp_m1_i ; VAL [b0_ev=0, b0_req_up=0, b0_val=0, b0_val_t=0, b1_ev=0, b1_req_up=0, b1_val=0, b1_val_t=0, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=0, d0_val_t=0, d1_ev=0, d1_req_up=0, d1_val=0, d1_val_t=0, z_ev=0, z_req_up=0, z_val=0, z_val_t=0] [L494] int __retres1 ; [L498] CALL init_model() [L465] b0_val = 0 [L466] b0_ev = 2 [L467] b0_req_up = 0 [L468] b1_val = 0 [L469] b1_ev = 2 [L470] b1_req_up = 0 [L471] d0_val = 0 [L472] d0_ev = 2 [L473] d0_req_up = 0 [L474] d1_val = 0 [L475] d1_ev = 2 [L476] d1_req_up = 0 [L477] z_val = 0 [L478] z_ev = 2 [L479] z_req_up = 0 [L480] b0_val_t = 1 [L481] b0_req_up = 1 [L482] b1_val_t = 1 [L483] b1_req_up = 1 [L484] d0_val_t = 1 [L485] d0_req_up = 1 [L486] d1_val_t = 1 [L487] d1_req_up = 1 [L488] comp_m1_i = 0 VAL [b0_ev=2, b0_req_up=1, b0_val=0, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L498] RET init_model() [L499] CALL start_simulation() [L419] int kernel_st ; [L420] int tmp ; [L424] kernel_st = 0 [L425] CALL update_channels() [L212] COND TRUE (int )b0_req_up == 1 [L214] CALL update_b0() [L137] COND TRUE (int )b0_val != (int )b0_val_t [L138] b0_val = b0_val_t [L139] b0_ev = 0 VAL [b0_ev=0, b0_req_up=1, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L143] b0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=1, b1_val=0, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L214] RET update_b0() [L219] COND TRUE (int )b1_req_up == 1 [L221] CALL update_b1() [L152] COND TRUE (int )b1_val != (int )b1_val_t [L153] b1_val = b1_val_t [L154] b1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=1, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L158] b1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=1, d0_val=0, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L221] RET update_b1() [L226] COND TRUE (int )d0_req_up == 1 [L228] CALL update_d0() [L167] COND TRUE (int )d0_val != (int )d0_val_t [L168] d0_val = d0_val_t [L169] d0_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=1, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L173] d0_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=1, d1_val=0, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L228] RET update_d0() [L233] COND TRUE (int )d1_req_up == 1 [L235] CALL update_d1() [L182] COND TRUE (int )d1_val != (int )d1_val_t [L183] d1_val = d1_val_t [L184] d1_ev = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=1, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L188] d1_req_up = 0 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L235] RET update_d1() [L240] COND FALSE !((int )z_req_up == 1) VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L425] RET update_channels() [L426] CALL init_threads() [L255] COND FALSE !((int )comp_m1_i == 1) [L258] comp_m1_st = 2 VAL [b0_ev=0, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L426] RET init_threads() [L427] CALL fire_delta_events() [L321] COND TRUE (int )b0_ev == 0 [L322] b0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=0, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L326] COND TRUE (int )b1_ev == 0 [L327] b1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=0, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L331] COND TRUE (int )d0_ev == 0 [L332] d0_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=0, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L336] COND TRUE (int )d1_ev == 0 [L337] d1_ev = 1 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L341] COND FALSE !((int )z_ev == 0) VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L427] RET fire_delta_events() [L428] CALL activate_threads() [L384] int tmp ; [L388] CALL, EXPR is_method1_triggered() [L104] int __retres1 ; VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L107] COND TRUE (int )b0_ev == 1 [L108] __retres1 = 1 VAL [__retres1=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L130] return (__retres1); VAL [\result=1, b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=2, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L388] RET, EXPR is_method1_triggered() [L388] tmp = is_method1_triggered() [L390] COND TRUE \read(tmp) [L391] comp_m1_st = 0 VAL [b0_ev=1, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L428] RET activate_threads() [L429] CALL reset_delta_events() [L354] COND TRUE (int )b0_ev == 1 [L355] b0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=1, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L359] COND TRUE (int )b1_ev == 1 [L360] b1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=1, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L364] COND TRUE (int )d0_ev == 1 [L365] d0_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=1, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L369] COND TRUE (int )d1_ev == 1 [L370] d1_ev = 2 VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L374] COND FALSE !((int )z_ev == 1) VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] [L429] RET reset_delta_events() [L435] kernel_st = 1 [L436] CALL eval() [L280] int tmp ; [L281] int tmp___0 ; VAL [b0_ev=2, b0_req_up=0, b0_val=1, b0_val_t=1, b1_ev=2, b1_req_up=0, b1_val=1, b1_val_t=1, comp_m1_i=0, comp_m1_st=0, d0_ev=2, d0_req_up=0, d0_val=1, d0_val_t=1, d1_ev=2, d1_req_up=0, d1_val=1, d1_val_t=1, z_ev=2, z_req_up=0, z_val=0, z_val_t=0] Loop: [L288] CALL, EXPR exists_runnable_thread() [L265] int __retres1 ; [L268] COND TRUE (int )comp_m1_st == 0 [L269] __retres1 = 1 [L276] return (__retres1); [L288] RET, EXPR exists_runnable_thread() [L288] tmp___0 = exists_runnable_thread() [L290] COND TRUE \read(tmp___0) [L295] COND TRUE (int )comp_m1_st == 0 [L297] tmp = __VERIFIER_nondet_int() [L299] COND FALSE !(\read(tmp)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-01-10 07:51:19,186 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)