./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 48c9605d Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/array-examples/sanfoundry_24-1.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b --- Real Ultimate output --- This is Ultimate 0.3.0-?-48c9605-m [2025-02-08 14:28:01,474 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-08 14:28:01,538 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-08 14:28:01,542 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-08 14:28:01,542 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-08 14:28:01,542 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-08 14:28:01,555 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-08 14:28:01,556 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-08 14:28:01,556 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-08 14:28:01,556 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * Use SBE=true [2025-02-08 14:28:01,556 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-08 14:28:01,556 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-08 14:28:01,557 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-08 14:28:01,557 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-08 14:28:01,557 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-08 14:28:01,558 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-08 14:28:01,558 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-08 14:28:01,558 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-08 14:28:01,558 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-08 14:28:01,558 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e0a16588b251f5de7b3febde43795c7086835cc989637b8bd82aa8d6af355c6b [2025-02-08 14:28:01,754 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-08 14:28:01,762 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-08 14:28:01,763 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-08 14:28:01,764 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-08 14:28:01,765 INFO L274 PluginConnector]: CDTParser initialized [2025-02-08 14:28:01,765 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-02-08 14:28:03,045 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2866d55c6/da67c0f253554e4eafbc10c90909d8be/FLAG9a2d2606e [2025-02-08 14:28:03,306 INFO L384 CDTParser]: Found 1 translation units. [2025-02-08 14:28:03,307 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/array-examples/sanfoundry_24-1.i [2025-02-08 14:28:03,317 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2866d55c6/da67c0f253554e4eafbc10c90909d8be/FLAG9a2d2606e [2025-02-08 14:28:03,361 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/2866d55c6/da67c0f253554e4eafbc10c90909d8be [2025-02-08 14:28:03,364 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-08 14:28:03,366 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-08 14:28:03,367 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-08 14:28:03,367 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-08 14:28:03,370 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-08 14:28:03,370 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,371 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6dd3c4b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03, skipping insertion in model container [2025-02-08 14:28:03,371 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,380 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-08 14:28:03,499 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-08 14:28:03,508 INFO L200 MainTranslator]: Completed pre-run [2025-02-08 14:28:03,523 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-08 14:28:03,540 INFO L204 MainTranslator]: Completed translation [2025-02-08 14:28:03,540 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03 WrapperNode [2025-02-08 14:28:03,540 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-08 14:28:03,541 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-08 14:28:03,541 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-08 14:28:03,541 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-08 14:28:03,546 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,551 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,562 INFO L138 Inliner]: procedures = 18, calls = 19, calls flagged for inlining = 7, calls inlined = 8, statements flattened = 69 [2025-02-08 14:28:03,562 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-08 14:28:03,562 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-08 14:28:03,563 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-08 14:28:03,563 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-08 14:28:03,568 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,568 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,569 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,577 INFO L175 MemorySlicer]: Split 7 memory accesses to 2 slices as follows [2, 5]. 71 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2, 0]. The 1 writes are split as follows [0, 1]. [2025-02-08 14:28:03,578 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,578 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,581 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,582 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,582 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,583 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,584 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-08 14:28:03,585 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-08 14:28:03,585 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-08 14:28:03,585 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-08 14:28:03,585 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (1/1) ... [2025-02-08 14:28:03,590 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:03,600 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:03,611 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:03,615 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-08 14:28:03,632 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-02-08 14:28:03,632 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-02-08 14:28:03,677 INFO L257 CfgBuilder]: Building ICFG [2025-02-08 14:28:03,679 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-08 14:28:03,804 INFO L1324 $ProcedureCfgBuilder]: dead code at ProgramPoint L23: call ULTIMATE.dealloc(main_~#array~0#1.base, main_~#array~0#1.offset);havoc main_~#array~0#1.base, main_~#array~0#1.offset; [2025-02-08 14:28:03,814 INFO L? ?]: Removed 16 outVars from TransFormulas that were not future-live. [2025-02-08 14:28:03,815 INFO L308 CfgBuilder]: Performing block encoding [2025-02-08 14:28:03,820 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-08 14:28:03,821 INFO L337 CfgBuilder]: Removed 0 assume(true) statements. [2025-02-08 14:28:03,821 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 08.02 02:28:03 BoogieIcfgContainer [2025-02-08 14:28:03,821 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-08 14:28:03,822 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-08 14:28:03,822 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-08 14:28:03,826 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-08 14:28:03,826 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:28:03,826 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.02 02:28:03" (1/3) ... [2025-02-08 14:28:03,827 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf25d0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.02 02:28:03, skipping insertion in model container [2025-02-08 14:28:03,827 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:28:03,827 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:28:03" (2/3) ... [2025-02-08 14:28:03,827 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6bf25d0e and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.02 02:28:03, skipping insertion in model container [2025-02-08 14:28:03,828 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:28:03,828 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 08.02 02:28:03" (3/3) ... [2025-02-08 14:28:03,829 INFO L363 chiAutomizerObserver]: Analyzing ICFG sanfoundry_24-1.i [2025-02-08 14:28:03,860 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-08 14:28:03,860 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-08 14:28:03,860 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-08 14:28:03,860 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-08 14:28:03,860 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-08 14:28:03,861 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-08 14:28:03,861 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-08 14:28:03,861 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-08 14:28:03,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 19 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:03,875 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2025-02-08 14:28:03,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:03,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:03,878 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:28:03,878 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-02-08 14:28:03,878 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-08 14:28:03,878 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 19 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:03,879 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 15 [2025-02-08 14:28:03,879 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:03,879 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:03,879 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:28:03,879 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1] [2025-02-08 14:28:03,882 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" [2025-02-08 14:28:03,883 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" [2025-02-08 14:28:03,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:03,886 INFO L85 PathProgramCache]: Analyzing trace with hash 58, now seen corresponding path program 1 times [2025-02-08 14:28:03,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:03,892 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1359212687] [2025-02-08 14:28:03,892 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:03,892 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:03,936 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:03,946 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:03,947 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:03,947 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:03,947 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:03,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:03,952 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:03,952 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:03,952 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:03,962 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:03,964 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:03,964 INFO L85 PathProgramCache]: Analyzing trace with hash 57, now seen corresponding path program 1 times [2025-02-08 14:28:03,964 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:03,964 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075474732] [2025-02-08 14:28:03,964 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:03,964 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:03,968 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:03,971 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:03,971 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:03,971 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:03,971 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:03,972 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:03,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:03,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:03,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:03,976 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:03,977 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:03,977 INFO L85 PathProgramCache]: Analyzing trace with hash 1824, now seen corresponding path program 1 times [2025-02-08 14:28:03,977 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:03,977 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1397630249] [2025-02-08 14:28:03,977 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:03,977 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:03,984 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-08 14:28:03,996 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-08 14:28:03,996 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:03,996 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:03,996 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:03,998 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-08 14:28:04,006 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-08 14:28:04,006 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:04,006 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:04,008 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:04,281 INFO L204 LassoAnalysis]: Preferences: [2025-02-08 14:28:04,282 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-02-08 14:28:04,282 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-02-08 14:28:04,282 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-02-08 14:28:04,282 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-02-08 14:28:04,282 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,282 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-02-08 14:28:04,282 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-02-08 14:28:04,283 INFO L132 ssoRankerPreferences]: Filename of dumped script: sanfoundry_24-1.i_Iteration1_Lasso [2025-02-08 14:28:04,283 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-02-08 14:28:04,283 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-02-08 14:28:04,292 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,424 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,426 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,439 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,447 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-02-08 14:28:04,606 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-02-08 14:28:04,608 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-02-08 14:28:04,609 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,610 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,612 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,613 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-02-08 14:28:04,618 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,630 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,630 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,630 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,630 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,636 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,636 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,655 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,663 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-02-08 14:28:04,665 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,666 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,667 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,670 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-02-08 14:28:04,670 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,681 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,681 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-02-08 14:28:04,682 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,682 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,682 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,682 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-02-08 14:28:04,683 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-02-08 14:28:04,685 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,690 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-02-08 14:28:04,691 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,691 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,693 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,694 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-02-08 14:28:04,696 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,707 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,707 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,707 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,707 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,711 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,711 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,716 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,722 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-02-08 14:28:04,722 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,722 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,725 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,725 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-02-08 14:28:04,727 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,737 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,737 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,737 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,737 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,739 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,739 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,742 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,748 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-02-08 14:28:04,748 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,749 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,750 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,752 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-02-08 14:28:04,753 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,763 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,763 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,763 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,763 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,765 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,765 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,768 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,774 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2025-02-08 14:28:04,775 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,775 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,777 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,777 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-02-08 14:28:04,779 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,790 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,790 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,790 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,790 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,792 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,792 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,795 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,801 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2025-02-08 14:28:04,802 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,802 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,809 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,810 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-02-08 14:28:04,811 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,822 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,822 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,822 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,822 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,824 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,824 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,829 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-02-08 14:28:04,836 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-02-08 14:28:04,836 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,836 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,838 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,839 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-02-08 14:28:04,840 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-02-08 14:28:04,850 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-02-08 14:28:04,850 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-02-08 14:28:04,851 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-02-08 14:28:04,851 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-02-08 14:28:04,854 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-02-08 14:28:04,854 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-02-08 14:28:04,861 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-02-08 14:28:04,875 INFO L443 ModelExtractionUtils]: Simplification made 9 calls to the SMT solver. [2025-02-08 14:28:04,877 INFO L444 ModelExtractionUtils]: 3 out of 16 variables were initially zero. Simplification set additionally 9 variables to zero. [2025-02-08 14:28:04,879 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:28:04,879 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:04,899 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:28:04,900 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-02-08 14:28:04,904 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-02-08 14:28:04,922 INFO L438 nArgumentSynthesizer]: Removed 1 redundant supporting invariants from a total of 2. [2025-02-08 14:28:04,923 INFO L474 LassoAnalysis]: Proved termination. [2025-02-08 14:28:04,923 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = 1*v_rep(select #length ULTIMATE.start_main_~#array~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [1*ULTIMATE.start_main_~#array~0#1.offset >= 0] [2025-02-08 14:28:04,931 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2025-02-08 14:28:04,944 INFO L156 tatePredicateManager]: 4 out of 5 supporting invariants were superfluous and have been removed [2025-02-08 14:28:04,949 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-02-08 14:28:04,950 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-02-08 14:28:04,972 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:04,979 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:04,982 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:04,982 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:04,982 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:04,983 INFO L256 TraceCheckSpWp]: Trace formula consists of 31 conjuncts, 3 conjuncts are in the unsatisfiable core [2025-02-08 14:28:04,984 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:04,990 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:28:04,991 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:28:04,991 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:04,991 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:04,992 INFO L256 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 5 conjuncts are in the unsatisfiable core [2025-02-08 14:28:04,992 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:04,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:05,013 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 1 loop predicates [2025-02-08 14:28:05,015 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 19 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 1.0) internal successors, (2), 1 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,046 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 19 states, 18 states have (on average 1.5) internal successors, (27), 18 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 2 states, 2 states have (on average 1.0) internal successors, (2), 1 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 21 states and 31 transitions. Complement of second has 3 states. [2025-02-08 14:28:05,047 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 2 states 1 stem states 0 non-accepting loop states 1 accepting loop states [2025-02-08 14:28:05,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2 states, 2 states have (on average 1.0) internal successors, (2), 1 states have internal predecessors, (2), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2 states to 2 states and 2 transitions. [2025-02-08 14:28:05,054 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 1 letters. Loop has 1 letters. [2025-02-08 14:28:05,054 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-08 14:28:05,054 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 2 letters. Loop has 1 letters. [2025-02-08 14:28:05,054 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-08 14:28:05,054 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 2 states and 2 transitions. Stem has 1 letters. Loop has 2 letters. [2025-02-08 14:28:05,054 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-02-08 14:28:05,054 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21 states and 31 transitions. [2025-02-08 14:28:05,055 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2025-02-08 14:28:05,056 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21 states to 18 states and 28 transitions. [2025-02-08 14:28:05,057 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16 [2025-02-08 14:28:05,057 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17 [2025-02-08 14:28:05,057 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18 states and 28 transitions. [2025-02-08 14:28:05,058 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:05,058 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18 states and 28 transitions. [2025-02-08 14:28:05,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states and 28 transitions. [2025-02-08 14:28:05,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 17. [2025-02-08 14:28:05,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17 states, 17 states have (on average 1.5294117647058822) internal successors, (26), 16 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17 states to 17 states and 26 transitions. [2025-02-08 14:28:05,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17 states and 26 transitions. [2025-02-08 14:28:05,077 INFO L432 stractBuchiCegarLoop]: Abstraction has 17 states and 26 transitions. [2025-02-08 14:28:05,077 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-08 14:28:05,077 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17 states and 26 transitions. [2025-02-08 14:28:05,078 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14 [2025-02-08 14:28:05,078 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:05,078 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:05,078 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-02-08 14:28:05,078 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:05,078 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" [2025-02-08 14:28:05,078 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" [2025-02-08 14:28:05,079 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1823, now seen corresponding path program 1 times [2025-02-08 14:28:05,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911061073] [2025-02-08 14:28:05,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,091 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-08 14:28:05,098 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-08 14:28:05,099 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,099 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,099 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,100 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-02-08 14:28:05,104 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-02-08 14:28:05,104 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,106 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,106 INFO L85 PathProgramCache]: Analyzing trace with hash 53583, now seen corresponding path program 1 times [2025-02-08 14:28:05,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1142490305] [2025-02-08 14:28:05,106 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,108 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,115 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,115 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,115 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,115 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,117 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,119 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,122 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,122 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,124 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,124 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,125 INFO L85 PathProgramCache]: Analyzing trace with hash 54332785, now seen corresponding path program 1 times [2025-02-08 14:28:05,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856028495] [2025-02-08 14:28:05,126 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,126 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-02-08 14:28:05,141 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-02-08 14:28:05,141 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,141 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:05,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:05,242 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:05,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856028495] [2025-02-08 14:28:05,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856028495] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:28:05,243 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:28:05,243 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-02-08 14:28:05,244 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2126916318] [2025-02-08 14:28:05,244 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:28:05,284 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:05,285 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-08 14:28:05,285 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-02-08 14:28:05,286 INFO L87 Difference]: Start difference. First operand 17 states and 26 transitions. cyclomatic complexity: 12 Second operand has 4 states, 4 states have (on average 1.25) internal successors, (5), 3 states have internal predecessors, (5), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:05,323 INFO L93 Difference]: Finished difference Result 29 states and 36 transitions. [2025-02-08 14:28:05,323 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29 states and 36 transitions. [2025-02-08 14:28:05,324 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:05,325 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29 states to 23 states and 29 transitions. [2025-02-08 14:28:05,326 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22 [2025-02-08 14:28:05,326 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22 [2025-02-08 14:28:05,326 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 29 transitions. [2025-02-08 14:28:05,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:05,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 29 transitions. [2025-02-08 14:28:05,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 29 transitions. [2025-02-08 14:28:05,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 14. [2025-02-08 14:28:05,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14 states, 14 states have (on average 1.2857142857142858) internal successors, (18), 13 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 18 transitions. [2025-02-08 14:28:05,328 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14 states and 18 transitions. [2025-02-08 14:28:05,329 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-08 14:28:05,329 INFO L432 stractBuchiCegarLoop]: Abstraction has 14 states and 18 transitions. [2025-02-08 14:28:05,330 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-08 14:28:05,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14 states and 18 transitions. [2025-02-08 14:28:05,331 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:05,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:05,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:05,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1] [2025-02-08 14:28:05,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:05,331 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:05,331 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:05,331 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,331 INFO L85 PathProgramCache]: Analyzing trace with hash 1753663, now seen corresponding path program 1 times [2025-02-08 14:28:05,331 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,331 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [256180144] [2025-02-08 14:28:05,332 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-02-08 14:28:05,343 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-02-08 14:28:05,346 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,346 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,346 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,347 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-02-08 14:28:05,354 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-02-08 14:28:05,357 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,357 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,359 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,359 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,359 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 2 times [2025-02-08 14:28:05,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167160648] [2025-02-08 14:28:05,359 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:05,360 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,364 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,371 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,371 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:05,371 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,371 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,372 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,374 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,374 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,377 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,378 INFO L85 PathProgramCache]: Analyzing trace with hash 703789473, now seen corresponding path program 1 times [2025-02-08 14:28:05,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029142809] [2025-02-08 14:28:05,380 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,383 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-08 14:28:05,391 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-08 14:28:05,391 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,391 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:05,479 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:05,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:05,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029142809] [2025-02-08 14:28:05,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029142809] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:05,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1173548762] [2025-02-08 14:28:05,481 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:28:05,481 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:05,481 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:05,488 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:05,490 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2025-02-08 14:28:05,538 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-02-08 14:28:05,546 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-02-08 14:28:05,546 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,546 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:05,547 INFO L256 TraceCheckSpWp]: Trace formula consists of 62 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-02-08 14:28:05,548 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:05,588 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:05,588 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:05,623 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:05,623 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1173548762] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:05,623 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:05,623 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4] total 8 [2025-02-08 14:28:05,623 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028919233] [2025-02-08 14:28:05,623 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:05,668 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:05,669 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-08 14:28:05,669 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2025-02-08 14:28:05,669 INFO L87 Difference]: Start difference. First operand 14 states and 18 transitions. cyclomatic complexity: 7 Second operand has 10 states, 9 states have (on average 2.0) internal successors, (18), 9 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:05,750 INFO L93 Difference]: Finished difference Result 46 states and 57 transitions. [2025-02-08 14:28:05,750 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 46 states and 57 transitions. [2025-02-08 14:28:05,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:05,753 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 46 states to 34 states and 42 transitions. [2025-02-08 14:28:05,753 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32 [2025-02-08 14:28:05,753 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32 [2025-02-08 14:28:05,754 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34 states and 42 transitions. [2025-02-08 14:28:05,754 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:05,754 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34 states and 42 transitions. [2025-02-08 14:28:05,754 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states and 42 transitions. [2025-02-08 14:28:05,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 20. [2025-02-08 14:28:05,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.25) internal successors, (25), 19 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:05,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 25 transitions. [2025-02-08 14:28:05,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 25 transitions. [2025-02-08 14:28:05,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-08 14:28:05,758 INFO L432 stractBuchiCegarLoop]: Abstraction has 20 states and 25 transitions. [2025-02-08 14:28:05,758 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-08 14:28:05,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 25 transitions. [2025-02-08 14:28:05,759 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:05,760 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:05,760 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:05,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1] [2025-02-08 14:28:05,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:05,760 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:05,760 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:05,760 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,760 INFO L85 PathProgramCache]: Analyzing trace with hash 372227079, now seen corresponding path program 2 times [2025-02-08 14:28:05,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815316115] [2025-02-08 14:28:05,761 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:05,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,766 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 8 statements into 2 equivalence classes. [2025-02-08 14:28:05,780 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 8 of 8 statements. [2025-02-08 14:28:05,781 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:05,781 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,781 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,783 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-02-08 14:28:05,825 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-02-08 14:28:05,828 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,831 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,836 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,839 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 3 times [2025-02-08 14:28:05,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861482755] [2025-02-08 14:28:05,839 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:05,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,846 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,849 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,852 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:28:05,852 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,853 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:05,853 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2025-02-08 14:28:05,854 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:05,857 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:05,859 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:05,862 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:05,864 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:05,865 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:05,865 INFO L85 PathProgramCache]: Analyzing trace with hash -588625191, now seen corresponding path program 3 times [2025-02-08 14:28:05,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:05,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1030904397] [2025-02-08 14:28:05,865 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:05,865 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:05,870 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 11 statements into 3 equivalence classes. [2025-02-08 14:28:05,880 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 11 of 11 statements. [2025-02-08 14:28:05,880 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-02-08 14:28:05,880 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:06,033 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 1 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:06,033 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:06,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1030904397] [2025-02-08 14:28:06,033 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1030904397] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:06,033 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1803456450] [2025-02-08 14:28:06,033 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:06,033 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:06,033 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:06,036 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:06,038 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2025-02-08 14:28:06,062 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 11 statements into 3 equivalence classes. [2025-02-08 14:28:06,072 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 11 of 11 statements. [2025-02-08 14:28:06,072 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-02-08 14:28:06,072 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:06,073 INFO L256 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-02-08 14:28:06,074 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:06,242 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:06,242 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:06,364 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:06,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1803456450] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:06,364 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:06,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 11 [2025-02-08 14:28:06,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2141241144] [2025-02-08 14:28:06,364 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:06,480 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:06,481 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-08 14:28:06,481 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=109, Unknown=0, NotChecked=0, Total=156 [2025-02-08 14:28:06,481 INFO L87 Difference]: Start difference. First operand 20 states and 25 transitions. cyclomatic complexity: 8 Second operand has 13 states, 12 states have (on average 2.0833333333333335) internal successors, (25), 12 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:06,654 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:06,655 INFO L93 Difference]: Finished difference Result 67 states and 82 transitions. [2025-02-08 14:28:06,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67 states and 82 transitions. [2025-02-08 14:28:06,656 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:06,656 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67 states to 45 states and 55 transitions. [2025-02-08 14:28:06,656 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42 [2025-02-08 14:28:06,657 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42 [2025-02-08 14:28:06,657 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 55 transitions. [2025-02-08 14:28:06,657 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:06,657 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45 states and 55 transitions. [2025-02-08 14:28:06,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 55 transitions. [2025-02-08 14:28:06,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 26. [2025-02-08 14:28:06,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26 states, 26 states have (on average 1.2307692307692308) internal successors, (32), 25 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:06,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 32 transitions. [2025-02-08 14:28:06,659 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26 states and 32 transitions. [2025-02-08 14:28:06,659 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-02-08 14:28:06,659 INFO L432 stractBuchiCegarLoop]: Abstraction has 26 states and 32 transitions. [2025-02-08 14:28:06,659 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-08 14:28:06,659 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26 states and 32 transitions. [2025-02-08 14:28:06,660 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:06,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:06,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:06,660 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1] [2025-02-08 14:28:06,660 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:06,660 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:06,661 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:06,661 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:06,661 INFO L85 PathProgramCache]: Analyzing trace with hash -23893441, now seen corresponding path program 4 times [2025-02-08 14:28:06,661 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:06,661 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678355069] [2025-02-08 14:28:06,661 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:06,661 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:06,665 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 12 statements into 2 equivalence classes. [2025-02-08 14:28:06,674 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 12 of 12 statements. [2025-02-08 14:28:06,674 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:06,674 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:06,674 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:06,675 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-02-08 14:28:06,684 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-02-08 14:28:06,684 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:06,684 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:06,686 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:06,686 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:06,686 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 4 times [2025-02-08 14:28:06,686 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:06,686 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1111539993] [2025-02-08 14:28:06,687 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:06,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:06,688 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-08 14:28:06,690 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:06,690 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:06,690 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:06,690 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:06,690 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:06,691 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:06,691 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:06,691 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:06,692 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:06,692 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:06,693 INFO L85 PathProgramCache]: Analyzing trace with hash 1155092897, now seen corresponding path program 5 times [2025-02-08 14:28:06,693 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:06,693 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [560582709] [2025-02-08 14:28:06,693 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:06,693 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:06,698 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 15 statements into 4 equivalence classes. [2025-02-08 14:28:06,708 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 15 of 15 statements. [2025-02-08 14:28:06,708 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-02-08 14:28:06,708 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:06,806 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:06,806 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:06,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [560582709] [2025-02-08 14:28:06,807 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [560582709] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:06,807 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [45425402] [2025-02-08 14:28:06,807 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:06,807 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:06,807 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:06,809 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:06,815 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2025-02-08 14:28:06,845 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 15 statements into 4 equivalence classes. [2025-02-08 14:28:06,858 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 15 of 15 statements. [2025-02-08 14:28:06,858 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-02-08 14:28:06,858 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:06,859 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-02-08 14:28:06,860 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:06,956 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:06,956 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:07,004 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:07,005 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [45425402] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:07,005 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:07,005 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 12 [2025-02-08 14:28:07,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [697179813] [2025-02-08 14:28:07,005 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:07,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:07,061 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2025-02-08 14:28:07,061 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2025-02-08 14:28:07,061 INFO L87 Difference]: Start difference. First operand 26 states and 32 transitions. cyclomatic complexity: 9 Second operand has 14 states, 13 states have (on average 2.0) internal successors, (26), 13 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:07,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:07,210 INFO L93 Difference]: Finished difference Result 88 states and 107 transitions. [2025-02-08 14:28:07,210 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 88 states and 107 transitions. [2025-02-08 14:28:07,211 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:07,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 88 states to 56 states and 68 transitions. [2025-02-08 14:28:07,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52 [2025-02-08 14:28:07,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52 [2025-02-08 14:28:07,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 56 states and 68 transitions. [2025-02-08 14:28:07,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:07,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 56 states and 68 transitions. [2025-02-08 14:28:07,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 56 states and 68 transitions. [2025-02-08 14:28:07,214 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 56 to 32. [2025-02-08 14:28:07,214 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.21875) internal successors, (39), 31 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:07,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 39 transitions. [2025-02-08 14:28:07,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 39 transitions. [2025-02-08 14:28:07,215 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:28:07,216 INFO L432 stractBuchiCegarLoop]: Abstraction has 32 states and 39 transitions. [2025-02-08 14:28:07,216 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-08 14:28:07,216 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 39 transitions. [2025-02-08 14:28:07,216 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:07,216 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:07,216 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:07,217 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 1, 1] [2025-02-08 14:28:07,217 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:07,217 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:07,217 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:07,217 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,218 INFO L85 PathProgramCache]: Analyzing trace with hash 611864071, now seen corresponding path program 6 times [2025-02-08 14:28:07,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780734381] [2025-02-08 14:28:07,218 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:07,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,224 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 16 statements into 4 equivalence classes. [2025-02-08 14:28:07,245 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) and asserted 16 of 16 statements. [2025-02-08 14:28:07,245 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 4 check-sat command(s) [2025-02-08 14:28:07,245 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,245 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:07,248 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 16 statements into 1 equivalence classes. [2025-02-08 14:28:07,255 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 16 of 16 statements. [2025-02-08 14:28:07,255 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,256 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:07,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,259 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 5 times [2025-02-08 14:28:07,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515308] [2025-02-08 14:28:07,259 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:07,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,261 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:07,263 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:07,263 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:07,263 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,263 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:07,264 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:07,265 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:07,265 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,265 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,266 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:07,266 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,266 INFO L85 PathProgramCache]: Analyzing trace with hash 201357529, now seen corresponding path program 7 times [2025-02-08 14:28:07,266 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,266 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915500156] [2025-02-08 14:28:07,266 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:07,267 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,272 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-02-08 14:28:07,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-02-08 14:28:07,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,279 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:07,441 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 12 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:07,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:07,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915500156] [2025-02-08 14:28:07,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915500156] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:07,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [104332397] [2025-02-08 14:28:07,442 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:07,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:07,442 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:07,446 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:07,449 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2025-02-08 14:28:07,483 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-02-08 14:28:07,497 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-02-08 14:28:07,498 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,498 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:07,498 INFO L256 TraceCheckSpWp]: Trace formula consists of 125 conjuncts, 12 conjuncts are in the unsatisfiable core [2025-02-08 14:28:07,499 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:07,603 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:07,603 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:07,674 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 22 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:07,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [104332397] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:07,674 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:07,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 17 [2025-02-08 14:28:07,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [597280907] [2025-02-08 14:28:07,674 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:07,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:07,710 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2025-02-08 14:28:07,710 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=249, Unknown=0, NotChecked=0, Total=342 [2025-02-08 14:28:07,710 INFO L87 Difference]: Start difference. First operand 32 states and 39 transitions. cyclomatic complexity: 10 Second operand has 19 states, 18 states have (on average 2.1666666666666665) internal successors, (39), 18 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:07,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:07,870 INFO L93 Difference]: Finished difference Result 109 states and 132 transitions. [2025-02-08 14:28:07,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 109 states and 132 transitions. [2025-02-08 14:28:07,874 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:07,874 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 109 states to 67 states and 81 transitions. [2025-02-08 14:28:07,874 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 62 [2025-02-08 14:28:07,874 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 62 [2025-02-08 14:28:07,874 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67 states and 81 transitions. [2025-02-08 14:28:07,874 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:07,874 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67 states and 81 transitions. [2025-02-08 14:28:07,875 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states and 81 transitions. [2025-02-08 14:28:07,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 38. [2025-02-08 14:28:07,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.2105263157894737) internal successors, (46), 37 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:07,880 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 46 transitions. [2025-02-08 14:28:07,880 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 46 transitions. [2025-02-08 14:28:07,881 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2025-02-08 14:28:07,882 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 46 transitions. [2025-02-08 14:28:07,882 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-08 14:28:07,882 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 46 transitions. [2025-02-08 14:28:07,882 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:07,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:07,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:07,882 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 1, 1] [2025-02-08 14:28:07,882 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:07,882 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:07,883 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:07,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,884 INFO L85 PathProgramCache]: Analyzing trace with hash -782314945, now seen corresponding path program 8 times [2025-02-08 14:28:07,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443845633] [2025-02-08 14:28:07,884 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:07,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,908 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 20 statements into 2 equivalence classes. [2025-02-08 14:28:07,929 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 20 of 20 statements. [2025-02-08 14:28:07,930 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:07,930 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,930 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:07,933 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 20 statements into 1 equivalence classes. [2025-02-08 14:28:07,951 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 20 of 20 statements. [2025-02-08 14:28:07,951 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,951 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,953 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:07,955 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,955 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 6 times [2025-02-08 14:28:07,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268593809] [2025-02-08 14:28:07,955 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:07,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,958 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:07,958 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:07,959 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:28:07,959 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,959 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:07,959 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:07,960 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:07,960 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:07,960 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:07,961 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:07,961 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:07,961 INFO L85 PathProgramCache]: Analyzing trace with hash -1451955807, now seen corresponding path program 9 times [2025-02-08 14:28:07,961 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:07,961 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1134078633] [2025-02-08 14:28:07,961 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:07,961 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:07,967 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 23 statements into 6 equivalence classes. [2025-02-08 14:28:08,004 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 23 of 23 statements. [2025-02-08 14:28:08,004 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-02-08 14:28:08,004 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:08,153 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 22 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:08,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:08,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1134078633] [2025-02-08 14:28:08,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1134078633] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:08,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1021175162] [2025-02-08 14:28:08,154 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:08,154 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:08,154 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:08,160 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:08,172 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2025-02-08 14:28:08,205 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 23 statements into 6 equivalence classes. [2025-02-08 14:28:08,230 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 23 of 23 statements. [2025-02-08 14:28:08,230 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-02-08 14:28:08,230 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:08,231 INFO L256 TraceCheckSpWp]: Trace formula consists of 146 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-02-08 14:28:08,232 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:08,343 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:08,343 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:08,444 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 35 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:08,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1021175162] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:08,444 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:08,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12] total 20 [2025-02-08 14:28:08,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [850602877] [2025-02-08 14:28:08,444 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:08,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:08,481 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-02-08 14:28:08,481 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=340, Unknown=0, NotChecked=0, Total=462 [2025-02-08 14:28:08,481 INFO L87 Difference]: Start difference. First operand 38 states and 46 transitions. cyclomatic complexity: 11 Second operand has 22 states, 21 states have (on average 2.1904761904761907) internal successors, (46), 21 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:08,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:08,664 INFO L93 Difference]: Finished difference Result 130 states and 157 transitions. [2025-02-08 14:28:08,664 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 130 states and 157 transitions. [2025-02-08 14:28:08,665 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:08,665 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 130 states to 78 states and 94 transitions. [2025-02-08 14:28:08,665 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 72 [2025-02-08 14:28:08,665 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 72 [2025-02-08 14:28:08,665 INFO L73 IsDeterministic]: Start isDeterministic. Operand 78 states and 94 transitions. [2025-02-08 14:28:08,666 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:08,666 INFO L218 hiAutomatonCegarLoop]: Abstraction has 78 states and 94 transitions. [2025-02-08 14:28:08,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states and 94 transitions. [2025-02-08 14:28:08,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 44. [2025-02-08 14:28:08,668 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 44 states, 44 states have (on average 1.2045454545454546) internal successors, (53), 43 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:08,668 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 53 transitions. [2025-02-08 14:28:08,668 INFO L240 hiAutomatonCegarLoop]: Abstraction has 44 states and 53 transitions. [2025-02-08 14:28:08,669 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-02-08 14:28:08,669 INFO L432 stractBuchiCegarLoop]: Abstraction has 44 states and 53 transitions. [2025-02-08 14:28:08,669 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-08 14:28:08,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 44 states and 53 transitions. [2025-02-08 14:28:08,670 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:08,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:08,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:08,670 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 1, 1] [2025-02-08 14:28:08,670 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:08,670 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:08,670 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:08,671 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:08,671 INFO L85 PathProgramCache]: Analyzing trace with hash 2073829383, now seen corresponding path program 10 times [2025-02-08 14:28:08,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:08,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1637285476] [2025-02-08 14:28:08,671 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:08,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:08,678 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 24 statements into 2 equivalence classes. [2025-02-08 14:28:08,695 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 24 of 24 statements. [2025-02-08 14:28:08,695 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:08,695 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:08,695 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:08,697 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 24 statements into 1 equivalence classes. [2025-02-08 14:28:08,709 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 24 of 24 statements. [2025-02-08 14:28:08,709 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:08,709 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:08,712 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:08,713 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:08,713 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 7 times [2025-02-08 14:28:08,713 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:08,713 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2053901385] [2025-02-08 14:28:08,713 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:08,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:08,715 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:08,716 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:08,716 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:08,716 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:08,716 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:08,717 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:08,718 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:08,718 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:08,718 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:08,719 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:08,719 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:08,719 INFO L85 PathProgramCache]: Analyzing trace with hash -1653381415, now seen corresponding path program 11 times [2025-02-08 14:28:08,719 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:08,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119314741] [2025-02-08 14:28:08,719 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:08,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:08,726 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 27 statements into 7 equivalence classes. [2025-02-08 14:28:08,741 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 27 of 27 statements. [2025-02-08 14:28:08,741 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-02-08 14:28:08,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:08,933 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:08,933 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:08,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [119314741] [2025-02-08 14:28:08,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [119314741] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:08,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [97227311] [2025-02-08 14:28:08,933 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:08,934 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:08,934 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:08,938 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:08,939 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2025-02-08 14:28:08,974 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 27 statements into 7 equivalence classes. [2025-02-08 14:28:09,011 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) and asserted 27 of 27 statements. [2025-02-08 14:28:09,011 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2025-02-08 14:28:09,011 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:09,012 INFO L256 TraceCheckSpWp]: Trace formula consists of 167 conjuncts, 16 conjuncts are in the unsatisfiable core [2025-02-08 14:28:09,014 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:09,179 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:09,179 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:09,293 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 51 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:09,294 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [97227311] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:09,294 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:09,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 21 [2025-02-08 14:28:09,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1848324341] [2025-02-08 14:28:09,294 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:09,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:09,329 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2025-02-08 14:28:09,330 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=372, Unknown=0, NotChecked=0, Total=506 [2025-02-08 14:28:09,330 INFO L87 Difference]: Start difference. First operand 44 states and 53 transitions. cyclomatic complexity: 12 Second operand has 23 states, 22 states have (on average 2.1363636363636362) internal successors, (47), 22 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:09,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:09,543 INFO L93 Difference]: Finished difference Result 151 states and 182 transitions. [2025-02-08 14:28:09,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 151 states and 182 transitions. [2025-02-08 14:28:09,544 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:09,545 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 151 states to 89 states and 107 transitions. [2025-02-08 14:28:09,545 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 82 [2025-02-08 14:28:09,545 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 82 [2025-02-08 14:28:09,545 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89 states and 107 transitions. [2025-02-08 14:28:09,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:09,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89 states and 107 transitions. [2025-02-08 14:28:09,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states and 107 transitions. [2025-02-08 14:28:09,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 50. [2025-02-08 14:28:09,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 50 states, 50 states have (on average 1.2) internal successors, (60), 49 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:09,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 60 transitions. [2025-02-08 14:28:09,548 INFO L240 hiAutomatonCegarLoop]: Abstraction has 50 states and 60 transitions. [2025-02-08 14:28:09,548 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2025-02-08 14:28:09,548 INFO L432 stractBuchiCegarLoop]: Abstraction has 50 states and 60 transitions. [2025-02-08 14:28:09,548 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-08 14:28:09,548 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 50 states and 60 transitions. [2025-02-08 14:28:09,549 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:09,549 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:09,549 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:09,549 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [7, 7, 6, 6, 1, 1] [2025-02-08 14:28:09,549 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:09,549 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:09,549 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:09,551 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:09,551 INFO L85 PathProgramCache]: Analyzing trace with hash 44890687, now seen corresponding path program 12 times [2025-02-08 14:28:09,552 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:09,552 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933793269] [2025-02-08 14:28:09,552 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:09,552 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:09,565 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 28 statements into 7 equivalence classes. [2025-02-08 14:28:09,609 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) and asserted 28 of 28 statements. [2025-02-08 14:28:09,610 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2025-02-08 14:28:09,610 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:09,610 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:09,614 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-02-08 14:28:09,643 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-02-08 14:28:09,643 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:09,643 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:09,649 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:09,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:09,651 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 8 times [2025-02-08 14:28:09,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:09,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [664829467] [2025-02-08 14:28:09,651 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:09,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:09,653 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:09,655 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:09,655 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:09,655 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:09,655 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:09,656 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:09,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:09,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:09,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:09,658 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:09,659 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:09,659 INFO L85 PathProgramCache]: Analyzing trace with hash 1603649953, now seen corresponding path program 13 times [2025-02-08 14:28:09,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:09,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661972053] [2025-02-08 14:28:09,659 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:09,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:09,666 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-02-08 14:28:09,678 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-02-08 14:28:09,679 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:09,679 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:10,049 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 51 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:10,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:10,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661972053] [2025-02-08 14:28:10,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661972053] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:10,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [412604350] [2025-02-08 14:28:10,049 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:10,049 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:10,049 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:10,052 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:10,053 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2025-02-08 14:28:10,100 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-02-08 14:28:10,117 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-02-08 14:28:10,117 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:10,117 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:10,118 INFO L256 TraceCheckSpWp]: Trace formula consists of 188 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-02-08 14:28:10,119 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:10,413 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:10,413 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:10,575 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 70 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:10,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [412604350] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:10,575 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:10,576 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 26 [2025-02-08 14:28:10,576 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436908556] [2025-02-08 14:28:10,576 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:10,611 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:10,612 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2025-02-08 14:28:10,612 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=192, Invalid=564, Unknown=0, NotChecked=0, Total=756 [2025-02-08 14:28:10,612 INFO L87 Difference]: Start difference. First operand 50 states and 60 transitions. cyclomatic complexity: 13 Second operand has 28 states, 27 states have (on average 2.2222222222222223) internal successors, (60), 27 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:10,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:10,855 INFO L93 Difference]: Finished difference Result 172 states and 207 transitions. [2025-02-08 14:28:10,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 172 states and 207 transitions. [2025-02-08 14:28:10,860 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:10,861 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 172 states to 100 states and 120 transitions. [2025-02-08 14:28:10,861 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 92 [2025-02-08 14:28:10,861 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 92 [2025-02-08 14:28:10,861 INFO L73 IsDeterministic]: Start isDeterministic. Operand 100 states and 120 transitions. [2025-02-08 14:28:10,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:10,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 100 states and 120 transitions. [2025-02-08 14:28:10,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states and 120 transitions. [2025-02-08 14:28:10,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 56. [2025-02-08 14:28:10,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 56 states, 56 states have (on average 1.1964285714285714) internal successors, (67), 55 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:10,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 67 transitions. [2025-02-08 14:28:10,865 INFO L240 hiAutomatonCegarLoop]: Abstraction has 56 states and 67 transitions. [2025-02-08 14:28:10,865 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-02-08 14:28:10,866 INFO L432 stractBuchiCegarLoop]: Abstraction has 56 states and 67 transitions. [2025-02-08 14:28:10,866 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-08 14:28:10,866 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 56 states and 67 transitions. [2025-02-08 14:28:10,866 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:10,866 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:10,866 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:10,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [8, 8, 7, 7, 1, 1] [2025-02-08 14:28:10,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:10,867 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:10,867 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:10,868 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:10,868 INFO L85 PathProgramCache]: Analyzing trace with hash -1653919225, now seen corresponding path program 14 times [2025-02-08 14:28:10,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:10,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1015463124] [2025-02-08 14:28:10,868 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:10,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:10,873 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 32 statements into 2 equivalence classes. [2025-02-08 14:28:10,887 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 32 of 32 statements. [2025-02-08 14:28:10,888 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:10,888 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:10,888 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:10,890 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 32 statements into 1 equivalence classes. [2025-02-08 14:28:10,903 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 32 of 32 statements. [2025-02-08 14:28:10,903 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:10,903 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:10,906 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:10,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:10,906 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 9 times [2025-02-08 14:28:10,906 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:10,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [413824112] [2025-02-08 14:28:10,907 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:10,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:10,908 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:10,909 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:10,909 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:28:10,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:10,909 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:10,909 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:10,910 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:10,910 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:10,910 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:10,910 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:10,911 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:10,911 INFO L85 PathProgramCache]: Analyzing trace with hash -42789671, now seen corresponding path program 15 times [2025-02-08 14:28:10,911 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:10,911 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661247432] [2025-02-08 14:28:10,911 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:10,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:10,916 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 35 statements into 9 equivalence classes. [2025-02-08 14:28:10,962 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 35 of 35 statements. [2025-02-08 14:28:10,963 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-02-08 14:28:10,963 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:11,275 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 70 proven. 58 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:11,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:11,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1661247432] [2025-02-08 14:28:11,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1661247432] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:11,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [482463650] [2025-02-08 14:28:11,275 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:11,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:11,276 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:11,283 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:11,284 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-02-08 14:28:11,355 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 35 statements into 9 equivalence classes. [2025-02-08 14:28:11,455 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) and asserted 35 of 35 statements. [2025-02-08 14:28:11,456 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2025-02-08 14:28:11,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:11,457 INFO L256 TraceCheckSpWp]: Trace formula consists of 209 conjuncts, 20 conjuncts are in the unsatisfiable core [2025-02-08 14:28:11,458 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:11,651 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:11,651 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:11,786 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 92 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:11,786 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [482463650] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:11,786 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:11,786 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18] total 29 [2025-02-08 14:28:11,786 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1805499101] [2025-02-08 14:28:11,787 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:11,817 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:11,817 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-02-08 14:28:11,818 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=697, Unknown=0, NotChecked=0, Total=930 [2025-02-08 14:28:11,818 INFO L87 Difference]: Start difference. First operand 56 states and 67 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.2333333333333334) internal successors, (67), 30 states have internal predecessors, (67), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:12,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:12,079 INFO L93 Difference]: Finished difference Result 193 states and 232 transitions. [2025-02-08 14:28:12,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 193 states and 232 transitions. [2025-02-08 14:28:12,080 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:12,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 193 states to 111 states and 133 transitions. [2025-02-08 14:28:12,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102 [2025-02-08 14:28:12,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102 [2025-02-08 14:28:12,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111 states and 133 transitions. [2025-02-08 14:28:12,081 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:12,081 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111 states and 133 transitions. [2025-02-08 14:28:12,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states and 133 transitions. [2025-02-08 14:28:12,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 62. [2025-02-08 14:28:12,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 62 states, 62 states have (on average 1.1935483870967742) internal successors, (74), 61 states have internal predecessors, (74), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:12,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 74 transitions. [2025-02-08 14:28:12,087 INFO L240 hiAutomatonCegarLoop]: Abstraction has 62 states and 74 transitions. [2025-02-08 14:28:12,088 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2025-02-08 14:28:12,088 INFO L432 stractBuchiCegarLoop]: Abstraction has 62 states and 74 transitions. [2025-02-08 14:28:12,088 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-08 14:28:12,088 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 62 states and 74 transitions. [2025-02-08 14:28:12,089 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:12,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:12,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:12,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [9, 9, 8, 8, 1, 1] [2025-02-08 14:28:12,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:12,089 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:12,089 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:12,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:12,091 INFO L85 PathProgramCache]: Analyzing trace with hash 2024661567, now seen corresponding path program 16 times [2025-02-08 14:28:12,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:12,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2033435859] [2025-02-08 14:28:12,091 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:12,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:12,097 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 36 statements into 2 equivalence classes. [2025-02-08 14:28:12,122 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 36 of 36 statements. [2025-02-08 14:28:12,122 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:12,122 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:12,122 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:12,124 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-02-08 14:28:12,139 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-02-08 14:28:12,139 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:12,139 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:12,143 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:12,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:12,144 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 10 times [2025-02-08 14:28:12,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:12,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137788845] [2025-02-08 14:28:12,144 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:12,144 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:12,145 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-08 14:28:12,150 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:12,150 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:12,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:12,150 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:12,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:12,151 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:12,151 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:12,151 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:12,152 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:12,152 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:12,152 INFO L85 PathProgramCache]: Analyzing trace with hash -1827939935, now seen corresponding path program 17 times [2025-02-08 14:28:12,152 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:12,152 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1762209124] [2025-02-08 14:28:12,152 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:12,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:12,162 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 39 statements into 10 equivalence classes. [2025-02-08 14:28:12,181 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 39 of 39 statements. [2025-02-08 14:28:12,181 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-02-08 14:28:12,181 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:12,521 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 108 proven. 54 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:12,522 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:12,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1762209124] [2025-02-08 14:28:12,522 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1762209124] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:12,522 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1954135226] [2025-02-08 14:28:12,522 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:12,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:12,522 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:12,524 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:12,525 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-02-08 14:28:12,574 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 39 statements into 10 equivalence classes. [2025-02-08 14:28:12,639 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) and asserted 39 of 39 statements. [2025-02-08 14:28:12,639 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2025-02-08 14:28:12,639 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:12,641 INFO L256 TraceCheckSpWp]: Trace formula consists of 230 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-02-08 14:28:12,642 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:13,073 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:13,074 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:13,347 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 117 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:13,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1954135226] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:13,348 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:13,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20, 20] total 41 [2025-02-08 14:28:13,348 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [998150466] [2025-02-08 14:28:13,348 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:13,380 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:13,381 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2025-02-08 14:28:13,381 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=318, Invalid=1488, Unknown=0, NotChecked=0, Total=1806 [2025-02-08 14:28:13,382 INFO L87 Difference]: Start difference. First operand 62 states and 74 transitions. cyclomatic complexity: 15 Second operand has 43 states, 42 states have (on average 1.9047619047619047) internal successors, (80), 42 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:14,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:14,387 INFO L93 Difference]: Finished difference Result 260 states and 311 transitions. [2025-02-08 14:28:14,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 260 states and 311 transitions. [2025-02-08 14:28:14,389 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:14,390 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 260 states to 122 states and 146 transitions. [2025-02-08 14:28:14,390 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 112 [2025-02-08 14:28:14,390 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 112 [2025-02-08 14:28:14,390 INFO L73 IsDeterministic]: Start isDeterministic. Operand 122 states and 146 transitions. [2025-02-08 14:28:14,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:14,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 122 states and 146 transitions. [2025-02-08 14:28:14,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states and 146 transitions. [2025-02-08 14:28:14,392 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 68. [2025-02-08 14:28:14,392 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 68 states, 68 states have (on average 1.1911764705882353) internal successors, (81), 67 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:14,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 68 states to 68 states and 81 transitions. [2025-02-08 14:28:14,392 INFO L240 hiAutomatonCegarLoop]: Abstraction has 68 states and 81 transitions. [2025-02-08 14:28:14,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2025-02-08 14:28:14,393 INFO L432 stractBuchiCegarLoop]: Abstraction has 68 states and 81 transitions. [2025-02-08 14:28:14,393 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-08 14:28:14,393 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 68 states and 81 transitions. [2025-02-08 14:28:14,394 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:14,394 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:14,394 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:14,394 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [10, 10, 9, 9, 1, 1] [2025-02-08 14:28:14,394 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:14,394 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:14,394 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:14,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:14,396 INFO L85 PathProgramCache]: Analyzing trace with hash 800424967, now seen corresponding path program 18 times [2025-02-08 14:28:14,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:14,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [39548667] [2025-02-08 14:28:14,396 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:14,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:14,406 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 40 statements into 10 equivalence classes. [2025-02-08 14:28:14,462 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) and asserted 40 of 40 statements. [2025-02-08 14:28:14,463 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 10 check-sat command(s) [2025-02-08 14:28:14,463 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:14,464 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:14,467 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-02-08 14:28:14,493 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-02-08 14:28:14,495 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:14,495 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:14,503 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:14,504 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:14,504 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 11 times [2025-02-08 14:28:14,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:14,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [167794782] [2025-02-08 14:28:14,504 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:14,504 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:14,508 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:14,509 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:14,509 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:14,509 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:14,509 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:14,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:14,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:14,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:14,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:14,512 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:14,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:14,513 INFO L85 PathProgramCache]: Analyzing trace with hash -198212903, now seen corresponding path program 19 times [2025-02-08 14:28:14,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:14,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213218664] [2025-02-08 14:28:14,513 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:14,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:14,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-08 14:28:14,528 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-08 14:28:14,528 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:14,528 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:14,837 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 117 proven. 83 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:14,838 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:14,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213218664] [2025-02-08 14:28:14,838 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213218664] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:14,838 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1462536863] [2025-02-08 14:28:14,838 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:14,838 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:14,838 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:14,841 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:14,842 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-02-08 14:28:14,892 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-02-08 14:28:14,913 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-02-08 14:28:14,913 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:14,913 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:14,914 INFO L256 TraceCheckSpWp]: Trace formula consists of 251 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-02-08 14:28:14,915 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:15,184 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:15,184 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:15,365 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 145 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:15,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1462536863] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:15,365 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:15,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22] total 35 [2025-02-08 14:28:15,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1677660056] [2025-02-08 14:28:15,365 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:15,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:15,396 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2025-02-08 14:28:15,396 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=327, Invalid=1005, Unknown=0, NotChecked=0, Total=1332 [2025-02-08 14:28:15,396 INFO L87 Difference]: Start difference. First operand 68 states and 81 transitions. cyclomatic complexity: 16 Second operand has 37 states, 36 states have (on average 2.25) internal successors, (81), 36 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:15,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:15,801 INFO L93 Difference]: Finished difference Result 235 states and 282 transitions. [2025-02-08 14:28:15,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 235 states and 282 transitions. [2025-02-08 14:28:15,802 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:15,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 235 states to 133 states and 159 transitions. [2025-02-08 14:28:15,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 122 [2025-02-08 14:28:15,803 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 122 [2025-02-08 14:28:15,803 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133 states and 159 transitions. [2025-02-08 14:28:15,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:15,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133 states and 159 transitions. [2025-02-08 14:28:15,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states and 159 transitions. [2025-02-08 14:28:15,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 74. [2025-02-08 14:28:15,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.1891891891891893) internal successors, (88), 73 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:15,805 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 88 transitions. [2025-02-08 14:28:15,805 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 88 transitions. [2025-02-08 14:28:15,806 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2025-02-08 14:28:15,806 INFO L432 stractBuchiCegarLoop]: Abstraction has 74 states and 88 transitions. [2025-02-08 14:28:15,806 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-08 14:28:15,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 88 transitions. [2025-02-08 14:28:15,807 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:15,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:15,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:15,807 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [11, 11, 10, 10, 1, 1] [2025-02-08 14:28:15,807 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:15,807 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:15,808 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:15,808 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:15,809 INFO L85 PathProgramCache]: Analyzing trace with hash 1972472383, now seen corresponding path program 20 times [2025-02-08 14:28:15,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:15,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345587466] [2025-02-08 14:28:15,809 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:15,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:15,815 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 44 statements into 2 equivalence classes. [2025-02-08 14:28:15,833 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 44 of 44 statements. [2025-02-08 14:28:15,834 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:15,834 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:15,834 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:15,836 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-02-08 14:28:15,848 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-02-08 14:28:15,848 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:15,848 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:15,851 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:15,852 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:15,852 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 12 times [2025-02-08 14:28:15,852 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:15,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [257226590] [2025-02-08 14:28:15,852 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:15,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:15,854 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:15,854 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:15,854 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:28:15,854 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:15,855 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:15,855 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:15,855 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:15,855 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:15,856 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:15,856 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:15,857 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:15,857 INFO L85 PathProgramCache]: Analyzing trace with hash -1817759327, now seen corresponding path program 21 times [2025-02-08 14:28:15,857 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:15,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681952057] [2025-02-08 14:28:15,857 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:15,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:15,863 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 47 statements into 12 equivalence classes. [2025-02-08 14:28:15,940 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 47 of 47 statements. [2025-02-08 14:28:15,940 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-02-08 14:28:15,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:16,299 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 145 proven. 97 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:16,299 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:16,299 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681952057] [2025-02-08 14:28:16,300 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681952057] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:16,300 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1713777181] [2025-02-08 14:28:16,300 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:16,300 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:16,300 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:16,308 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:16,309 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-02-08 14:28:16,359 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 47 statements into 12 equivalence classes. [2025-02-08 14:28:16,456 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) and asserted 47 of 47 statements. [2025-02-08 14:28:16,456 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2025-02-08 14:28:16,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:16,461 INFO L256 TraceCheckSpWp]: Trace formula consists of 272 conjuncts, 26 conjuncts are in the unsatisfiable core [2025-02-08 14:28:16,462 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:16,748 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:16,748 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:16,951 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 176 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:16,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1713777181] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:16,952 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:16,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24] total 38 [2025-02-08 14:28:16,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119620719] [2025-02-08 14:28:16,952 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:16,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:16,981 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2025-02-08 14:28:16,981 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=380, Invalid=1180, Unknown=0, NotChecked=0, Total=1560 [2025-02-08 14:28:16,981 INFO L87 Difference]: Start difference. First operand 74 states and 88 transitions. cyclomatic complexity: 17 Second operand has 40 states, 39 states have (on average 2.2564102564102564) internal successors, (88), 39 states have internal predecessors, (88), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:17,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:17,322 INFO L93 Difference]: Finished difference Result 256 states and 307 transitions. [2025-02-08 14:28:17,322 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 256 states and 307 transitions. [2025-02-08 14:28:17,323 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:17,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 256 states to 144 states and 172 transitions. [2025-02-08 14:28:17,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 132 [2025-02-08 14:28:17,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 132 [2025-02-08 14:28:17,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144 states and 172 transitions. [2025-02-08 14:28:17,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:17,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144 states and 172 transitions. [2025-02-08 14:28:17,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states and 172 transitions. [2025-02-08 14:28:17,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 80. [2025-02-08 14:28:17,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80 states, 80 states have (on average 1.1875) internal successors, (95), 79 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:17,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 95 transitions. [2025-02-08 14:28:17,327 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80 states and 95 transitions. [2025-02-08 14:28:17,327 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2025-02-08 14:28:17,327 INFO L432 stractBuchiCegarLoop]: Abstraction has 80 states and 95 transitions. [2025-02-08 14:28:17,327 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-08 14:28:17,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80 states and 95 transitions. [2025-02-08 14:28:17,328 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:17,328 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:17,328 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:17,328 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [12, 12, 11, 11, 1, 1] [2025-02-08 14:28:17,328 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:17,329 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:17,329 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:17,329 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:17,329 INFO L85 PathProgramCache]: Analyzing trace with hash -62188025, now seen corresponding path program 22 times [2025-02-08 14:28:17,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:17,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704078714] [2025-02-08 14:28:17,329 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:17,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:17,336 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 48 statements into 2 equivalence classes. [2025-02-08 14:28:17,361 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 48 of 48 statements. [2025-02-08 14:28:17,361 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:17,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:17,361 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:17,363 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-02-08 14:28:17,383 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-02-08 14:28:17,384 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:17,384 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:17,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:17,391 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:17,391 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 13 times [2025-02-08 14:28:17,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:17,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [218820747] [2025-02-08 14:28:17,391 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:17,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:17,393 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:17,394 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:17,394 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:17,395 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:17,395 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:17,395 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:17,396 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:17,396 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:17,396 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:17,397 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:17,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:17,397 INFO L85 PathProgramCache]: Analyzing trace with hash -1512525607, now seen corresponding path program 23 times [2025-02-08 14:28:17,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:17,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [49173285] [2025-02-08 14:28:17,397 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:17,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:17,404 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 51 statements into 13 equivalence classes. [2025-02-08 14:28:17,424 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 51 of 51 statements. [2025-02-08 14:28:17,425 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-02-08 14:28:17,425 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:17,850 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:17,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:17,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [49173285] [2025-02-08 14:28:17,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [49173285] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:17,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [834670384] [2025-02-08 14:28:17,851 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:17,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:17,851 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:17,855 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:17,860 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-02-08 14:28:17,916 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 51 statements into 13 equivalence classes. [2025-02-08 14:28:18,054 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) and asserted 51 of 51 statements. [2025-02-08 14:28:18,055 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2025-02-08 14:28:18,055 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:18,057 INFO L256 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 28 conjuncts are in the unsatisfiable core [2025-02-08 14:28:18,058 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:18,394 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:18,394 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:18,631 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 210 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:18,631 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [834670384] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:18,632 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:18,632 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26] total 39 [2025-02-08 14:28:18,632 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1468907370] [2025-02-08 14:28:18,632 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:18,664 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:18,665 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2025-02-08 14:28:18,665 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=404, Invalid=1236, Unknown=0, NotChecked=0, Total=1640 [2025-02-08 14:28:18,665 INFO L87 Difference]: Start difference. First operand 80 states and 95 transitions. cyclomatic complexity: 18 Second operand has 41 states, 40 states have (on average 2.225) internal successors, (89), 40 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:19,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:19,041 INFO L93 Difference]: Finished difference Result 277 states and 332 transitions. [2025-02-08 14:28:19,041 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 277 states and 332 transitions. [2025-02-08 14:28:19,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:19,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 277 states to 155 states and 185 transitions. [2025-02-08 14:28:19,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 142 [2025-02-08 14:28:19,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 142 [2025-02-08 14:28:19,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 155 states and 185 transitions. [2025-02-08 14:28:19,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:19,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 155 states and 185 transitions. [2025-02-08 14:28:19,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states and 185 transitions. [2025-02-08 14:28:19,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 86. [2025-02-08 14:28:19,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 86 states, 86 states have (on average 1.186046511627907) internal successors, (102), 85 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:19,055 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 102 transitions. [2025-02-08 14:28:19,055 INFO L240 hiAutomatonCegarLoop]: Abstraction has 86 states and 102 transitions. [2025-02-08 14:28:19,056 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2025-02-08 14:28:19,057 INFO L432 stractBuchiCegarLoop]: Abstraction has 86 states and 102 transitions. [2025-02-08 14:28:19,057 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-08 14:28:19,057 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 86 states and 102 transitions. [2025-02-08 14:28:19,057 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:19,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:19,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:19,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [13, 13, 12, 12, 1, 1] [2025-02-08 14:28:19,062 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:19,062 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:19,064 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:19,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:19,064 INFO L85 PathProgramCache]: Analyzing trace with hash -1752698305, now seen corresponding path program 24 times [2025-02-08 14:28:19,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:19,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711637284] [2025-02-08 14:28:19,064 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:19,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:19,072 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 52 statements into 13 equivalence classes. [2025-02-08 14:28:19,175 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) and asserted 52 of 52 statements. [2025-02-08 14:28:19,176 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2025-02-08 14:28:19,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:19,176 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:19,180 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 52 statements into 1 equivalence classes. [2025-02-08 14:28:19,205 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 52 of 52 statements. [2025-02-08 14:28:19,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:19,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:19,212 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:19,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:19,212 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 14 times [2025-02-08 14:28:19,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:19,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331186220] [2025-02-08 14:28:19,213 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:19,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:19,215 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:19,216 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:19,216 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:19,216 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:19,216 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:19,216 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:19,217 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:19,217 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:19,217 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:19,218 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:19,219 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:19,219 INFO L85 PathProgramCache]: Analyzing trace with hash -717764191, now seen corresponding path program 25 times [2025-02-08 14:28:19,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:19,219 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1061317479] [2025-02-08 14:28:19,219 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:19,219 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:19,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes. [2025-02-08 14:28:19,237 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements. [2025-02-08 14:28:19,238 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:19,238 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:19,846 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 210 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:19,846 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:19,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1061317479] [2025-02-08 14:28:19,846 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1061317479] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:19,846 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [513752863] [2025-02-08 14:28:19,846 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:19,846 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:19,847 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:19,849 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:19,851 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-02-08 14:28:19,913 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 55 statements into 1 equivalence classes. [2025-02-08 14:28:19,940 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 55 of 55 statements. [2025-02-08 14:28:19,940 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:19,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:19,941 INFO L256 TraceCheckSpWp]: Trace formula consists of 314 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-02-08 14:28:19,943 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:20,354 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:20,355 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:20,620 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 247 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:20,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [513752863] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:20,620 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:20,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28] total 44 [2025-02-08 14:28:20,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [219505242] [2025-02-08 14:28:20,621 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:20,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:20,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2025-02-08 14:28:20,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=498, Invalid=1572, Unknown=0, NotChecked=0, Total=2070 [2025-02-08 14:28:20,651 INFO L87 Difference]: Start difference. First operand 86 states and 102 transitions. cyclomatic complexity: 19 Second operand has 46 states, 45 states have (on average 2.2666666666666666) internal successors, (102), 45 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:21,084 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:21,084 INFO L93 Difference]: Finished difference Result 298 states and 357 transitions. [2025-02-08 14:28:21,084 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 298 states and 357 transitions. [2025-02-08 14:28:21,086 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:21,086 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 298 states to 166 states and 198 transitions. [2025-02-08 14:28:21,086 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152 [2025-02-08 14:28:21,086 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152 [2025-02-08 14:28:21,086 INFO L73 IsDeterministic]: Start isDeterministic. Operand 166 states and 198 transitions. [2025-02-08 14:28:21,087 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:21,087 INFO L218 hiAutomatonCegarLoop]: Abstraction has 166 states and 198 transitions. [2025-02-08 14:28:21,087 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states and 198 transitions. [2025-02-08 14:28:21,088 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 92. [2025-02-08 14:28:21,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 92 states, 92 states have (on average 1.184782608695652) internal successors, (109), 91 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:21,089 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 109 transitions. [2025-02-08 14:28:21,089 INFO L240 hiAutomatonCegarLoop]: Abstraction has 92 states and 109 transitions. [2025-02-08 14:28:21,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2025-02-08 14:28:21,090 INFO L432 stractBuchiCegarLoop]: Abstraction has 92 states and 109 transitions. [2025-02-08 14:28:21,090 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-08 14:28:21,090 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 92 states and 109 transitions. [2025-02-08 14:28:21,090 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:21,090 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:21,090 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:21,091 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [14, 14, 13, 13, 1, 1] [2025-02-08 14:28:21,091 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:21,091 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:21,091 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:21,091 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:21,091 INFO L85 PathProgramCache]: Analyzing trace with hash -251926521, now seen corresponding path program 26 times [2025-02-08 14:28:21,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:21,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779811104] [2025-02-08 14:28:21,092 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:21,092 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:21,099 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 56 statements into 2 equivalence classes. [2025-02-08 14:28:21,125 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 56 of 56 statements. [2025-02-08 14:28:21,125 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:21,125 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:21,125 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:21,128 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-02-08 14:28:21,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-02-08 14:28:21,154 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:21,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:21,159 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:21,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:21,159 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 15 times [2025-02-08 14:28:21,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:21,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136274235] [2025-02-08 14:28:21,160 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:21,160 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:21,161 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:21,162 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:21,162 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:28:21,162 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:21,162 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:21,163 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:21,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:21,163 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:21,163 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:21,164 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:21,165 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:21,165 INFO L85 PathProgramCache]: Analyzing trace with hash -1835098407, now seen corresponding path program 27 times [2025-02-08 14:28:21,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:21,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [304936755] [2025-02-08 14:28:21,165 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:21,165 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:21,173 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 59 statements into 15 equivalence classes. [2025-02-08 14:28:21,329 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 59 of 59 statements. [2025-02-08 14:28:21,330 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-02-08 14:28:21,330 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:21,781 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 247 proven. 145 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:21,781 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:21,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [304936755] [2025-02-08 14:28:21,781 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [304936755] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:21,781 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [296027581] [2025-02-08 14:28:21,781 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:21,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:21,781 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:21,790 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:21,793 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-02-08 14:28:21,864 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 59 statements into 15 equivalence classes. [2025-02-08 14:28:22,311 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) and asserted 59 of 59 statements. [2025-02-08 14:28:22,311 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2025-02-08 14:28:22,311 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:22,314 INFO L256 TraceCheckSpWp]: Trace formula consists of 335 conjuncts, 32 conjuncts are in the unsatisfiable core [2025-02-08 14:28:22,316 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:22,705 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:22,705 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:23,022 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 287 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:23,022 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [296027581] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:23,022 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:23,022 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30] total 47 [2025-02-08 14:28:23,022 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [682020847] [2025-02-08 14:28:23,022 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:23,048 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:23,048 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2025-02-08 14:28:23,048 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=563, Invalid=1789, Unknown=0, NotChecked=0, Total=2352 [2025-02-08 14:28:23,049 INFO L87 Difference]: Start difference. First operand 92 states and 109 transitions. cyclomatic complexity: 20 Second operand has 49 states, 48 states have (on average 2.2708333333333335) internal successors, (109), 48 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:23,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:23,451 INFO L93 Difference]: Finished difference Result 319 states and 382 transitions. [2025-02-08 14:28:23,451 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 319 states and 382 transitions. [2025-02-08 14:28:23,452 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:23,453 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 319 states to 177 states and 211 transitions. [2025-02-08 14:28:23,453 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162 [2025-02-08 14:28:23,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162 [2025-02-08 14:28:23,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 177 states and 211 transitions. [2025-02-08 14:28:23,453 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:23,453 INFO L218 hiAutomatonCegarLoop]: Abstraction has 177 states and 211 transitions. [2025-02-08 14:28:23,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states and 211 transitions. [2025-02-08 14:28:23,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 98. [2025-02-08 14:28:23,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 98 states, 98 states have (on average 1.183673469387755) internal successors, (116), 97 states have internal predecessors, (116), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:23,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 116 transitions. [2025-02-08 14:28:23,458 INFO L240 hiAutomatonCegarLoop]: Abstraction has 98 states and 116 transitions. [2025-02-08 14:28:23,462 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-02-08 14:28:23,462 INFO L432 stractBuchiCegarLoop]: Abstraction has 98 states and 116 transitions. [2025-02-08 14:28:23,463 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-08 14:28:23,463 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 98 states and 116 transitions. [2025-02-08 14:28:23,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:23,464 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:23,464 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:23,464 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [15, 15, 14, 14, 1, 1] [2025-02-08 14:28:23,465 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:23,465 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:23,465 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:23,465 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:23,465 INFO L85 PathProgramCache]: Analyzing trace with hash -658433473, now seen corresponding path program 28 times [2025-02-08 14:28:23,465 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:23,465 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [286769067] [2025-02-08 14:28:23,466 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:23,466 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:23,473 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 60 statements into 2 equivalence classes. [2025-02-08 14:28:23,507 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 60 of 60 statements. [2025-02-08 14:28:23,508 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:23,509 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:23,509 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:23,511 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 60 statements into 1 equivalence classes. [2025-02-08 14:28:23,538 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 60 of 60 statements. [2025-02-08 14:28:23,539 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:23,539 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:23,544 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:23,545 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:23,545 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 16 times [2025-02-08 14:28:23,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:23,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971357089] [2025-02-08 14:28:23,545 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:23,546 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:23,547 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-08 14:28:23,548 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:23,548 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:23,548 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:23,548 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:23,548 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:23,549 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:23,549 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:23,549 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:23,550 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:23,550 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:23,550 INFO L85 PathProgramCache]: Analyzing trace with hash -275930719, now seen corresponding path program 29 times [2025-02-08 14:28:23,550 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:23,550 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198954468] [2025-02-08 14:28:23,550 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:23,551 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:23,558 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 63 statements into 16 equivalence classes. [2025-02-08 14:28:23,585 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 63 of 63 statements. [2025-02-08 14:28:23,585 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-02-08 14:28:23,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:24,203 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 315 proven. 135 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:24,203 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:24,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198954468] [2025-02-08 14:28:24,203 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198954468] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:24,203 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1640414377] [2025-02-08 14:28:24,203 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:24,203 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:24,203 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:24,206 INFO L229 MonitoredProcess]: Starting monitored process 25 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:24,208 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (25)] Waiting until timeout for monitored process [2025-02-08 14:28:24,277 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 63 statements into 16 equivalence classes. [2025-02-08 14:28:24,414 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) and asserted 63 of 63 statements. [2025-02-08 14:28:24,414 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2025-02-08 14:28:24,414 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:24,418 INFO L256 TraceCheckSpWp]: Trace formula consists of 356 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-02-08 14:28:24,419 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:25,302 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:25,303 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:25,847 INFO L134 CoverageAnalysis]: Checked inductivity of 450 backedges. 330 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:25,847 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1640414377] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:25,847 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:25,847 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 32, 32] total 65 [2025-02-08 14:28:25,847 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342913882] [2025-02-08 14:28:25,847 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:25,878 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:25,879 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-02-08 14:28:25,880 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=747, Invalid=3675, Unknown=0, NotChecked=0, Total=4422 [2025-02-08 14:28:25,880 INFO L87 Difference]: Start difference. First operand 98 states and 116 transitions. cyclomatic complexity: 21 Second operand has 67 states, 66 states have (on average 1.9393939393939394) internal successors, (128), 66 states have internal predecessors, (128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:27,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:27,606 INFO L93 Difference]: Finished difference Result 416 states and 497 transitions. [2025-02-08 14:28:27,606 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 416 states and 497 transitions. [2025-02-08 14:28:27,609 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:27,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 416 states to 188 states and 224 transitions. [2025-02-08 14:28:27,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 172 [2025-02-08 14:28:27,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 172 [2025-02-08 14:28:27,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 188 states and 224 transitions. [2025-02-08 14:28:27,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:27,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 188 states and 224 transitions. [2025-02-08 14:28:27,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states and 224 transitions. [2025-02-08 14:28:27,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 104. [2025-02-08 14:28:27,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 104 states, 104 states have (on average 1.1826923076923077) internal successors, (123), 103 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:27,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 123 transitions. [2025-02-08 14:28:27,616 INFO L240 hiAutomatonCegarLoop]: Abstraction has 104 states and 123 transitions. [2025-02-08 14:28:27,617 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2025-02-08 14:28:27,617 INFO L432 stractBuchiCegarLoop]: Abstraction has 104 states and 123 transitions. [2025-02-08 14:28:27,617 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-08 14:28:27,617 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 104 states and 123 transitions. [2025-02-08 14:28:27,618 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:27,618 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:27,618 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:27,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [16, 16, 15, 15, 1, 1] [2025-02-08 14:28:27,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:27,622 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:27,622 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:27,622 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:27,622 INFO L85 PathProgramCache]: Analyzing trace with hash 530053639, now seen corresponding path program 30 times [2025-02-08 14:28:27,622 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:27,622 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [83681286] [2025-02-08 14:28:27,622 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:27,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:27,638 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 64 statements into 16 equivalence classes. [2025-02-08 14:28:27,748 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) and asserted 64 of 64 statements. [2025-02-08 14:28:27,749 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 16 check-sat command(s) [2025-02-08 14:28:27,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:27,749 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:27,753 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 64 statements into 1 equivalence classes. [2025-02-08 14:28:27,780 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 64 of 64 statements. [2025-02-08 14:28:27,781 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:27,781 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:27,785 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:27,785 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:27,785 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 17 times [2025-02-08 14:28:27,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:27,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138724276] [2025-02-08 14:28:27,785 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:27,786 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:27,787 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:27,788 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:27,788 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:27,788 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:27,788 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:27,788 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:27,789 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:27,789 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:27,789 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:27,790 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:27,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:27,790 INFO L85 PathProgramCache]: Analyzing trace with hash -1766765351, now seen corresponding path program 31 times [2025-02-08 14:28:27,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:27,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1078355133] [2025-02-08 14:28:27,790 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:27,791 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:27,798 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-02-08 14:28:27,805 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-02-08 14:28:27,805 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:27,805 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:28,422 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 330 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:28,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:28,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1078355133] [2025-02-08 14:28:28,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1078355133] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:28,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [851576990] [2025-02-08 14:28:28,423 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:28,423 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:28,423 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:28,425 INFO L229 MonitoredProcess]: Starting monitored process 26 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:28,426 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (26)] Waiting until timeout for monitored process [2025-02-08 14:28:28,514 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 67 statements into 1 equivalence classes. [2025-02-08 14:28:28,571 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 67 of 67 statements. [2025-02-08 14:28:28,572 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:28,572 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:28,574 INFO L256 TraceCheckSpWp]: Trace formula consists of 377 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-02-08 14:28:28,575 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:29,122 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:29,122 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:29,554 INFO L134 CoverageAnalysis]: Checked inductivity of 512 backedges. 376 proven. 136 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:29,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [851576990] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:29,555 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:29,555 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34] total 53 [2025-02-08 14:28:29,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139461637] [2025-02-08 14:28:29,555 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:29,585 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:29,585 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2025-02-08 14:28:29,586 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=705, Invalid=2265, Unknown=0, NotChecked=0, Total=2970 [2025-02-08 14:28:29,586 INFO L87 Difference]: Start difference. First operand 104 states and 123 transitions. cyclomatic complexity: 22 Second operand has 55 states, 54 states have (on average 2.2777777777777777) internal successors, (123), 54 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:30,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:30,121 INFO L93 Difference]: Finished difference Result 361 states and 432 transitions. [2025-02-08 14:28:30,121 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 361 states and 432 transitions. [2025-02-08 14:28:30,123 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:30,125 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 361 states to 199 states and 237 transitions. [2025-02-08 14:28:30,125 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 182 [2025-02-08 14:28:30,126 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 182 [2025-02-08 14:28:30,126 INFO L73 IsDeterministic]: Start isDeterministic. Operand 199 states and 237 transitions. [2025-02-08 14:28:30,126 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:30,126 INFO L218 hiAutomatonCegarLoop]: Abstraction has 199 states and 237 transitions. [2025-02-08 14:28:30,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states and 237 transitions. [2025-02-08 14:28:30,130 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 110. [2025-02-08 14:28:30,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.1818181818181819) internal successors, (130), 109 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:30,130 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 130 transitions. [2025-02-08 14:28:30,130 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110 states and 130 transitions. [2025-02-08 14:28:30,134 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2025-02-08 14:28:30,136 INFO L432 stractBuchiCegarLoop]: Abstraction has 110 states and 130 transitions. [2025-02-08 14:28:30,136 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-08 14:28:30,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 130 transitions. [2025-02-08 14:28:30,137 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:30,137 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:30,137 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:30,137 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [17, 17, 16, 16, 1, 1] [2025-02-08 14:28:30,137 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:30,137 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:30,138 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:30,138 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:30,138 INFO L85 PathProgramCache]: Analyzing trace with hash -1888681409, now seen corresponding path program 32 times [2025-02-08 14:28:30,138 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:30,138 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632548894] [2025-02-08 14:28:30,138 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:30,138 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:30,147 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 68 statements into 2 equivalence classes. [2025-02-08 14:28:30,177 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 68 of 68 statements. [2025-02-08 14:28:30,177 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:30,177 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:30,177 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:30,181 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 68 statements into 1 equivalence classes. [2025-02-08 14:28:30,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 68 of 68 statements. [2025-02-08 14:28:30,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:30,209 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:30,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:30,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:30,215 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 18 times [2025-02-08 14:28:30,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:30,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [588664060] [2025-02-08 14:28:30,215 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:30,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:30,217 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:30,218 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:30,218 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:28:30,218 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:30,218 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:30,218 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:30,218 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:30,218 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:30,219 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:30,220 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:30,221 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:30,222 INFO L85 PathProgramCache]: Analyzing trace with hash -1636255327, now seen corresponding path program 33 times [2025-02-08 14:28:30,222 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:30,222 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [943808604] [2025-02-08 14:28:30,222 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:30,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:30,237 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 71 statements into 18 equivalence classes. [2025-02-08 14:28:30,374 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 71 of 71 statements. [2025-02-08 14:28:30,374 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-02-08 14:28:30,374 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:31,211 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 376 proven. 202 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:31,212 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:31,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [943808604] [2025-02-08 14:28:31,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [943808604] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:31,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1113191918] [2025-02-08 14:28:31,212 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:31,212 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:31,212 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:31,214 INFO L229 MonitoredProcess]: Starting monitored process 27 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:31,227 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (27)] Waiting until timeout for monitored process [2025-02-08 14:28:31,305 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 71 statements into 18 equivalence classes. [2025-02-08 14:28:31,807 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) and asserted 71 of 71 statements. [2025-02-08 14:28:31,807 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2025-02-08 14:28:31,807 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:31,811 INFO L256 TraceCheckSpWp]: Trace formula consists of 398 conjuncts, 38 conjuncts are in the unsatisfiable core [2025-02-08 14:28:31,813 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:32,330 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:32,330 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:32,737 INFO L134 CoverageAnalysis]: Checked inductivity of 578 backedges. 425 proven. 153 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:32,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1113191918] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:32,738 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:32,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36] total 56 [2025-02-08 14:28:32,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1665177157] [2025-02-08 14:28:32,738 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:32,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:32,762 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2025-02-08 14:28:32,762 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=782, Invalid=2524, Unknown=0, NotChecked=0, Total=3306 [2025-02-08 14:28:32,763 INFO L87 Difference]: Start difference. First operand 110 states and 130 transitions. cyclomatic complexity: 23 Second operand has 58 states, 57 states have (on average 2.280701754385965) internal successors, (130), 57 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:33,320 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:33,321 INFO L93 Difference]: Finished difference Result 382 states and 457 transitions. [2025-02-08 14:28:33,321 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 382 states and 457 transitions. [2025-02-08 14:28:33,323 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:33,324 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 382 states to 210 states and 250 transitions. [2025-02-08 14:28:33,324 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 192 [2025-02-08 14:28:33,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 192 [2025-02-08 14:28:33,324 INFO L73 IsDeterministic]: Start isDeterministic. Operand 210 states and 250 transitions. [2025-02-08 14:28:33,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:33,324 INFO L218 hiAutomatonCegarLoop]: Abstraction has 210 states and 250 transitions. [2025-02-08 14:28:33,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states and 250 transitions. [2025-02-08 14:28:33,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 116. [2025-02-08 14:28:33,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 116 states, 116 states have (on average 1.1810344827586208) internal successors, (137), 115 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:33,326 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 137 transitions. [2025-02-08 14:28:33,326 INFO L240 hiAutomatonCegarLoop]: Abstraction has 116 states and 137 transitions. [2025-02-08 14:28:33,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2025-02-08 14:28:33,331 INFO L432 stractBuchiCegarLoop]: Abstraction has 116 states and 137 transitions. [2025-02-08 14:28:33,331 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-08 14:28:33,331 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 116 states and 137 transitions. [2025-02-08 14:28:33,332 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:33,332 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:33,332 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:33,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [18, 18, 17, 17, 1, 1] [2025-02-08 14:28:33,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:33,333 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:33,333 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:33,333 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:33,333 INFO L85 PathProgramCache]: Analyzing trace with hash -1108390905, now seen corresponding path program 34 times [2025-02-08 14:28:33,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:33,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1849420102] [2025-02-08 14:28:33,334 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:33,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:33,350 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 72 statements into 2 equivalence classes. [2025-02-08 14:28:33,418 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 72 of 72 statements. [2025-02-08 14:28:33,418 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:33,419 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:33,419 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:33,423 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 72 statements into 1 equivalence classes. [2025-02-08 14:28:33,462 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 72 of 72 statements. [2025-02-08 14:28:33,462 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:33,462 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:33,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:33,470 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:33,470 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 19 times [2025-02-08 14:28:33,470 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:33,470 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [926994461] [2025-02-08 14:28:33,470 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:33,470 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:33,473 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:33,474 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:33,474 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:33,474 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:33,474 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:33,474 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:33,475 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:33,475 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:33,475 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:33,476 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:33,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:33,477 INFO L85 PathProgramCache]: Analyzing trace with hash -364856615, now seen corresponding path program 35 times [2025-02-08 14:28:33,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:33,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1072122585] [2025-02-08 14:28:33,477 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:33,477 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:33,486 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 75 statements into 19 equivalence classes. [2025-02-08 14:28:33,514 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 75 of 75 statements. [2025-02-08 14:28:33,514 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-02-08 14:28:33,514 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:34,296 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:34,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:34,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1072122585] [2025-02-08 14:28:34,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1072122585] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:34,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [88437195] [2025-02-08 14:28:34,297 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:34,297 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:34,297 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:34,303 INFO L229 MonitoredProcess]: Starting monitored process 28 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:34,308 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (28)] Waiting until timeout for monitored process [2025-02-08 14:28:34,390 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 75 statements into 19 equivalence classes. [2025-02-08 14:28:34,852 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) and asserted 75 of 75 statements. [2025-02-08 14:28:34,852 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2025-02-08 14:28:34,852 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:34,857 INFO L256 TraceCheckSpWp]: Trace formula consists of 419 conjuncts, 40 conjuncts are in the unsatisfiable core [2025-02-08 14:28:34,858 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:35,465 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:35,465 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:35,921 INFO L134 CoverageAnalysis]: Checked inductivity of 648 backedges. 477 proven. 171 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:35,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [88437195] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:35,922 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:35,922 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38] total 57 [2025-02-08 14:28:35,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718340238] [2025-02-08 14:28:35,922 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:35,950 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:35,951 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2025-02-08 14:28:35,952 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2025-02-08 14:28:35,952 INFO L87 Difference]: Start difference. First operand 116 states and 137 transitions. cyclomatic complexity: 24 Second operand has 59 states, 58 states have (on average 2.2586206896551726) internal successors, (131), 58 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:36,556 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:36,556 INFO L93 Difference]: Finished difference Result 403 states and 482 transitions. [2025-02-08 14:28:36,557 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 403 states and 482 transitions. [2025-02-08 14:28:36,561 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:36,562 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 403 states to 221 states and 263 transitions. [2025-02-08 14:28:36,562 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 202 [2025-02-08 14:28:36,563 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 202 [2025-02-08 14:28:36,563 INFO L73 IsDeterministic]: Start isDeterministic. Operand 221 states and 263 transitions. [2025-02-08 14:28:36,563 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:36,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 221 states and 263 transitions. [2025-02-08 14:28:36,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states and 263 transitions. [2025-02-08 14:28:36,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 122. [2025-02-08 14:28:36,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 122 states, 122 states have (on average 1.180327868852459) internal successors, (144), 121 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:36,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 144 transitions. [2025-02-08 14:28:36,565 INFO L240 hiAutomatonCegarLoop]: Abstraction has 122 states and 144 transitions. [2025-02-08 14:28:36,568 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2025-02-08 14:28:36,568 INFO L432 stractBuchiCegarLoop]: Abstraction has 122 states and 144 transitions. [2025-02-08 14:28:36,568 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-08 14:28:36,568 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 122 states and 144 transitions. [2025-02-08 14:28:36,569 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:36,569 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:36,569 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:36,569 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [19, 19, 18, 18, 1, 1] [2025-02-08 14:28:36,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:36,570 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:36,570 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:36,570 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:36,570 INFO L85 PathProgramCache]: Analyzing trace with hash 1841015359, now seen corresponding path program 36 times [2025-02-08 14:28:36,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:36,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217279137] [2025-02-08 14:28:36,570 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:36,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:36,583 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 76 statements into 19 equivalence classes. [2025-02-08 14:28:36,672 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) and asserted 76 of 76 statements. [2025-02-08 14:28:36,673 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2025-02-08 14:28:36,673 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:36,673 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:36,677 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-02-08 14:28:36,714 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-02-08 14:28:36,714 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:36,714 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:36,720 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:36,720 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:36,720 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 20 times [2025-02-08 14:28:36,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:36,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [866131571] [2025-02-08 14:28:36,720 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:36,720 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:36,722 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:36,765 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:36,765 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:36,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:36,765 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:36,765 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:36,766 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:36,766 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:36,766 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:36,767 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:36,768 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:36,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1043787359, now seen corresponding path program 37 times [2025-02-08 14:28:36,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:36,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345868011] [2025-02-08 14:28:36,768 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:36,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:36,778 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-08 14:28:36,786 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-08 14:28:36,786 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:36,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:37,482 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 477 proven. 245 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:37,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:37,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1345868011] [2025-02-08 14:28:37,483 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1345868011] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:37,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1077883771] [2025-02-08 14:28:37,483 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:37,483 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:37,483 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:37,486 INFO L229 MonitoredProcess]: Starting monitored process 29 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:37,487 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (29)] Waiting until timeout for monitored process [2025-02-08 14:28:37,580 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-02-08 14:28:37,619 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-02-08 14:28:37,619 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:37,620 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:37,622 INFO L256 TraceCheckSpWp]: Trace formula consists of 440 conjuncts, 42 conjuncts are in the unsatisfiable core [2025-02-08 14:28:37,623 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:38,244 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:38,245 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:38,717 INFO L134 CoverageAnalysis]: Checked inductivity of 722 backedges. 532 proven. 190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:38,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1077883771] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:38,718 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:38,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40] total 62 [2025-02-08 14:28:38,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [840343773] [2025-02-08 14:28:38,718 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:38,746 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:38,747 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2025-02-08 14:28:38,748 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=948, Invalid=3084, Unknown=0, NotChecked=0, Total=4032 [2025-02-08 14:28:38,748 INFO L87 Difference]: Start difference. First operand 122 states and 144 transitions. cyclomatic complexity: 25 Second operand has 64 states, 63 states have (on average 2.2857142857142856) internal successors, (144), 63 states have internal predecessors, (144), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:39,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:39,491 INFO L93 Difference]: Finished difference Result 424 states and 507 transitions. [2025-02-08 14:28:39,491 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 424 states and 507 transitions. [2025-02-08 14:28:39,492 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:39,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 424 states to 232 states and 276 transitions. [2025-02-08 14:28:39,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 212 [2025-02-08 14:28:39,493 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 212 [2025-02-08 14:28:39,493 INFO L73 IsDeterministic]: Start isDeterministic. Operand 232 states and 276 transitions. [2025-02-08 14:28:39,493 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:39,493 INFO L218 hiAutomatonCegarLoop]: Abstraction has 232 states and 276 transitions. [2025-02-08 14:28:39,494 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 232 states and 276 transitions. [2025-02-08 14:28:39,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 232 to 128. [2025-02-08 14:28:39,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.1796875) internal successors, (151), 127 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:39,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 151 transitions. [2025-02-08 14:28:39,495 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 151 transitions. [2025-02-08 14:28:39,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2025-02-08 14:28:39,496 INFO L432 stractBuchiCegarLoop]: Abstraction has 128 states and 151 transitions. [2025-02-08 14:28:39,496 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-02-08 14:28:39,496 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 151 transitions. [2025-02-08 14:28:39,496 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:39,497 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:39,497 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:39,497 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [20, 20, 19, 19, 1, 1] [2025-02-08 14:28:39,497 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:39,497 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:39,497 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:39,498 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:39,498 INFO L85 PathProgramCache]: Analyzing trace with hash 634510855, now seen corresponding path program 38 times [2025-02-08 14:28:39,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:39,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185329935] [2025-02-08 14:28:39,498 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:39,498 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:39,508 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 80 statements into 2 equivalence classes. [2025-02-08 14:28:39,546 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 80 of 80 statements. [2025-02-08 14:28:39,548 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:39,548 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:39,548 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:39,553 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-02-08 14:28:39,590 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-02-08 14:28:39,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:39,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:39,595 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:39,596 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:39,596 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 21 times [2025-02-08 14:28:39,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:39,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [313686088] [2025-02-08 14:28:39,596 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:39,596 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:39,598 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:39,599 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:39,599 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:28:39,599 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:39,599 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:39,599 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:39,600 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:39,600 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:39,600 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:39,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:39,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:39,602 INFO L85 PathProgramCache]: Analyzing trace with hash 561834201, now seen corresponding path program 39 times [2025-02-08 14:28:39,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:39,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [139539466] [2025-02-08 14:28:39,602 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:39,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:39,614 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 83 statements into 21 equivalence classes. [2025-02-08 14:28:39,961 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 83 of 83 statements. [2025-02-08 14:28:39,962 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-02-08 14:28:39,962 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:40,786 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 532 proven. 268 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:40,786 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:40,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [139539466] [2025-02-08 14:28:40,787 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [139539466] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:40,787 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [669535316] [2025-02-08 14:28:40,787 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:40,787 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:40,787 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:40,789 INFO L229 MonitoredProcess]: Starting monitored process 30 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:40,790 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (30)] Waiting until timeout for monitored process [2025-02-08 14:28:40,939 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 83 statements into 21 equivalence classes. [2025-02-08 14:28:42,316 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) and asserted 83 of 83 statements. [2025-02-08 14:28:42,316 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2025-02-08 14:28:42,316 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:42,321 INFO L256 TraceCheckSpWp]: Trace formula consists of 461 conjuncts, 44 conjuncts are in the unsatisfiable core [2025-02-08 14:28:42,322 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:43,038 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:43,039 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:43,470 INFO L134 CoverageAnalysis]: Checked inductivity of 800 backedges. 590 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:43,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [669535316] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:43,470 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:43,470 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42] total 65 [2025-02-08 14:28:43,470 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [461024457] [2025-02-08 14:28:43,470 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:43,495 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:43,495 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2025-02-08 14:28:43,496 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1037, Invalid=3385, Unknown=0, NotChecked=0, Total=4422 [2025-02-08 14:28:43,496 INFO L87 Difference]: Start difference. First operand 128 states and 151 transitions. cyclomatic complexity: 26 Second operand has 67 states, 66 states have (on average 2.287878787878788) internal successors, (151), 66 states have internal predecessors, (151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:44,077 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:44,077 INFO L93 Difference]: Finished difference Result 445 states and 532 transitions. [2025-02-08 14:28:44,078 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 445 states and 532 transitions. [2025-02-08 14:28:44,079 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:44,080 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 445 states to 243 states and 289 transitions. [2025-02-08 14:28:44,080 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 222 [2025-02-08 14:28:44,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 222 [2025-02-08 14:28:44,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 243 states and 289 transitions. [2025-02-08 14:28:44,080 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:44,080 INFO L218 hiAutomatonCegarLoop]: Abstraction has 243 states and 289 transitions. [2025-02-08 14:28:44,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states and 289 transitions. [2025-02-08 14:28:44,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 134. [2025-02-08 14:28:44,088 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 134 states, 134 states have (on average 1.1791044776119404) internal successors, (158), 133 states have internal predecessors, (158), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:44,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 158 transitions. [2025-02-08 14:28:44,088 INFO L240 hiAutomatonCegarLoop]: Abstraction has 134 states and 158 transitions. [2025-02-08 14:28:44,089 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2025-02-08 14:28:44,089 INFO L432 stractBuchiCegarLoop]: Abstraction has 134 states and 158 transitions. [2025-02-08 14:28:44,089 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-02-08 14:28:44,089 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 134 states and 158 transitions. [2025-02-08 14:28:44,089 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:44,089 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:44,089 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:44,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [21, 21, 20, 20, 1, 1] [2025-02-08 14:28:44,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:44,090 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:44,090 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:44,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:44,090 INFO L85 PathProgramCache]: Analyzing trace with hash -2116218305, now seen corresponding path program 40 times [2025-02-08 14:28:44,091 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:44,091 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123749662] [2025-02-08 14:28:44,091 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:44,091 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:44,102 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 84 statements into 2 equivalence classes. [2025-02-08 14:28:44,152 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 84 of 84 statements. [2025-02-08 14:28:44,153 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:44,153 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:44,153 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:44,156 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 84 statements into 1 equivalence classes. [2025-02-08 14:28:44,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 84 of 84 statements. [2025-02-08 14:28:44,197 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:44,197 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:44,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:44,203 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:44,203 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 22 times [2025-02-08 14:28:44,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:44,203 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1022287451] [2025-02-08 14:28:44,203 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:44,203 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:44,205 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-08 14:28:44,206 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:44,206 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:44,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:44,206 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:44,206 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:44,207 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:44,207 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:44,207 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:44,208 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:44,209 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:44,209 INFO L85 PathProgramCache]: Analyzing trace with hash 1565436321, now seen corresponding path program 41 times [2025-02-08 14:28:44,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:44,209 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1038929863] [2025-02-08 14:28:44,209 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:44,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:44,219 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 87 statements into 22 equivalence classes. [2025-02-08 14:28:44,250 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 87 of 87 statements. [2025-02-08 14:28:44,250 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-02-08 14:28:44,250 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:45,065 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:45,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:45,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1038929863] [2025-02-08 14:28:45,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1038929863] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:45,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [114679725] [2025-02-08 14:28:45,066 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:45,066 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:45,066 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:45,069 INFO L229 MonitoredProcess]: Starting monitored process 31 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:45,070 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (31)] Waiting until timeout for monitored process [2025-02-08 14:28:45,180 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 87 statements into 22 equivalence classes. [2025-02-08 14:28:45,966 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) and asserted 87 of 87 statements. [2025-02-08 14:28:45,966 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2025-02-08 14:28:45,966 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:45,977 INFO L256 TraceCheckSpWp]: Trace formula consists of 482 conjuncts, 46 conjuncts are in the unsatisfiable core [2025-02-08 14:28:45,978 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:46,703 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:46,703 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:47,299 INFO L134 CoverageAnalysis]: Checked inductivity of 882 backedges. 651 proven. 231 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:47,299 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [114679725] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:47,299 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:47,300 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44] total 66 [2025-02-08 14:28:47,300 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1589319536] [2025-02-08 14:28:47,300 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:47,329 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:47,330 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2025-02-08 14:28:47,331 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1079, Invalid=3477, Unknown=0, NotChecked=0, Total=4556 [2025-02-08 14:28:47,331 INFO L87 Difference]: Start difference. First operand 134 states and 158 transitions. cyclomatic complexity: 27 Second operand has 68 states, 67 states have (on average 2.2686567164179103) internal successors, (152), 67 states have internal predecessors, (152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:48,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:48,253 INFO L93 Difference]: Finished difference Result 466 states and 557 transitions. [2025-02-08 14:28:48,253 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 466 states and 557 transitions. [2025-02-08 14:28:48,254 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:48,255 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 466 states to 254 states and 302 transitions. [2025-02-08 14:28:48,255 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 232 [2025-02-08 14:28:48,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 232 [2025-02-08 14:28:48,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 254 states and 302 transitions. [2025-02-08 14:28:48,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:48,255 INFO L218 hiAutomatonCegarLoop]: Abstraction has 254 states and 302 transitions. [2025-02-08 14:28:48,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states and 302 transitions. [2025-02-08 14:28:48,257 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 140. [2025-02-08 14:28:48,257 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 140 states, 140 states have (on average 1.1785714285714286) internal successors, (165), 139 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:48,258 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 165 transitions. [2025-02-08 14:28:48,258 INFO L240 hiAutomatonCegarLoop]: Abstraction has 140 states and 165 transitions. [2025-02-08 14:28:48,258 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2025-02-08 14:28:48,258 INFO L432 stractBuchiCegarLoop]: Abstraction has 140 states and 165 transitions. [2025-02-08 14:28:48,259 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-02-08 14:28:48,259 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 140 states and 165 transitions. [2025-02-08 14:28:48,259 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:48,259 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:48,259 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:48,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [22, 22, 21, 21, 1, 1] [2025-02-08 14:28:48,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:48,260 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:48,260 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:48,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:48,260 INFO L85 PathProgramCache]: Analyzing trace with hash -720392185, now seen corresponding path program 42 times [2025-02-08 14:28:48,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:48,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1983611837] [2025-02-08 14:28:48,260 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:48,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:48,270 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 88 statements into 22 equivalence classes. [2025-02-08 14:28:48,445 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) and asserted 88 of 88 statements. [2025-02-08 14:28:48,445 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2025-02-08 14:28:48,445 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:48,445 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:48,450 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 88 statements into 1 equivalence classes. [2025-02-08 14:28:48,489 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 88 of 88 statements. [2025-02-08 14:28:48,489 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:48,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:48,495 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:48,496 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:48,496 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 23 times [2025-02-08 14:28:48,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:48,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [249191581] [2025-02-08 14:28:48,496 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:48,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:48,498 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:48,499 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:48,499 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:28:48,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:48,499 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:48,499 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:48,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:48,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:48,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:48,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:48,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:48,502 INFO L85 PathProgramCache]: Analyzing trace with hash 748017369, now seen corresponding path program 43 times [2025-02-08 14:28:48,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:48,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1256178169] [2025-02-08 14:28:48,502 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:48,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:48,512 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-02-08 14:28:48,520 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-02-08 14:28:48,520 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:48,520 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:49,433 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 651 proven. 317 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:49,434 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:49,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1256178169] [2025-02-08 14:28:49,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1256178169] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:49,434 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2009787571] [2025-02-08 14:28:49,434 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:49,434 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:49,434 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:49,439 INFO L229 MonitoredProcess]: Starting monitored process 32 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:49,441 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (32)] Waiting until timeout for monitored process [2025-02-08 14:28:49,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-02-08 14:28:49,602 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-02-08 14:28:49,602 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:49,602 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:49,604 INFO L256 TraceCheckSpWp]: Trace formula consists of 503 conjuncts, 48 conjuncts are in the unsatisfiable core [2025-02-08 14:28:49,606 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:50,508 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:50,508 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:51,159 INFO L134 CoverageAnalysis]: Checked inductivity of 968 backedges. 715 proven. 253 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:51,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2009787571] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:51,159 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:51,160 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46] total 71 [2025-02-08 14:28:51,160 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1374108674] [2025-02-08 14:28:51,160 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:51,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:51,190 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2025-02-08 14:28:51,191 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1227, Invalid=4029, Unknown=0, NotChecked=0, Total=5256 [2025-02-08 14:28:51,191 INFO L87 Difference]: Start difference. First operand 140 states and 165 transitions. cyclomatic complexity: 28 Second operand has 73 states, 72 states have (on average 2.2916666666666665) internal successors, (165), 72 states have internal predecessors, (165), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:51,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:51,942 INFO L93 Difference]: Finished difference Result 487 states and 582 transitions. [2025-02-08 14:28:51,942 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 487 states and 582 transitions. [2025-02-08 14:28:51,944 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:51,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 487 states to 265 states and 315 transitions. [2025-02-08 14:28:51,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 242 [2025-02-08 14:28:51,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 242 [2025-02-08 14:28:51,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 265 states and 315 transitions. [2025-02-08 14:28:51,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:51,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 265 states and 315 transitions. [2025-02-08 14:28:51,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states and 315 transitions. [2025-02-08 14:28:51,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 146. [2025-02-08 14:28:51,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 146 states, 146 states have (on average 1.178082191780822) internal successors, (172), 145 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:51,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 172 transitions. [2025-02-08 14:28:51,947 INFO L240 hiAutomatonCegarLoop]: Abstraction has 146 states and 172 transitions. [2025-02-08 14:28:51,948 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2025-02-08 14:28:51,948 INFO L432 stractBuchiCegarLoop]: Abstraction has 146 states and 172 transitions. [2025-02-08 14:28:51,948 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-02-08 14:28:51,949 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 146 states and 172 transitions. [2025-02-08 14:28:51,949 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:51,949 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:51,949 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:51,950 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [23, 23, 22, 22, 1, 1] [2025-02-08 14:28:51,950 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:51,950 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:51,950 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:51,950 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:51,950 INFO L85 PathProgramCache]: Analyzing trace with hash 906050111, now seen corresponding path program 44 times [2025-02-08 14:28:51,950 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:51,950 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911094777] [2025-02-08 14:28:51,951 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:28:51,951 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:51,962 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 92 statements into 2 equivalence classes. [2025-02-08 14:28:52,005 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 92 of 92 statements. [2025-02-08 14:28:52,005 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:28:52,005 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:52,006 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:52,010 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-02-08 14:28:52,043 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-02-08 14:28:52,043 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:52,043 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:52,053 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:52,054 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:52,054 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 24 times [2025-02-08 14:28:52,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:52,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329011848] [2025-02-08 14:28:52,054 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:28:52,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:52,057 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:52,057 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:52,057 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:28:52,058 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:52,058 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:52,058 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:52,058 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:52,058 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:52,058 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:52,060 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:52,060 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:52,061 INFO L85 PathProgramCache]: Analyzing trace with hash -1730575967, now seen corresponding path program 45 times [2025-02-08 14:28:52,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:52,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019571564] [2025-02-08 14:28:52,061 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:52,061 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:52,072 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 95 statements into 24 equivalence classes. [2025-02-08 14:28:52,382 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:28:52,383 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-02-08 14:28:52,383 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:53,417 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 715 proven. 343 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:53,418 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:53,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019571564] [2025-02-08 14:28:53,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019571564] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:53,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [799898296] [2025-02-08 14:28:53,418 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:28:53,418 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:53,418 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:53,421 INFO L229 MonitoredProcess]: Starting monitored process 33 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:53,423 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (33)] Waiting until timeout for monitored process [2025-02-08 14:28:53,549 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 95 statements into 24 equivalence classes. [2025-02-08 14:28:54,942 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:28:54,942 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2025-02-08 14:28:54,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:54,947 INFO L256 TraceCheckSpWp]: Trace formula consists of 524 conjuncts, 50 conjuncts are in the unsatisfiable core [2025-02-08 14:28:54,949 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:28:55,755 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:55,756 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:28:56,377 INFO L134 CoverageAnalysis]: Checked inductivity of 1058 backedges. 782 proven. 276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:56,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [799898296] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:28:56,377 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:28:56,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48] total 74 [2025-02-08 14:28:56,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353489364] [2025-02-08 14:28:56,378 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:28:56,404 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:28:56,405 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2025-02-08 14:28:56,406 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1328, Invalid=4372, Unknown=0, NotChecked=0, Total=5700 [2025-02-08 14:28:56,406 INFO L87 Difference]: Start difference. First operand 146 states and 172 transitions. cyclomatic complexity: 29 Second operand has 76 states, 75 states have (on average 2.2933333333333334) internal successors, (172), 75 states have internal predecessors, (172), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:57,209 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:28:57,209 INFO L93 Difference]: Finished difference Result 508 states and 607 transitions. [2025-02-08 14:28:57,209 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 508 states and 607 transitions. [2025-02-08 14:28:57,211 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:57,212 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 508 states to 276 states and 328 transitions. [2025-02-08 14:28:57,212 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 252 [2025-02-08 14:28:57,212 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 252 [2025-02-08 14:28:57,212 INFO L73 IsDeterministic]: Start isDeterministic. Operand 276 states and 328 transitions. [2025-02-08 14:28:57,212 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:28:57,212 INFO L218 hiAutomatonCegarLoop]: Abstraction has 276 states and 328 transitions. [2025-02-08 14:28:57,215 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states and 328 transitions. [2025-02-08 14:28:57,217 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 152. [2025-02-08 14:28:57,217 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152 states, 152 states have (on average 1.1776315789473684) internal successors, (179), 151 states have internal predecessors, (179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:28:57,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152 states to 152 states and 179 transitions. [2025-02-08 14:28:57,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 152 states and 179 transitions. [2025-02-08 14:28:57,222 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2025-02-08 14:28:57,222 INFO L432 stractBuchiCegarLoop]: Abstraction has 152 states and 179 transitions. [2025-02-08 14:28:57,222 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-02-08 14:28:57,222 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152 states and 179 transitions. [2025-02-08 14:28:57,223 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:28:57,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:28:57,226 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:28:57,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [24, 24, 23, 23, 1, 1] [2025-02-08 14:28:57,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:28:57,227 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:57,230 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:28:57,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:57,230 INFO L85 PathProgramCache]: Analyzing trace with hash 1836630535, now seen corresponding path program 46 times [2025-02-08 14:28:57,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:57,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1361908084] [2025-02-08 14:28:57,230 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:28:57,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:57,250 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 96 statements into 2 equivalence classes. [2025-02-08 14:28:57,323 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:28:57,323 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:28:57,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:57,323 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:57,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:28:57,378 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:28:57,378 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:57,378 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:57,386 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:57,387 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:57,387 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 25 times [2025-02-08 14:28:57,387 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:57,387 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1644673928] [2025-02-08 14:28:57,387 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:28:57,388 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:57,390 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:57,390 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:57,390 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:57,390 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:57,391 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:28:57,391 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:28:57,391 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:28:57,391 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:28:57,391 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:28:57,393 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:28:57,393 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:28:57,393 INFO L85 PathProgramCache]: Analyzing trace with hash 1471907033, now seen corresponding path program 47 times [2025-02-08 14:28:57,393 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:28:57,393 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1170988654] [2025-02-08 14:28:57,393 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:57,393 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:28:57,409 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 99 statements into 25 equivalence classes. [2025-02-08 14:28:57,449 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 99 of 99 statements. [2025-02-08 14:28:57,449 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-02-08 14:28:57,449 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:58,394 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:28:58,394 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:28:58,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1170988654] [2025-02-08 14:28:58,394 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1170988654] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:28:58,394 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [78542443] [2025-02-08 14:28:58,395 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:28:58,395 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:28:58,395 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:28:58,398 INFO L229 MonitoredProcess]: Starting monitored process 34 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:28:58,401 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (34)] Waiting until timeout for monitored process [2025-02-08 14:28:58,557 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 99 statements into 25 equivalence classes. [2025-02-08 14:28:59,356 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) and asserted 99 of 99 statements. [2025-02-08 14:28:59,356 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2025-02-08 14:28:59,356 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:28:59,361 INFO L256 TraceCheckSpWp]: Trace formula consists of 545 conjuncts, 52 conjuncts are in the unsatisfiable core [2025-02-08 14:28:59,363 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:29:00,349 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:00,349 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:29:01,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1152 backedges. 852 proven. 300 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:01,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [78542443] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:29:01,124 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:29:01,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50] total 75 [2025-02-08 14:29:01,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068995129] [2025-02-08 14:29:01,124 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:29:01,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:29:01,156 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2025-02-08 14:29:01,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1376, Invalid=4476, Unknown=0, NotChecked=0, Total=5852 [2025-02-08 14:29:01,158 INFO L87 Difference]: Start difference. First operand 152 states and 179 transitions. cyclomatic complexity: 30 Second operand has 77 states, 76 states have (on average 2.276315789473684) internal successors, (173), 76 states have internal predecessors, (173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:01,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:29:01,987 INFO L93 Difference]: Finished difference Result 529 states and 632 transitions. [2025-02-08 14:29:01,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 529 states and 632 transitions. [2025-02-08 14:29:01,989 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:01,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 529 states to 287 states and 341 transitions. [2025-02-08 14:29:01,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 262 [2025-02-08 14:29:01,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 262 [2025-02-08 14:29:01,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 287 states and 341 transitions. [2025-02-08 14:29:01,990 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:29:01,990 INFO L218 hiAutomatonCegarLoop]: Abstraction has 287 states and 341 transitions. [2025-02-08 14:29:01,990 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states and 341 transitions. [2025-02-08 14:29:01,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 158. [2025-02-08 14:29:01,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 158 states, 158 states have (on average 1.1772151898734178) internal successors, (186), 157 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:01,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 158 states to 158 states and 186 transitions. [2025-02-08 14:29:01,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 158 states and 186 transitions. [2025-02-08 14:29:01,996 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2025-02-08 14:29:01,996 INFO L432 stractBuchiCegarLoop]: Abstraction has 158 states and 186 transitions. [2025-02-08 14:29:01,996 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-02-08 14:29:01,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 158 states and 186 transitions. [2025-02-08 14:29:01,997 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:01,997 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:29:01,997 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:29:01,998 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [25, 25, 24, 24, 1, 1] [2025-02-08 14:29:01,998 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:29:01,998 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:01,998 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:01,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:01,999 INFO L85 PathProgramCache]: Analyzing trace with hash 1347953215, now seen corresponding path program 48 times [2025-02-08 14:29:01,999 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:01,999 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213409814] [2025-02-08 14:29:01,999 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:29:01,999 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:02,015 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 100 statements into 25 equivalence classes. [2025-02-08 14:29:02,275 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) and asserted 100 of 100 statements. [2025-02-08 14:29:02,275 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2025-02-08 14:29:02,275 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:02,275 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:02,280 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 100 statements into 1 equivalence classes. [2025-02-08 14:29:02,338 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 100 of 100 statements. [2025-02-08 14:29:02,338 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:02,338 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:02,345 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:02,345 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:02,346 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 26 times [2025-02-08 14:29:02,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:02,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [376042911] [2025-02-08 14:29:02,346 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:29:02,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:02,348 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:02,349 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:02,349 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:29:02,349 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:02,349 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:02,349 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:02,350 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:02,350 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:02,350 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:02,351 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:02,352 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:02,352 INFO L85 PathProgramCache]: Analyzing trace with hash -1069966943, now seen corresponding path program 49 times [2025-02-08 14:29:02,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:02,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1518750633] [2025-02-08 14:29:02,352 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:29:02,352 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:02,373 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 103 statements into 1 equivalence classes. [2025-02-08 14:29:02,383 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 103 of 103 statements. [2025-02-08 14:29:02,383 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:02,383 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:03,413 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 852 proven. 398 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:03,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:29:03,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1518750633] [2025-02-08 14:29:03,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1518750633] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:29:03,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1701941671] [2025-02-08 14:29:03,414 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:29:03,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:29:03,414 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:29:03,416 INFO L229 MonitoredProcess]: Starting monitored process 35 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:29:03,418 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (35)] Waiting until timeout for monitored process [2025-02-08 14:29:03,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 103 statements into 1 equivalence classes. [2025-02-08 14:29:03,609 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 103 of 103 statements. [2025-02-08 14:29:03,609 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:03,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:03,617 INFO L256 TraceCheckSpWp]: Trace formula consists of 566 conjuncts, 54 conjuncts are in the unsatisfiable core [2025-02-08 14:29:03,619 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:29:04,524 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:04,524 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:29:05,311 INFO L134 CoverageAnalysis]: Checked inductivity of 1250 backedges. 925 proven. 325 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:05,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1701941671] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:29:05,311 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:29:05,311 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52] total 80 [2025-02-08 14:29:05,311 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761519458] [2025-02-08 14:29:05,311 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:29:05,342 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:29:05,343 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2025-02-08 14:29:05,344 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1542, Invalid=5100, Unknown=0, NotChecked=0, Total=6642 [2025-02-08 14:29:05,344 INFO L87 Difference]: Start difference. First operand 158 states and 186 transitions. cyclomatic complexity: 31 Second operand has 82 states, 81 states have (on average 2.2962962962962963) internal successors, (186), 81 states have internal predecessors, (186), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:06,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:29:06,408 INFO L93 Difference]: Finished difference Result 550 states and 657 transitions. [2025-02-08 14:29:06,409 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 550 states and 657 transitions. [2025-02-08 14:29:06,410 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:06,411 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 550 states to 298 states and 354 transitions. [2025-02-08 14:29:06,411 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 272 [2025-02-08 14:29:06,411 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 272 [2025-02-08 14:29:06,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 298 states and 354 transitions. [2025-02-08 14:29:06,411 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:29:06,412 INFO L218 hiAutomatonCegarLoop]: Abstraction has 298 states and 354 transitions. [2025-02-08 14:29:06,412 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states and 354 transitions. [2025-02-08 14:29:06,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 164. [2025-02-08 14:29:06,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164 states, 164 states have (on average 1.1768292682926829) internal successors, (193), 163 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:06,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 193 transitions. [2025-02-08 14:29:06,414 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164 states and 193 transitions. [2025-02-08 14:29:06,414 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2025-02-08 14:29:06,415 INFO L432 stractBuchiCegarLoop]: Abstraction has 164 states and 193 transitions. [2025-02-08 14:29:06,415 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-02-08 14:29:06,415 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164 states and 193 transitions. [2025-02-08 14:29:06,415 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:06,415 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:29:06,415 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:29:06,415 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [26, 26, 25, 25, 1, 1] [2025-02-08 14:29:06,415 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:29:06,416 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:06,416 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:06,416 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:06,416 INFO L85 PathProgramCache]: Analyzing trace with hash -1260579833, now seen corresponding path program 50 times [2025-02-08 14:29:06,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:06,417 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1148620224] [2025-02-08 14:29:06,417 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:29:06,417 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:06,429 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 104 statements into 2 equivalence classes. [2025-02-08 14:29:06,480 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 104 of 104 statements. [2025-02-08 14:29:06,480 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:29:06,480 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:06,480 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:06,484 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 104 statements into 1 equivalence classes. [2025-02-08 14:29:06,570 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 104 of 104 statements. [2025-02-08 14:29:06,571 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:06,571 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:06,577 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:06,577 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:06,577 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 27 times [2025-02-08 14:29:06,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:06,578 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2090601659] [2025-02-08 14:29:06,578 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:29:06,578 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:06,581 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:06,581 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:06,581 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:29:06,581 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:06,581 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:06,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:06,582 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:06,582 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:06,582 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:06,584 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:06,584 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:06,584 INFO L85 PathProgramCache]: Analyzing trace with hash 1260253913, now seen corresponding path program 51 times [2025-02-08 14:29:06,584 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:06,584 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775311712] [2025-02-08 14:29:06,584 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:29:06,585 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:06,597 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 107 statements into 27 equivalence classes. [2025-02-08 14:29:06,994 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 107 of 107 statements. [2025-02-08 14:29:06,994 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-02-08 14:29:06,994 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:08,315 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 925 proven. 427 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:08,315 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:29:08,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775311712] [2025-02-08 14:29:08,316 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775311712] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:29:08,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1879516539] [2025-02-08 14:29:08,316 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:29:08,316 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:29:08,316 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:29:08,318 INFO L229 MonitoredProcess]: Starting monitored process 36 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:29:08,320 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (36)] Waiting until timeout for monitored process [2025-02-08 14:29:08,457 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 107 statements into 27 equivalence classes. [2025-02-08 14:29:12,119 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) and asserted 107 of 107 statements. [2025-02-08 14:29:12,119 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2025-02-08 14:29:12,119 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:12,127 INFO L256 TraceCheckSpWp]: Trace formula consists of 587 conjuncts, 56 conjuncts are in the unsatisfiable core [2025-02-08 14:29:12,129 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:29:13,253 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:13,253 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:29:13,986 INFO L134 CoverageAnalysis]: Checked inductivity of 1352 backedges. 1001 proven. 351 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:13,987 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1879516539] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:29:13,987 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:29:13,987 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54] total 83 [2025-02-08 14:29:13,987 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [795129405] [2025-02-08 14:29:13,987 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:29:14,014 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:29:14,015 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 85 interpolants. [2025-02-08 14:29:14,015 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1655, Invalid=5485, Unknown=0, NotChecked=0, Total=7140 [2025-02-08 14:29:14,016 INFO L87 Difference]: Start difference. First operand 164 states and 193 transitions. cyclomatic complexity: 32 Second operand has 85 states, 84 states have (on average 2.2976190476190474) internal successors, (193), 84 states have internal predecessors, (193), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:14,918 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:29:14,919 INFO L93 Difference]: Finished difference Result 571 states and 682 transitions. [2025-02-08 14:29:14,919 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 571 states and 682 transitions. [2025-02-08 14:29:14,921 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:14,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 571 states to 309 states and 367 transitions. [2025-02-08 14:29:14,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 282 [2025-02-08 14:29:14,923 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 282 [2025-02-08 14:29:14,923 INFO L73 IsDeterministic]: Start isDeterministic. Operand 309 states and 367 transitions. [2025-02-08 14:29:14,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:29:14,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 309 states and 367 transitions. [2025-02-08 14:29:14,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states and 367 transitions. [2025-02-08 14:29:14,929 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 170. [2025-02-08 14:29:14,934 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 170 states, 170 states have (on average 1.1764705882352942) internal successors, (200), 169 states have internal predecessors, (200), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:14,934 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 170 states to 170 states and 200 transitions. [2025-02-08 14:29:14,934 INFO L240 hiAutomatonCegarLoop]: Abstraction has 170 states and 200 transitions. [2025-02-08 14:29:14,938 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2025-02-08 14:29:14,938 INFO L432 stractBuchiCegarLoop]: Abstraction has 170 states and 200 transitions. [2025-02-08 14:29:14,938 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-02-08 14:29:14,938 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 170 states and 200 transitions. [2025-02-08 14:29:14,938 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:14,938 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:29:14,938 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:29:14,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [27, 27, 26, 26, 1, 1] [2025-02-08 14:29:14,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:29:14,939 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:14,943 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:14,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:14,943 INFO L85 PathProgramCache]: Analyzing trace with hash -216937921, now seen corresponding path program 52 times [2025-02-08 14:29:14,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:14,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1711370839] [2025-02-08 14:29:14,943 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:29:14,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:14,959 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 108 statements into 2 equivalence classes. [2025-02-08 14:29:15,037 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 108 of 108 statements. [2025-02-08 14:29:15,037 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:29:15,038 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:15,038 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:15,042 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 108 statements into 1 equivalence classes. [2025-02-08 14:29:15,106 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 108 of 108 statements. [2025-02-08 14:29:15,106 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:15,107 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:15,113 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:15,114 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:15,114 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 28 times [2025-02-08 14:29:15,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:15,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [677970166] [2025-02-08 14:29:15,114 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:29:15,114 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:15,117 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 3 statements into 2 equivalence classes. [2025-02-08 14:29:15,118 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:15,118 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:29:15,118 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:15,118 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:15,118 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:15,118 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:15,118 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:15,119 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:15,120 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:15,120 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:15,120 INFO L85 PathProgramCache]: Analyzing trace with hash 1128198561, now seen corresponding path program 53 times [2025-02-08 14:29:15,120 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:15,120 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1226271784] [2025-02-08 14:29:15,120 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:29:15,120 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:15,133 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 111 statements into 28 equivalence classes. [2025-02-08 14:29:15,211 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 111 of 111 statements. [2025-02-08 14:29:15,211 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-02-08 14:29:15,211 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:16,508 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:16,508 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:29:16,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1226271784] [2025-02-08 14:29:16,509 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1226271784] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:29:16,509 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1984585226] [2025-02-08 14:29:16,509 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:29:16,509 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:29:16,509 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:29:16,512 INFO L229 MonitoredProcess]: Starting monitored process 37 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:29:16,513 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (37)] Waiting until timeout for monitored process [2025-02-08 14:29:16,658 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 111 statements into 28 equivalence classes. [2025-02-08 14:29:19,169 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) and asserted 111 of 111 statements. [2025-02-08 14:29:19,169 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2025-02-08 14:29:19,169 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:19,182 INFO L256 TraceCheckSpWp]: Trace formula consists of 608 conjuncts, 58 conjuncts are in the unsatisfiable core [2025-02-08 14:29:19,184 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:29:20,395 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:20,395 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:29:21,221 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 1080 proven. 378 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:21,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1984585226] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:29:21,221 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:29:21,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56] total 84 [2025-02-08 14:29:21,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784738481] [2025-02-08 14:29:21,222 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:29:21,249 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:29:21,249 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 86 interpolants. [2025-02-08 14:29:21,250 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1709, Invalid=5601, Unknown=0, NotChecked=0, Total=7310 [2025-02-08 14:29:21,250 INFO L87 Difference]: Start difference. First operand 170 states and 200 transitions. cyclomatic complexity: 33 Second operand has 86 states, 85 states have (on average 2.2823529411764705) internal successors, (194), 85 states have internal predecessors, (194), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:22,160 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:29:22,160 INFO L93 Difference]: Finished difference Result 592 states and 707 transitions. [2025-02-08 14:29:22,160 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 707 transitions. [2025-02-08 14:29:22,162 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:22,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 320 states and 380 transitions. [2025-02-08 14:29:22,163 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 292 [2025-02-08 14:29:22,164 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 292 [2025-02-08 14:29:22,164 INFO L73 IsDeterministic]: Start isDeterministic. Operand 320 states and 380 transitions. [2025-02-08 14:29:22,164 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:29:22,164 INFO L218 hiAutomatonCegarLoop]: Abstraction has 320 states and 380 transitions. [2025-02-08 14:29:22,164 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 320 states and 380 transitions. [2025-02-08 14:29:22,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 320 to 176. [2025-02-08 14:29:22,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 176 states, 176 states have (on average 1.1761363636363635) internal successors, (207), 175 states have internal predecessors, (207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:22,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 207 transitions. [2025-02-08 14:29:22,167 INFO L240 hiAutomatonCegarLoop]: Abstraction has 176 states and 207 transitions. [2025-02-08 14:29:22,168 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2025-02-08 14:29:22,168 INFO L432 stractBuchiCegarLoop]: Abstraction has 176 states and 207 transitions. [2025-02-08 14:29:22,168 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-02-08 14:29:22,169 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 176 states and 207 transitions. [2025-02-08 14:29:22,169 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:22,169 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:29:22,169 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:29:22,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [28, 28, 27, 27, 1, 1] [2025-02-08 14:29:22,170 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:29:22,170 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:22,171 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:22,171 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:22,171 INFO L85 PathProgramCache]: Analyzing trace with hash -1794333177, now seen corresponding path program 54 times [2025-02-08 14:29:22,171 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:22,171 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325292537] [2025-02-08 14:29:22,171 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:29:22,171 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:22,191 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 112 statements into 28 equivalence classes. [2025-02-08 14:29:22,641 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) and asserted 112 of 112 statements. [2025-02-08 14:29:22,641 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2025-02-08 14:29:22,641 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:22,641 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:22,649 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 112 statements into 1 equivalence classes. [2025-02-08 14:29:22,730 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 112 of 112 statements. [2025-02-08 14:29:22,731 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:22,731 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:22,746 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:22,746 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:22,747 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 29 times [2025-02-08 14:29:22,747 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:22,747 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [212638487] [2025-02-08 14:29:22,747 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:29:22,747 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:22,750 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:22,754 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:22,754 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:29:22,754 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:22,754 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:22,755 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:22,755 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:22,755 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:22,755 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:22,757 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:22,761 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:22,761 INFO L85 PathProgramCache]: Analyzing trace with hash 183312601, now seen corresponding path program 55 times [2025-02-08 14:29:22,761 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:22,761 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [92424878] [2025-02-08 14:29:22,761 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:29:22,761 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:22,793 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 115 statements into 1 equivalence classes. [2025-02-08 14:29:22,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 115 of 115 statements. [2025-02-08 14:29:22,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:22,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:24,046 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1080 proven. 488 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:24,047 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:29:24,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [92424878] [2025-02-08 14:29:24,047 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [92424878] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:29:24,047 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1532076312] [2025-02-08 14:29:24,047 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:29:24,047 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:29:24,048 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:29:24,050 INFO L229 MonitoredProcess]: Starting monitored process 38 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:29:24,053 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (38)] Waiting until timeout for monitored process [2025-02-08 14:29:24,204 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 115 statements into 1 equivalence classes. [2025-02-08 14:29:24,258 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 115 of 115 statements. [2025-02-08 14:29:24,258 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:24,258 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:24,261 INFO L256 TraceCheckSpWp]: Trace formula consists of 629 conjuncts, 60 conjuncts are in the unsatisfiable core [2025-02-08 14:29:24,263 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-02-08 14:29:25,282 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:25,282 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-02-08 14:29:26,128 INFO L134 CoverageAnalysis]: Checked inductivity of 1568 backedges. 1162 proven. 406 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:26,128 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1532076312] provided 0 perfect and 2 imperfect interpolant sequences [2025-02-08 14:29:26,128 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-02-08 14:29:26,128 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58] total 89 [2025-02-08 14:29:26,128 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [50520788] [2025-02-08 14:29:26,128 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-02-08 14:29:26,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:29:26,157 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 91 interpolants. [2025-02-08 14:29:26,158 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1893, Invalid=6297, Unknown=0, NotChecked=0, Total=8190 [2025-02-08 14:29:26,158 INFO L87 Difference]: Start difference. First operand 176 states and 207 transitions. cyclomatic complexity: 34 Second operand has 91 states, 90 states have (on average 2.3) internal successors, (207), 90 states have internal predecessors, (207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:27,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:29:27,224 INFO L93 Difference]: Finished difference Result 613 states and 732 transitions. [2025-02-08 14:29:27,224 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 613 states and 732 transitions. [2025-02-08 14:29:27,226 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:27,227 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 613 states to 331 states and 393 transitions. [2025-02-08 14:29:27,227 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 302 [2025-02-08 14:29:27,227 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 302 [2025-02-08 14:29:27,227 INFO L73 IsDeterministic]: Start isDeterministic. Operand 331 states and 393 transitions. [2025-02-08 14:29:27,228 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:29:27,228 INFO L218 hiAutomatonCegarLoop]: Abstraction has 331 states and 393 transitions. [2025-02-08 14:29:27,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states and 393 transitions. [2025-02-08 14:29:27,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 182. [2025-02-08 14:29:27,230 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 182 states, 182 states have (on average 1.1758241758241759) internal successors, (214), 181 states have internal predecessors, (214), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:29:27,230 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 214 transitions. [2025-02-08 14:29:27,230 INFO L240 hiAutomatonCegarLoop]: Abstraction has 182 states and 214 transitions. [2025-02-08 14:29:27,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2025-02-08 14:29:27,232 INFO L432 stractBuchiCegarLoop]: Abstraction has 182 states and 214 transitions. [2025-02-08 14:29:27,232 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-02-08 14:29:27,232 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 182 states and 214 transitions. [2025-02-08 14:29:27,232 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 10 [2025-02-08 14:29:27,233 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:29:27,233 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:29:27,233 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [29, 29, 28, 28, 1, 1] [2025-02-08 14:29:27,233 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-02-08 14:29:27,233 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(18, 2);assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet1#1, main_#t~nondet2#1, main_#t~post3#1, main_#t~mem4#1, main_#t~mem5#1, main_#t~post6#1, main_#t~mem7#1, main_#t~mem8#1, main_#t~post9#1, main_~#array~0#1.base, main_~#array~0#1.offset, main_~i~0#1, main_~num~0#1;call main_~#array~0#1.base, main_~#array~0#1.offset := #Ultimate.allocOnStack(400000);havoc main_~i~0#1;havoc main_#t~nondet1#1;main_~num~0#1 := main_#t~nondet1#1;havoc main_#t~nondet1#1;main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume main_~i~0#1 < main_~num~0#1;havoc main_#t~nondet2#1;call write~int#1(main_#t~nondet2#1, main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet2#1;main_#t~post3#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post3#1;havoc main_#t~post3#1;" "assume !(main_~i~0#1 < main_~num~0#1);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:27,233 INFO L754 eck$LassoCheckResult]: Loop: "assume !(0 == (if main_#t~mem4#1 < 0 && 0 != main_#t~mem4#1 % 2 then main_#t~mem4#1 % 2 - 2 else main_#t~mem4#1 % 2));havoc main_#t~mem4#1;" "main_#t~post6#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post6#1;havoc main_#t~post6#1;" "assume main_~i~0#1 < main_~num~0#1;call main_#t~mem4#1 := read~int#1(main_~#array~0#1.base, main_~#array~0#1.offset + 4 * main_~i~0#1, 4);" [2025-02-08 14:29:27,234 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:27,234 INFO L85 PathProgramCache]: Analyzing trace with hash -1671548353, now seen corresponding path program 56 times [2025-02-08 14:29:27,234 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:27,234 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435355853] [2025-02-08 14:29:27,234 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:29:27,234 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:27,251 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 116 statements into 2 equivalence classes. [2025-02-08 14:29:27,322 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 116 of 116 statements. [2025-02-08 14:29:27,322 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-02-08 14:29:27,322 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:27,322 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:27,328 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 116 statements into 1 equivalence classes. [2025-02-08 14:29:27,430 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 116 of 116 statements. [2025-02-08 14:29:27,431 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:27,431 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:27,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:27,439 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:27,439 INFO L85 PathProgramCache]: Analyzing trace with hash 52383, now seen corresponding path program 30 times [2025-02-08 14:29:27,439 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:27,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600411683] [2025-02-08 14:29:27,440 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:29:27,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:27,446 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:27,450 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:27,450 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:29:27,450 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:27,450 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:29:27,450 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-02-08 14:29:27,451 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-02-08 14:29:27,451 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:29:27,451 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:29:27,452 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:29:27,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:29:27,453 INFO L85 PathProgramCache]: Analyzing trace with hash -1246131807, now seen corresponding path program 57 times [2025-02-08 14:29:27,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:29:27,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672420538] [2025-02-08 14:29:27,453 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:29:27,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:29:27,465 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 119 statements into 30 equivalence classes. [2025-02-08 14:29:27,991 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) and asserted 119 of 119 statements. [2025-02-08 14:29:27,992 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2025-02-08 14:29:27,992 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:29:29,271 INFO L134 CoverageAnalysis]: Checked inductivity of 1682 backedges. 1162 proven. 520 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:29:29,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:29:29,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1672420538] [2025-02-08 14:29:29,272 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1672420538] provided 0 perfect and 1 imperfect interpolant sequences [2025-02-08 14:29:29,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1701439555] [2025-02-08 14:29:29,272 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:29:29,272 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-02-08 14:29:29,272 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:29:29,274 INFO L229 MonitoredProcess]: Starting monitored process 39 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-02-08 14:29:29,275 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (39)] Waiting until timeout for monitored process [2025-02-08 14:29:29,444 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 119 statements into 30 equivalence classes.