./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test8-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 48c9605d Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test8-2.i -s /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash fe37ed55d149c65fede95413b0b499314c3ede2b9eb9a49f03115ea64cafc68c --- Real Ultimate output --- This is Ultimate 0.3.0-?-48c9605-m [2025-02-08 14:58:00,977 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-02-08 14:58:01,049 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-02-08 14:58:01,054 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-02-08 14:58:01,054 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-02-08 14:58:01,054 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-02-08 14:58:01,083 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-02-08 14:58:01,085 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-02-08 14:58:01,085 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-02-08 14:58:01,085 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-02-08 14:58:01,085 INFO L153 SettingsManager]: * Use memory slicer=true [2025-02-08 14:58:01,086 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-02-08 14:58:01,086 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-02-08 14:58:01,086 INFO L153 SettingsManager]: * Use SBE=true [2025-02-08 14:58:01,086 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-02-08 14:58:01,086 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Use old map elimination=false [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-02-08 14:58:01,087 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * sizeof long=4 [2025-02-08 14:58:01,087 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * sizeof long double=12 [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-02-08 14:58:01,088 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-02-08 14:58:01,089 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-02-08 14:58:01,089 INFO L153 SettingsManager]: * Use constant arrays=true [2025-02-08 14:58:01,089 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-02-08 14:58:01,089 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-02-08 14:58:01,089 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-02-08 14:58:01,089 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-02-08 14:58:01,090 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-02-08 14:58:01,090 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> fe37ed55d149c65fede95413b0b499314c3ede2b9eb9a49f03115ea64cafc68c [2025-02-08 14:58:01,369 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-02-08 14:58:01,380 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-02-08 14:58:01,382 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-02-08 14:58:01,384 INFO L270 PluginConnector]: Initializing CDTParser... [2025-02-08 14:58:01,384 INFO L274 PluginConnector]: CDTParser initialized [2025-02-08 14:58:01,385 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_BER_test8-2.i [2025-02-08 14:58:02,707 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/49738f3c6/929bfc73d0094776ba07ff1f95318ce6/FLAG93571faeb [2025-02-08 14:58:03,067 INFO L384 CDTParser]: Found 1 translation units. [2025-02-08 14:58:03,069 INFO L180 CDTParser]: Scanning /storage/repos/ultimate-jdk21/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_BER_test8-2.i [2025-02-08 14:58:03,085 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/49738f3c6/929bfc73d0094776ba07ff1f95318ce6/FLAG93571faeb [2025-02-08 14:58:03,098 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/data/49738f3c6/929bfc73d0094776ba07ff1f95318ce6 [2025-02-08 14:58:03,100 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-02-08 14:58:03,101 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-02-08 14:58:03,102 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-02-08 14:58:03,102 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-02-08 14:58:03,106 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-02-08 14:58:03,106 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,107 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5ba8ab43 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03, skipping insertion in model container [2025-02-08 14:58:03,107 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,143 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-02-08 14:58:03,505 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-08 14:58:03,522 INFO L200 MainTranslator]: Completed pre-run [2025-02-08 14:58:03,638 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-02-08 14:58:03,676 INFO L204 MainTranslator]: Completed translation [2025-02-08 14:58:03,676 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03 WrapperNode [2025-02-08 14:58:03,676 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-02-08 14:58:03,677 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-02-08 14:58:03,677 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-02-08 14:58:03,677 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-02-08 14:58:03,682 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,711 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,782 INFO L138 Inliner]: procedures = 177, calls = 342, calls flagged for inlining = 21, calls inlined = 65, statements flattened = 1833 [2025-02-08 14:58:03,783 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-02-08 14:58:03,784 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-02-08 14:58:03,784 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-02-08 14:58:03,784 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-02-08 14:58:03,792 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,793 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,809 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,919 INFO L175 MemorySlicer]: Split 304 memory accesses to 3 slices as follows [268, 2, 34]. 88 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [0, 2, 0]. The 62 writes are split as follows [58, 0, 4]. [2025-02-08 14:58:03,922 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,923 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,974 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,979 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,988 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:03,993 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:04,004 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-02-08 14:58:04,005 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-02-08 14:58:04,005 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-02-08 14:58:04,005 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-02-08 14:58:04,006 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (1/1) ... [2025-02-08 14:58:04,011 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-02-08 14:58:04,023 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 [2025-02-08 14:58:04,040 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-02-08 14:58:04,047 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate-jdk21/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-02-08 14:58:04,068 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-02-08 14:58:04,069 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-02-08 14:58:04,069 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-02-08 14:58:04,069 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-02-08 14:58:04,069 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-02-08 14:58:04,070 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-02-08 14:58:04,071 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-02-08 14:58:04,071 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-02-08 14:58:04,071 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-02-08 14:58:04,309 INFO L257 CfgBuilder]: Building ICFG [2025-02-08 14:58:04,311 INFO L287 CfgBuilder]: Building CFG for each procedure with an implementation [2025-02-08 14:58:06,029 INFO L1324 $ProcedureCfgBuilder]: dead code at ProgramPoint L763: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-02-08 14:58:06,139 INFO L? ?]: Removed 492 outVars from TransFormulas that were not future-live. [2025-02-08 14:58:06,139 INFO L308 CfgBuilder]: Performing block encoding [2025-02-08 14:58:06,210 INFO L332 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-02-08 14:58:06,211 INFO L337 CfgBuilder]: Removed 1 assume(true) statements. [2025-02-08 14:58:06,211 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 08.02 02:58:06 BoogieIcfgContainer [2025-02-08 14:58:06,211 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-02-08 14:58:06,212 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-02-08 14:58:06,212 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-02-08 14:58:06,217 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-02-08 14:58:06,217 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:58:06,218 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 08.02 02:58:03" (1/3) ... [2025-02-08 14:58:06,219 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e66dd23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.02 02:58:06, skipping insertion in model container [2025-02-08 14:58:06,220 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:58:06,220 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 08.02 02:58:03" (2/3) ... [2025-02-08 14:58:06,220 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@6e66dd23 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 08.02 02:58:06, skipping insertion in model container [2025-02-08 14:58:06,220 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-02-08 14:58:06,220 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 08.02 02:58:06" (3/3) ... [2025-02-08 14:58:06,221 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_BER_test8-2.i [2025-02-08 14:58:06,283 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-02-08 14:58:06,283 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-02-08 14:58:06,283 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-02-08 14:58:06,283 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-02-08 14:58:06,284 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-02-08 14:58:06,284 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-02-08 14:58:06,284 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-02-08 14:58:06,284 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-02-08 14:58:06,291 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 573 states, 566 states have (on average 1.6130742049469964) internal successors, (913), 568 states have internal predecessors, (913), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:06,333 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 439 [2025-02-08 14:58:06,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:06,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:06,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:06,341 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:06,341 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-02-08 14:58:06,343 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 573 states, 566 states have (on average 1.6130742049469964) internal successors, (913), 568 states have internal predecessors, (913), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:06,359 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 439 [2025-02-08 14:58:06,359 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:06,359 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:06,360 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:06,360 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:06,364 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:06,365 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume !true;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:06,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:06,372 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 1 times [2025-02-08 14:58:06,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:06,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1793400873] [2025-02-08 14:58:06,379 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:06,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:06,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:06,478 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:06,480 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:06,480 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:06,481 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:06,494 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:06,506 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:06,507 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:06,507 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:06,537 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:06,540 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:06,540 INFO L85 PathProgramCache]: Analyzing trace with hash 61457265, now seen corresponding path program 1 times [2025-02-08 14:58:06,540 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:06,541 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108125534] [2025-02-08 14:58:06,541 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:06,542 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:06,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 21 statements into 1 equivalence classes. [2025-02-08 14:58:06,571 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 21 of 21 statements. [2025-02-08 14:58:06,574 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:06,574 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:06,649 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:06,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:06,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [108125534] [2025-02-08 14:58:06,650 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [108125534] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:06,650 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:06,650 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-02-08 14:58:06,651 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [173489555] [2025-02-08 14:58:06,651 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:06,654 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:06,657 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:06,678 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-02-08 14:58:06,679 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-02-08 14:58:06,682 INFO L87 Difference]: Start difference. First operand has 573 states, 566 states have (on average 1.6130742049469964) internal successors, (913), 568 states have internal predecessors, (913), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 10.5) internal successors, (21), 2 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:06,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:06,814 INFO L93 Difference]: Finished difference Result 542 states and 756 transitions. [2025-02-08 14:58:06,815 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 542 states and 756 transitions. [2025-02-08 14:58:06,826 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 437 [2025-02-08 14:58:06,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 542 states to 446 states and 632 transitions. [2025-02-08 14:58:06,842 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 446 [2025-02-08 14:58:06,844 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 446 [2025-02-08 14:58:06,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 446 states and 632 transitions. [2025-02-08 14:58:06,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:06,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 446 states and 632 transitions. [2025-02-08 14:58:06,863 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 446 states and 632 transitions. [2025-02-08 14:58:06,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 446 to 446. [2025-02-08 14:58:06,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.416289592760181) internal successors, (626), 441 states have internal predecessors, (626), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:06,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 632 transitions. [2025-02-08 14:58:06,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 632 transitions. [2025-02-08 14:58:06,924 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-02-08 14:58:06,927 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 632 transitions. [2025-02-08 14:58:06,928 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-02-08 14:58:06,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 632 transitions. [2025-02-08 14:58:06,931 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 437 [2025-02-08 14:58:06,932 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:06,932 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:06,934 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:06,935 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:06,935 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:06,936 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem32#1 := read~int#0(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem32#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem33#1 := read~int#0(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem33#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem34#1 := read~int#0(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem34#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem35#1 := read~int#0(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem35#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem36#1 := read~int#0(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem36#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem38#1 := read~int#0(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem38#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem38#1 % 256 % 4294967296 else main_#t~mem38#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:06,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:06,942 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 2 times [2025-02-08 14:58:06,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:06,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1291402408] [2025-02-08 14:58:06,942 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:58:06,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:06,961 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:06,973 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:06,973 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:06,973 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:06,974 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:06,980 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:06,985 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:06,985 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:06,985 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:06,994 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:06,994 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:06,995 INFO L85 PathProgramCache]: Analyzing trace with hash -882695326, now seen corresponding path program 1 times [2025-02-08 14:58:06,995 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:06,995 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [749847686] [2025-02-08 14:58:06,995 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:06,995 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:07,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 90 statements into 1 equivalence classes. [2025-02-08 14:58:07,074 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 90 of 90 statements. [2025-02-08 14:58:07,077 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:07,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:07,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:07,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:07,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [749847686] [2025-02-08 14:58:07,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [749847686] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:07,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:07,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-08 14:58:07,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756210976] [2025-02-08 14:58:07,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:07,468 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:07,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:07,469 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-08 14:58:07,469 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-08 14:58:07,470 INFO L87 Difference]: Start difference. First operand 446 states and 632 transitions. cyclomatic complexity: 190 Second operand has 4 states, 4 states have (on average 22.5) internal successors, (90), 4 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:07,694 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:07,695 INFO L93 Difference]: Finished difference Result 449 states and 628 transitions. [2025-02-08 14:58:07,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 449 states and 628 transitions. [2025-02-08 14:58:07,698 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 440 [2025-02-08 14:58:07,701 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 449 states to 449 states and 628 transitions. [2025-02-08 14:58:07,701 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 449 [2025-02-08 14:58:07,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 449 [2025-02-08 14:58:07,707 INFO L73 IsDeterministic]: Start isDeterministic. Operand 449 states and 628 transitions. [2025-02-08 14:58:07,709 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:07,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 449 states and 628 transitions. [2025-02-08 14:58:07,713 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states and 628 transitions. [2025-02-08 14:58:07,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 446. [2025-02-08 14:58:07,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 446 states, 442 states have (on average 1.4004524886877827) internal successors, (619), 441 states have internal predecessors, (619), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:07,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 625 transitions. [2025-02-08 14:58:07,724 INFO L240 hiAutomatonCegarLoop]: Abstraction has 446 states and 625 transitions. [2025-02-08 14:58:07,724 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-08 14:58:07,725 INFO L432 stractBuchiCegarLoop]: Abstraction has 446 states and 625 transitions. [2025-02-08 14:58:07,725 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-02-08 14:58:07,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 446 states and 625 transitions. [2025-02-08 14:58:07,727 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 437 [2025-02-08 14:58:07,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:07,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:07,728 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:07,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:07,729 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:07,729 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:07,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:07,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 3 times [2025-02-08 14:58:07,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:07,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1910263036] [2025-02-08 14:58:07,730 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:58:07,730 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:07,743 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:07,750 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:07,752 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:58:07,752 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:07,752 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:07,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:07,761 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:07,764 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:07,764 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:07,773 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:07,777 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:07,777 INFO L85 PathProgramCache]: Analyzing trace with hash -2039362532, now seen corresponding path program 1 times [2025-02-08 14:58:07,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:07,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407039330] [2025-02-08 14:58:07,778 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:07,778 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:07,840 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 90 statements into 1 equivalence classes. [2025-02-08 14:58:08,004 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 90 of 90 statements. [2025-02-08 14:58:08,005 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:08,005 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:08,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:08,621 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:08,621 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1407039330] [2025-02-08 14:58:08,621 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1407039330] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:08,621 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:08,621 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-02-08 14:58:08,621 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [617330298] [2025-02-08 14:58:08,621 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:08,621 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:08,621 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:08,622 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-02-08 14:58:08,622 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-02-08 14:58:08,622 INFO L87 Difference]: Start difference. First operand 446 states and 625 transitions. cyclomatic complexity: 183 Second operand has 6 states, 6 states have (on average 15.0) internal successors, (90), 6 states have internal predecessors, (90), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:09,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:09,426 INFO L93 Difference]: Finished difference Result 480 states and 668 transitions. [2025-02-08 14:58:09,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 480 states and 668 transitions. [2025-02-08 14:58:09,432 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 471 [2025-02-08 14:58:09,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 480 states to 480 states and 668 transitions. [2025-02-08 14:58:09,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 480 [2025-02-08 14:58:09,437 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 480 [2025-02-08 14:58:09,437 INFO L73 IsDeterministic]: Start isDeterministic. Operand 480 states and 668 transitions. [2025-02-08 14:58:09,438 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:09,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 480 states and 668 transitions. [2025-02-08 14:58:09,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 480 states and 668 transitions. [2025-02-08 14:58:09,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 480 to 475. [2025-02-08 14:58:09,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 475 states, 471 states have (on average 1.3906581740976645) internal successors, (655), 470 states have internal predecessors, (655), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:09,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 475 states to 475 states and 661 transitions. [2025-02-08 14:58:09,452 INFO L240 hiAutomatonCegarLoop]: Abstraction has 475 states and 661 transitions. [2025-02-08 14:58:09,453 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-08 14:58:09,453 INFO L432 stractBuchiCegarLoop]: Abstraction has 475 states and 661 transitions. [2025-02-08 14:58:09,453 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-02-08 14:58:09,453 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 475 states and 661 transitions. [2025-02-08 14:58:09,455 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 466 [2025-02-08 14:58:09,455 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:09,455 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:09,459 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:09,459 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:09,460 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:09,460 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:09,461 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:09,462 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 4 times [2025-02-08 14:58:09,462 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:09,462 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885195510] [2025-02-08 14:58:09,462 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:58:09,462 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:09,473 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-02-08 14:58:09,478 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:09,478 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:58:09,478 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:09,478 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:09,482 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:09,484 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:09,484 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:09,484 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:09,490 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:09,490 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:09,490 INFO L85 PathProgramCache]: Analyzing trace with hash -1721762882, now seen corresponding path program 1 times [2025-02-08 14:58:09,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:09,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [255591173] [2025-02-08 14:58:09,491 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:09,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:09,541 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-02-08 14:58:09,602 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-02-08 14:58:09,602 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:09,602 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:09,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:09,919 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:09,920 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [255591173] [2025-02-08 14:58:09,920 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [255591173] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:09,920 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:09,920 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-08 14:58:09,920 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [497995581] [2025-02-08 14:58:09,920 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:09,921 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:09,921 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:09,921 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-08 14:58:09,922 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-08 14:58:09,922 INFO L87 Difference]: Start difference. First operand 475 states and 661 transitions. cyclomatic complexity: 190 Second operand has 7 states, 7 states have (on average 13.0) internal successors, (91), 7 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:10,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:10,702 INFO L93 Difference]: Finished difference Result 488 states and 680 transitions. [2025-02-08 14:58:10,702 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 488 states and 680 transitions. [2025-02-08 14:58:10,705 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 479 [2025-02-08 14:58:10,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 488 states to 488 states and 680 transitions. [2025-02-08 14:58:10,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2025-02-08 14:58:10,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2025-02-08 14:58:10,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 488 states and 680 transitions. [2025-02-08 14:58:10,711 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:10,711 INFO L218 hiAutomatonCegarLoop]: Abstraction has 488 states and 680 transitions. [2025-02-08 14:58:10,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states and 680 transitions. [2025-02-08 14:58:10,718 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 485. [2025-02-08 14:58:10,719 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 481 states have (on average 1.392931392931393) internal successors, (670), 480 states have internal predecessors, (670), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:10,722 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 676 transitions. [2025-02-08 14:58:10,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 485 states and 676 transitions. [2025-02-08 14:58:10,723 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-08 14:58:10,724 INFO L432 stractBuchiCegarLoop]: Abstraction has 485 states and 676 transitions. [2025-02-08 14:58:10,724 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-02-08 14:58:10,724 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 676 transitions. [2025-02-08 14:58:10,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 476 [2025-02-08 14:58:10,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:10,726 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:10,729 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:10,729 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:10,729 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:10,730 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:10,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:10,730 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 5 times [2025-02-08 14:58:10,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:10,730 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [803871052] [2025-02-08 14:58:10,731 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:58:10,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:10,740 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:10,743 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:10,743 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:10,743 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:10,744 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:10,747 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:10,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:10,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:10,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:10,755 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:10,755 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:10,756 INFO L85 PathProgramCache]: Analyzing trace with hash 1279210231, now seen corresponding path program 1 times [2025-02-08 14:58:10,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:10,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [678383086] [2025-02-08 14:58:10,757 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:10,757 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:10,796 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 91 statements into 1 equivalence classes. [2025-02-08 14:58:10,951 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 91 of 91 statements. [2025-02-08 14:58:10,951 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:10,951 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:11,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:11,261 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:11,261 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [678383086] [2025-02-08 14:58:11,261 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [678383086] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:11,261 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:11,261 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-02-08 14:58:11,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1707715047] [2025-02-08 14:58:11,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:11,262 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:11,262 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:11,262 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-02-08 14:58:11,262 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-02-08 14:58:11,262 INFO L87 Difference]: Start difference. First operand 485 states and 676 transitions. cyclomatic complexity: 195 Second operand has 4 states, 4 states have (on average 22.75) internal successors, (91), 4 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:11,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:11,569 INFO L93 Difference]: Finished difference Result 488 states and 679 transitions. [2025-02-08 14:58:11,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 488 states and 679 transitions. [2025-02-08 14:58:11,572 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 479 [2025-02-08 14:58:11,576 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 488 states to 488 states and 679 transitions. [2025-02-08 14:58:11,576 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 488 [2025-02-08 14:58:11,576 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 488 [2025-02-08 14:58:11,576 INFO L73 IsDeterministic]: Start isDeterministic. Operand 488 states and 679 transitions. [2025-02-08 14:58:11,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:11,577 INFO L218 hiAutomatonCegarLoop]: Abstraction has 488 states and 679 transitions. [2025-02-08 14:58:11,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states and 679 transitions. [2025-02-08 14:58:11,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 485. [2025-02-08 14:58:11,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 485 states, 481 states have (on average 1.3908523908523909) internal successors, (669), 480 states have internal predecessors, (669), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:11,587 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 675 transitions. [2025-02-08 14:58:11,587 INFO L240 hiAutomatonCegarLoop]: Abstraction has 485 states and 675 transitions. [2025-02-08 14:58:11,587 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-02-08 14:58:11,588 INFO L432 stractBuchiCegarLoop]: Abstraction has 485 states and 675 transitions. [2025-02-08 14:58:11,588 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-02-08 14:58:11,588 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 485 states and 675 transitions. [2025-02-08 14:58:11,590 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 476 [2025-02-08 14:58:11,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:11,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:11,591 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:11,591 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:11,591 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:11,592 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:11,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:11,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 6 times [2025-02-08 14:58:11,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:11,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [20874274] [2025-02-08 14:58:11,593 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:58:11,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:11,601 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:11,603 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:11,604 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:58:11,604 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:11,604 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:11,607 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:11,609 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:11,609 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:11,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:11,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:11,615 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:11,615 INFO L85 PathProgramCache]: Analyzing trace with hash -424538397, now seen corresponding path program 1 times [2025-02-08 14:58:11,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:11,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1216976970] [2025-02-08 14:58:11,616 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:11,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:11,651 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-02-08 14:58:11,678 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-02-08 14:58:11,679 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:11,679 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:12,181 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:12,182 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:12,182 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1216976970] [2025-02-08 14:58:12,182 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1216976970] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:12,182 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:12,182 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-08 14:58:12,182 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1864378231] [2025-02-08 14:58:12,182 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:12,183 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:12,183 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:12,183 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-08 14:58:12,184 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-02-08 14:58:12,184 INFO L87 Difference]: Start difference. First operand 485 states and 675 transitions. cyclomatic complexity: 194 Second operand has 9 states, 9 states have (on average 10.222222222222221) internal successors, (92), 9 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:13,292 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:13,292 INFO L93 Difference]: Finished difference Result 499 states and 693 transitions. [2025-02-08 14:58:13,293 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 499 states and 693 transitions. [2025-02-08 14:58:13,296 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 490 [2025-02-08 14:58:13,299 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 499 states to 499 states and 693 transitions. [2025-02-08 14:58:13,299 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 499 [2025-02-08 14:58:13,300 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 499 [2025-02-08 14:58:13,300 INFO L73 IsDeterministic]: Start isDeterministic. Operand 499 states and 693 transitions. [2025-02-08 14:58:13,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:13,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 499 states and 693 transitions. [2025-02-08 14:58:13,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 499 states and 693 transitions. [2025-02-08 14:58:13,307 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 499 to 493. [2025-02-08 14:58:13,307 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 493 states, 489 states have (on average 1.3885480572597138) internal successors, (679), 488 states have internal predecessors, (679), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:13,309 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 685 transitions. [2025-02-08 14:58:13,310 INFO L240 hiAutomatonCegarLoop]: Abstraction has 493 states and 685 transitions. [2025-02-08 14:58:13,310 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-02-08 14:58:13,311 INFO L432 stractBuchiCegarLoop]: Abstraction has 493 states and 685 transitions. [2025-02-08 14:58:13,311 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-02-08 14:58:13,311 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 493 states and 685 transitions. [2025-02-08 14:58:13,313 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 484 [2025-02-08 14:58:13,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:13,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:13,314 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:13,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:13,315 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:13,316 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:13,316 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:13,316 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 7 times [2025-02-08 14:58:13,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:13,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1570684331] [2025-02-08 14:58:13,316 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:58:13,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:13,325 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:13,327 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:13,327 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:13,327 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:13,327 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:13,330 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:13,332 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:13,332 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:13,332 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:13,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:13,339 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:13,339 INFO L85 PathProgramCache]: Analyzing trace with hash 1154276735, now seen corresponding path program 1 times [2025-02-08 14:58:13,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:13,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1877082554] [2025-02-08 14:58:13,339 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:13,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:13,376 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 92 statements into 1 equivalence classes. [2025-02-08 14:58:13,404 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 92 of 92 statements. [2025-02-08 14:58:13,405 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:13,405 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:13,647 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:13,647 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:13,647 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1877082554] [2025-02-08 14:58:13,648 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1877082554] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:13,648 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:13,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-02-08 14:58:13,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9677695] [2025-02-08 14:58:13,649 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:13,649 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:13,649 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:13,649 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-02-08 14:58:13,650 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-02-08 14:58:13,650 INFO L87 Difference]: Start difference. First operand 493 states and 685 transitions. cyclomatic complexity: 196 Second operand has 6 states, 6 states have (on average 15.333333333333334) internal successors, (92), 6 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:14,182 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:14,182 INFO L93 Difference]: Finished difference Result 496 states and 688 transitions. [2025-02-08 14:58:14,182 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 496 states and 688 transitions. [2025-02-08 14:58:14,186 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 487 [2025-02-08 14:58:14,190 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 496 states to 496 states and 688 transitions. [2025-02-08 14:58:14,190 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 496 [2025-02-08 14:58:14,190 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 496 [2025-02-08 14:58:14,190 INFO L73 IsDeterministic]: Start isDeterministic. Operand 496 states and 688 transitions. [2025-02-08 14:58:14,191 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:14,191 INFO L218 hiAutomatonCegarLoop]: Abstraction has 496 states and 688 transitions. [2025-02-08 14:58:14,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states and 688 transitions. [2025-02-08 14:58:14,201 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 496. [2025-02-08 14:58:14,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 492 states have (on average 1.386178861788618) internal successors, (682), 491 states have internal predecessors, (682), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:14,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 688 transitions. [2025-02-08 14:58:14,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 496 states and 688 transitions. [2025-02-08 14:58:14,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-02-08 14:58:14,207 INFO L432 stractBuchiCegarLoop]: Abstraction has 496 states and 688 transitions. [2025-02-08 14:58:14,208 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-02-08 14:58:14,208 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 688 transitions. [2025-02-08 14:58:14,210 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 487 [2025-02-08 14:58:14,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:14,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:14,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:14,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:14,211 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:14,212 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:14,212 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:14,212 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 8 times [2025-02-08 14:58:14,212 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:14,212 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [830652463] [2025-02-08 14:58:14,212 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:58:14,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:14,224 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:14,226 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:14,226 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:14,226 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:14,226 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:14,229 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:14,231 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:14,231 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:14,231 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:14,237 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:14,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:14,238 INFO L85 PathProgramCache]: Analyzing trace with hash -1859140020, now seen corresponding path program 1 times [2025-02-08 14:58:14,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:14,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782392099] [2025-02-08 14:58:14,238 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:14,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:14,283 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-02-08 14:58:14,481 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-02-08 14:58:14,482 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:14,482 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:15,232 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:15,232 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:15,233 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782392099] [2025-02-08 14:58:15,233 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782392099] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:15,233 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:15,233 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-08 14:58:15,233 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [351204763] [2025-02-08 14:58:15,233 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:15,233 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:15,234 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:15,234 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-08 14:58:15,234 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-02-08 14:58:15,235 INFO L87 Difference]: Start difference. First operand 496 states and 688 transitions. cyclomatic complexity: 196 Second operand has 13 states, 13 states have (on average 7.153846153846154) internal successors, (93), 13 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:17,149 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:17,149 INFO L93 Difference]: Finished difference Result 594 states and 828 transitions. [2025-02-08 14:58:17,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 594 states and 828 transitions. [2025-02-08 14:58:17,153 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 585 [2025-02-08 14:58:17,157 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 594 states to 594 states and 828 transitions. [2025-02-08 14:58:17,157 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 594 [2025-02-08 14:58:17,158 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 594 [2025-02-08 14:58:17,158 INFO L73 IsDeterministic]: Start isDeterministic. Operand 594 states and 828 transitions. [2025-02-08 14:58:17,159 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:17,159 INFO L218 hiAutomatonCegarLoop]: Abstraction has 594 states and 828 transitions. [2025-02-08 14:58:17,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 594 states and 828 transitions. [2025-02-08 14:58:17,166 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 594 to 502. [2025-02-08 14:58:17,167 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 502 states, 498 states have (on average 1.3855421686746987) internal successors, (690), 497 states have internal predecessors, (690), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:17,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 696 transitions. [2025-02-08 14:58:17,169 INFO L240 hiAutomatonCegarLoop]: Abstraction has 502 states and 696 transitions. [2025-02-08 14:58:17,170 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-02-08 14:58:17,170 INFO L432 stractBuchiCegarLoop]: Abstraction has 502 states and 696 transitions. [2025-02-08 14:58:17,170 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-02-08 14:58:17,170 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 502 states and 696 transitions. [2025-02-08 14:58:17,172 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-02-08 14:58:17,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:17,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:17,173 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:17,173 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:17,173 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:17,174 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:17,174 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:17,174 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 9 times [2025-02-08 14:58:17,174 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:17,174 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292218711] [2025-02-08 14:58:17,174 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:58:17,174 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:17,182 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:17,184 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:17,184 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:58:17,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:17,185 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:17,188 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:17,189 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:17,190 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:17,190 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:17,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:17,196 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:17,196 INFO L85 PathProgramCache]: Analyzing trace with hash 107223261, now seen corresponding path program 1 times [2025-02-08 14:58:17,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:17,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1814941559] [2025-02-08 14:58:17,196 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:17,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:17,231 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 93 statements into 1 equivalence classes. [2025-02-08 14:58:17,278 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 93 of 93 statements. [2025-02-08 14:58:17,278 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:17,278 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:17,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:17,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:17,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1814941559] [2025-02-08 14:58:17,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1814941559] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:17,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:17,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-08 14:58:17,543 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038219150] [2025-02-08 14:58:17,543 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:17,543 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:17,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:17,543 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-08 14:58:17,544 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-08 14:58:17,544 INFO L87 Difference]: Start difference. First operand 502 states and 696 transitions. cyclomatic complexity: 198 Second operand has 7 states, 7 states have (on average 13.285714285714286) internal successors, (93), 7 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:18,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:18,386 INFO L93 Difference]: Finished difference Result 509 states and 705 transitions. [2025-02-08 14:58:18,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 509 states and 705 transitions. [2025-02-08 14:58:18,389 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 500 [2025-02-08 14:58:18,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 509 states to 509 states and 705 transitions. [2025-02-08 14:58:18,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 509 [2025-02-08 14:58:18,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 509 [2025-02-08 14:58:18,393 INFO L73 IsDeterministic]: Start isDeterministic. Operand 509 states and 705 transitions. [2025-02-08 14:58:18,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:18,394 INFO L218 hiAutomatonCegarLoop]: Abstraction has 509 states and 705 transitions. [2025-02-08 14:58:18,395 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 509 states and 705 transitions. [2025-02-08 14:58:18,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 509 to 502. [2025-02-08 14:58:18,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 502 states, 498 states have (on average 1.3855421686746987) internal successors, (690), 497 states have internal predecessors, (690), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:18,402 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 696 transitions. [2025-02-08 14:58:18,402 INFO L240 hiAutomatonCegarLoop]: Abstraction has 502 states and 696 transitions. [2025-02-08 14:58:18,403 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-08 14:58:18,403 INFO L432 stractBuchiCegarLoop]: Abstraction has 502 states and 696 transitions. [2025-02-08 14:58:18,403 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-02-08 14:58:18,403 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 502 states and 696 transitions. [2025-02-08 14:58:18,405 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-02-08 14:58:18,405 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:18,405 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:18,406 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:18,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:18,406 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:18,408 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:18,409 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:18,409 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 10 times [2025-02-08 14:58:18,409 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:18,409 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [940495580] [2025-02-08 14:58:18,409 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:58:18,410 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:18,418 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-02-08 14:58:18,420 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:18,420 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:58:18,420 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:18,420 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:18,423 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:18,425 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:18,425 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:18,425 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:18,431 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:18,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:18,432 INFO L85 PathProgramCache]: Analyzing trace with hash 439457188, now seen corresponding path program 1 times [2025-02-08 14:58:18,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:18,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [893970558] [2025-02-08 14:58:18,432 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:18,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:18,466 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-02-08 14:58:18,608 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-02-08 14:58:18,608 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:18,608 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:18,876 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:18,876 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:18,876 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [893970558] [2025-02-08 14:58:18,876 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [893970558] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:18,876 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:18,876 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-08 14:58:18,876 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [473891293] [2025-02-08 14:58:18,876 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:18,877 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:18,877 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:18,877 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-08 14:58:18,877 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-02-08 14:58:18,877 INFO L87 Difference]: Start difference. First operand 502 states and 696 transitions. cyclomatic complexity: 198 Second operand has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:19,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:19,994 INFO L93 Difference]: Finished difference Result 522 states and 722 transitions. [2025-02-08 14:58:19,995 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 722 transitions. [2025-02-08 14:58:20,015 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 513 [2025-02-08 14:58:20,018 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 722 transitions. [2025-02-08 14:58:20,018 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2025-02-08 14:58:20,019 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2025-02-08 14:58:20,019 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 722 transitions. [2025-02-08 14:58:20,020 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:20,020 INFO L218 hiAutomatonCegarLoop]: Abstraction has 522 states and 722 transitions. [2025-02-08 14:58:20,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 722 transitions. [2025-02-08 14:58:20,026 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 505. [2025-02-08 14:58:20,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 505 states, 501 states have (on average 1.3852295409181636) internal successors, (694), 500 states have internal predecessors, (694), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:20,029 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 505 states to 505 states and 700 transitions. [2025-02-08 14:58:20,029 INFO L240 hiAutomatonCegarLoop]: Abstraction has 505 states and 700 transitions. [2025-02-08 14:58:20,030 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:20,030 INFO L432 stractBuchiCegarLoop]: Abstraction has 505 states and 700 transitions. [2025-02-08 14:58:20,031 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-02-08 14:58:20,031 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 505 states and 700 transitions. [2025-02-08 14:58:20,033 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 496 [2025-02-08 14:58:20,033 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:20,033 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:20,034 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:20,034 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:20,034 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:20,034 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:20,035 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:20,035 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 11 times [2025-02-08 14:58:20,035 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:20,035 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1760781143] [2025-02-08 14:58:20,035 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:58:20,035 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:20,044 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:20,047 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:20,047 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:20,047 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:20,047 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:20,050 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:20,053 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:20,054 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:20,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:20,061 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:20,062 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:20,062 INFO L85 PathProgramCache]: Analyzing trace with hash 14015068, now seen corresponding path program 1 times [2025-02-08 14:58:20,063 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:20,063 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070183030] [2025-02-08 14:58:20,063 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:20,063 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:20,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-02-08 14:58:20,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-02-08 14:58:20,191 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:20,191 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:20,677 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:20,678 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:20,678 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070183030] [2025-02-08 14:58:20,678 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070183030] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:20,678 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:20,679 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-02-08 14:58:20,679 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2061614533] [2025-02-08 14:58:20,679 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:20,679 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:20,679 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:20,679 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-02-08 14:58:20,679 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-02-08 14:58:20,679 INFO L87 Difference]: Start difference. First operand 505 states and 700 transitions. cyclomatic complexity: 199 Second operand has 11 states, 11 states have (on average 8.545454545454545) internal successors, (94), 11 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:22,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:22,487 INFO L93 Difference]: Finished difference Result 577 states and 798 transitions. [2025-02-08 14:58:22,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 577 states and 798 transitions. [2025-02-08 14:58:22,490 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 568 [2025-02-08 14:58:22,493 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 577 states to 577 states and 798 transitions. [2025-02-08 14:58:22,493 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 577 [2025-02-08 14:58:22,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 577 [2025-02-08 14:58:22,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 577 states and 798 transitions. [2025-02-08 14:58:22,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:22,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 577 states and 798 transitions. [2025-02-08 14:58:22,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states and 798 transitions. [2025-02-08 14:58:22,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 508. [2025-02-08 14:58:22,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 508 states, 504 states have (on average 1.3849206349206349) internal successors, (698), 503 states have internal predecessors, (698), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:22,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 508 states to 508 states and 704 transitions. [2025-02-08 14:58:22,505 INFO L240 hiAutomatonCegarLoop]: Abstraction has 508 states and 704 transitions. [2025-02-08 14:58:22,506 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-02-08 14:58:22,506 INFO L432 stractBuchiCegarLoop]: Abstraction has 508 states and 704 transitions. [2025-02-08 14:58:22,506 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-02-08 14:58:22,506 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 508 states and 704 transitions. [2025-02-08 14:58:22,508 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 499 [2025-02-08 14:58:22,508 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:22,508 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:22,509 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:22,509 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:22,509 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:22,510 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:22,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:22,510 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 12 times [2025-02-08 14:58:22,510 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:22,510 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [281587373] [2025-02-08 14:58:22,511 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:58:22,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:22,519 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:22,521 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:22,521 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:58:22,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:22,521 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:22,525 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:22,527 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:22,527 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:22,527 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:22,533 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:22,534 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:22,534 INFO L85 PathProgramCache]: Analyzing trace with hash 2056147846, now seen corresponding path program 1 times [2025-02-08 14:58:22,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:22,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846302304] [2025-02-08 14:58:22,535 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:22,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:22,574 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-02-08 14:58:22,595 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-02-08 14:58:22,595 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:22,595 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:22,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:22,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:22,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846302304] [2025-02-08 14:58:22,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846302304] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:22,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:22,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-08 14:58:22,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [119987106] [2025-02-08 14:58:22,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:22,928 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:22,928 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:22,929 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-08 14:58:22,929 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-02-08 14:58:22,929 INFO L87 Difference]: Start difference. First operand 508 states and 704 transitions. cyclomatic complexity: 200 Second operand has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:23,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:23,758 INFO L93 Difference]: Finished difference Result 521 states and 720 transitions. [2025-02-08 14:58:23,759 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 521 states and 720 transitions. [2025-02-08 14:58:23,762 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 512 [2025-02-08 14:58:23,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 521 states to 521 states and 720 transitions. [2025-02-08 14:58:23,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 521 [2025-02-08 14:58:23,766 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 521 [2025-02-08 14:58:23,766 INFO L73 IsDeterministic]: Start isDeterministic. Operand 521 states and 720 transitions. [2025-02-08 14:58:23,767 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:23,768 INFO L218 hiAutomatonCegarLoop]: Abstraction has 521 states and 720 transitions. [2025-02-08 14:58:23,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states and 720 transitions. [2025-02-08 14:58:23,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 508. [2025-02-08 14:58:23,777 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 508 states, 504 states have (on average 1.3849206349206349) internal successors, (698), 503 states have internal predecessors, (698), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:23,779 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 508 states to 508 states and 704 transitions. [2025-02-08 14:58:23,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 508 states and 704 transitions. [2025-02-08 14:58:23,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-02-08 14:58:23,781 INFO L432 stractBuchiCegarLoop]: Abstraction has 508 states and 704 transitions. [2025-02-08 14:58:23,782 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-02-08 14:58:23,782 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 508 states and 704 transitions. [2025-02-08 14:58:23,784 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 499 [2025-02-08 14:58:23,785 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:23,785 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:23,785 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:23,785 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:23,786 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:23,786 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:23,787 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:23,787 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 13 times [2025-02-08 14:58:23,787 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:23,787 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [382327332] [2025-02-08 14:58:23,787 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:58:23,787 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:23,799 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:23,801 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:23,801 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:23,801 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:23,801 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:23,806 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:23,807 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:23,808 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:23,808 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:23,816 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:23,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:23,817 INFO L85 PathProgramCache]: Analyzing trace with hash 1163035747, now seen corresponding path program 1 times [2025-02-08 14:58:23,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:23,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1327788650] [2025-02-08 14:58:23,818 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:23,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:23,866 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-02-08 14:58:24,057 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-02-08 14:58:24,057 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:24,057 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:24,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:24,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:24,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1327788650] [2025-02-08 14:58:24,860 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1327788650] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:24,860 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:24,860 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-02-08 14:58:24,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1284669457] [2025-02-08 14:58:24,860 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:24,860 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:24,860 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:24,861 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-02-08 14:58:24,861 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-02-08 14:58:24,861 INFO L87 Difference]: Start difference. First operand 508 states and 704 transitions. cyclomatic complexity: 200 Second operand has 13 states, 13 states have (on average 7.230769230769231) internal successors, (94), 13 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:37,742 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 12.00s for a HTC check with result UNKNOWN. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-02-08 14:58:38,461 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:38,462 INFO L93 Difference]: Finished difference Result 601 states and 836 transitions. [2025-02-08 14:58:38,462 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 601 states and 836 transitions. [2025-02-08 14:58:38,465 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 592 [2025-02-08 14:58:38,468 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 601 states to 601 states and 836 transitions. [2025-02-08 14:58:38,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 601 [2025-02-08 14:58:38,469 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 601 [2025-02-08 14:58:38,469 INFO L73 IsDeterministic]: Start isDeterministic. Operand 601 states and 836 transitions. [2025-02-08 14:58:38,470 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:38,470 INFO L218 hiAutomatonCegarLoop]: Abstraction has 601 states and 836 transitions. [2025-02-08 14:58:38,471 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 601 states and 836 transitions. [2025-02-08 14:58:38,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 601 to 509. [2025-02-08 14:58:38,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 509 states, 505 states have (on average 1.386138613861386) internal successors, (700), 504 states have internal predecessors, (700), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:38,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 509 states to 509 states and 706 transitions. [2025-02-08 14:58:38,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 509 states and 706 transitions. [2025-02-08 14:58:38,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-02-08 14:58:38,478 INFO L432 stractBuchiCegarLoop]: Abstraction has 509 states and 706 transitions. [2025-02-08 14:58:38,479 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-02-08 14:58:38,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 509 states and 706 transitions. [2025-02-08 14:58:38,480 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 500 [2025-02-08 14:58:38,480 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:38,480 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:38,480 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:38,480 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:38,481 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:38,481 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise48#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:38,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:38,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 14 times [2025-02-08 14:58:38,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:38,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1401572041] [2025-02-08 14:58:38,482 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:58:38,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:38,491 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:38,493 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:38,493 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:38,493 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:38,493 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:38,497 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:38,499 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:38,499 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:38,499 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:38,504 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:38,506 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:38,506 INFO L85 PathProgramCache]: Analyzing trace with hash -1959787478, now seen corresponding path program 1 times [2025-02-08 14:58:38,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:38,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1405689039] [2025-02-08 14:58:38,506 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:38,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:38,540 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 94 statements into 1 equivalence classes. [2025-02-08 14:58:38,658 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 94 of 94 statements. [2025-02-08 14:58:38,659 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:38,659 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:39,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:39,456 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:39,457 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1405689039] [2025-02-08 14:58:39,457 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1405689039] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:39,457 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:39,457 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-08 14:58:39,457 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967435274] [2025-02-08 14:58:39,457 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:39,457 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:39,457 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:39,458 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-08 14:58:39,458 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-02-08 14:58:39,458 INFO L87 Difference]: Start difference. First operand 509 states and 706 transitions. cyclomatic complexity: 201 Second operand has 9 states, 9 states have (on average 10.444444444444445) internal successors, (94), 9 states have internal predecessors, (94), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:40,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:40,191 INFO L93 Difference]: Finished difference Result 501 states and 693 transitions. [2025-02-08 14:58:40,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 501 states and 693 transitions. [2025-02-08 14:58:40,194 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 492 [2025-02-08 14:58:40,196 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 501 states to 501 states and 693 transitions. [2025-02-08 14:58:40,196 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 501 [2025-02-08 14:58:40,197 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 501 [2025-02-08 14:58:40,197 INFO L73 IsDeterministic]: Start isDeterministic. Operand 501 states and 693 transitions. [2025-02-08 14:58:40,198 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:40,198 INFO L218 hiAutomatonCegarLoop]: Abstraction has 501 states and 693 transitions. [2025-02-08 14:58:40,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 501 states and 693 transitions. [2025-02-08 14:58:40,205 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 501 to 496. [2025-02-08 14:58:40,206 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 496 states, 492 states have (on average 1.3841463414634145) internal successors, (681), 491 states have internal predecessors, (681), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:40,207 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 687 transitions. [2025-02-08 14:58:40,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 496 states and 687 transitions. [2025-02-08 14:58:40,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-02-08 14:58:40,209 INFO L432 stractBuchiCegarLoop]: Abstraction has 496 states and 687 transitions. [2025-02-08 14:58:40,209 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-02-08 14:58:40,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 496 states and 687 transitions. [2025-02-08 14:58:40,211 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 487 [2025-02-08 14:58:40,211 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:40,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:40,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:40,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:40,212 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:40,212 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:40,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:40,213 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 15 times [2025-02-08 14:58:40,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:40,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1623882788] [2025-02-08 14:58:40,213 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:58:40,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:40,222 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:40,224 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:40,224 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:58:40,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:40,224 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:40,228 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:40,229 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:40,229 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:40,229 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:40,236 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:40,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:40,237 INFO L85 PathProgramCache]: Analyzing trace with hash -1633418317, now seen corresponding path program 1 times [2025-02-08 14:58:40,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:40,237 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1367708864] [2025-02-08 14:58:40,237 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:40,237 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:40,270 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-02-08 14:58:40,337 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:58:40,339 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:40,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:40,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:40,899 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:40,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1367708864] [2025-02-08 14:58:40,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1367708864] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:40,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:40,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2025-02-08 14:58:40,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1512544008] [2025-02-08 14:58:40,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:40,900 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:40,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:40,901 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2025-02-08 14:58:40,901 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2025-02-08 14:58:40,901 INFO L87 Difference]: Start difference. First operand 496 states and 687 transitions. cyclomatic complexity: 195 Second operand has 12 states, 12 states have (on average 7.916666666666667) internal successors, (95), 12 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:43,538 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 1.79s for a HTC check with result INVALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-02-08 14:58:43,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:43,840 INFO L93 Difference]: Finished difference Result 550 states and 763 transitions. [2025-02-08 14:58:43,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 550 states and 763 transitions. [2025-02-08 14:58:43,842 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 541 [2025-02-08 14:58:43,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 550 states to 550 states and 763 transitions. [2025-02-08 14:58:43,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 550 [2025-02-08 14:58:43,846 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 550 [2025-02-08 14:58:43,846 INFO L73 IsDeterministic]: Start isDeterministic. Operand 550 states and 763 transitions. [2025-02-08 14:58:43,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:43,849 INFO L218 hiAutomatonCegarLoop]: Abstraction has 550 states and 763 transitions. [2025-02-08 14:58:43,850 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states and 763 transitions. [2025-02-08 14:58:43,855 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 506. [2025-02-08 14:58:43,856 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 506 states, 502 states have (on average 1.3824701195219125) internal successors, (694), 501 states have internal predecessors, (694), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:43,859 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 700 transitions. [2025-02-08 14:58:43,859 INFO L240 hiAutomatonCegarLoop]: Abstraction has 506 states and 700 transitions. [2025-02-08 14:58:43,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-02-08 14:58:43,860 INFO L432 stractBuchiCegarLoop]: Abstraction has 506 states and 700 transitions. [2025-02-08 14:58:43,860 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-02-08 14:58:43,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 506 states and 700 transitions. [2025-02-08 14:58:43,861 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 497 [2025-02-08 14:58:43,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:43,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:43,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:43,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:43,862 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:43,863 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:43,863 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:43,863 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 16 times [2025-02-08 14:58:43,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:43,864 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [869264733] [2025-02-08 14:58:43,864 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:58:43,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:43,872 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-02-08 14:58:43,874 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:43,874 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:58:43,874 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:43,874 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:43,880 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:43,881 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:43,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:43,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:43,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:43,888 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:43,889 INFO L85 PathProgramCache]: Analyzing trace with hash 1128854626, now seen corresponding path program 1 times [2025-02-08 14:58:43,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:43,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1217174628] [2025-02-08 14:58:43,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:43,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:43,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-02-08 14:58:43,976 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:58:43,976 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:43,976 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:44,342 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:44,342 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:44,343 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1217174628] [2025-02-08 14:58:44,343 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1217174628] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:44,343 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:44,343 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-08 14:58:44,343 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2101826849] [2025-02-08 14:58:44,343 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:44,343 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:44,343 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:44,344 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-08 14:58:44,344 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2025-02-08 14:58:44,344 INFO L87 Difference]: Start difference. First operand 506 states and 700 transitions. cyclomatic complexity: 198 Second operand has 10 states, 10 states have (on average 9.5) internal successors, (95), 10 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:45,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:45,433 INFO L93 Difference]: Finished difference Result 522 states and 721 transitions. [2025-02-08 14:58:45,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 522 states and 721 transitions. [2025-02-08 14:58:45,435 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 513 [2025-02-08 14:58:45,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 522 states to 522 states and 721 transitions. [2025-02-08 14:58:45,438 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 522 [2025-02-08 14:58:45,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 522 [2025-02-08 14:58:45,438 INFO L73 IsDeterministic]: Start isDeterministic. Operand 522 states and 721 transitions. [2025-02-08 14:58:45,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:45,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 522 states and 721 transitions. [2025-02-08 14:58:45,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states and 721 transitions. [2025-02-08 14:58:45,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 516. [2025-02-08 14:58:45,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 516 states, 512 states have (on average 1.37890625) internal successors, (706), 511 states have internal predecessors, (706), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:45,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 712 transitions. [2025-02-08 14:58:45,447 INFO L240 hiAutomatonCegarLoop]: Abstraction has 516 states and 712 transitions. [2025-02-08 14:58:45,448 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:45,448 INFO L432 stractBuchiCegarLoop]: Abstraction has 516 states and 712 transitions. [2025-02-08 14:58:45,448 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-02-08 14:58:45,449 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 516 states and 712 transitions. [2025-02-08 14:58:45,450 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 507 [2025-02-08 14:58:45,450 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:45,450 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:45,450 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:45,451 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:45,451 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:45,451 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:45,452 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:45,452 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 17 times [2025-02-08 14:58:45,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:45,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812368519] [2025-02-08 14:58:45,452 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:58:45,452 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:45,459 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:45,461 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:45,461 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:45,461 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:45,461 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:45,464 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:45,465 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:45,465 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:45,465 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:45,471 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:45,471 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:45,472 INFO L85 PathProgramCache]: Analyzing trace with hash -1743915516, now seen corresponding path program 1 times [2025-02-08 14:58:45,472 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:45,472 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982645046] [2025-02-08 14:58:45,472 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:45,472 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:45,502 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-02-08 14:58:45,542 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:58:45,543 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:45,543 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:45,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:45,864 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:45,864 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982645046] [2025-02-08 14:58:45,864 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982645046] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:45,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:45,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-08 14:58:45,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [264397500] [2025-02-08 14:58:45,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:45,864 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:45,865 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:45,865 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-08 14:58:45,865 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-02-08 14:58:45,866 INFO L87 Difference]: Start difference. First operand 516 states and 712 transitions. cyclomatic complexity: 200 Second operand has 10 states, 10 states have (on average 9.5) internal successors, (95), 10 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:46,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:46,962 INFO L93 Difference]: Finished difference Result 531 states and 733 transitions. [2025-02-08 14:58:46,962 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 531 states and 733 transitions. [2025-02-08 14:58:46,964 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 522 [2025-02-08 14:58:46,969 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 531 states to 531 states and 733 transitions. [2025-02-08 14:58:46,969 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 531 [2025-02-08 14:58:46,969 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 531 [2025-02-08 14:58:46,969 INFO L73 IsDeterministic]: Start isDeterministic. Operand 531 states and 733 transitions. [2025-02-08 14:58:46,970 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:46,970 INFO L218 hiAutomatonCegarLoop]: Abstraction has 531 states and 733 transitions. [2025-02-08 14:58:46,971 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states and 733 transitions. [2025-02-08 14:58:46,975 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 516. [2025-02-08 14:58:46,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 516 states, 512 states have (on average 1.37890625) internal successors, (706), 511 states have internal predecessors, (706), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:46,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 516 states to 516 states and 712 transitions. [2025-02-08 14:58:46,977 INFO L240 hiAutomatonCegarLoop]: Abstraction has 516 states and 712 transitions. [2025-02-08 14:58:46,978 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:46,978 INFO L432 stractBuchiCegarLoop]: Abstraction has 516 states and 712 transitions. [2025-02-08 14:58:46,978 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-02-08 14:58:46,979 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 516 states and 712 transitions. [2025-02-08 14:58:46,980 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 507 [2025-02-08 14:58:46,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:46,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:46,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:46,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:46,981 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:46,981 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:46,982 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:46,982 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 18 times [2025-02-08 14:58:46,982 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:46,982 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1407309837] [2025-02-08 14:58:46,982 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:58:46,982 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:46,990 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:46,992 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:46,992 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:58:46,992 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:46,992 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:46,995 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:46,996 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:46,996 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:46,996 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:47,002 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:47,002 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:47,002 INFO L85 PathProgramCache]: Analyzing trace with hash 1015266208, now seen corresponding path program 1 times [2025-02-08 14:58:47,002 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:47,003 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901270838] [2025-02-08 14:58:47,003 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:47,003 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:47,036 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-02-08 14:58:47,074 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:58:47,075 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:47,075 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:47,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:47,283 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:47,283 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901270838] [2025-02-08 14:58:47,283 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901270838] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:47,283 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:47,283 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-08 14:58:47,283 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [787249506] [2025-02-08 14:58:47,283 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:47,283 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:47,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:47,284 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-08 14:58:47,284 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-08 14:58:47,284 INFO L87 Difference]: Start difference. First operand 516 states and 712 transitions. cyclomatic complexity: 200 Second operand has 7 states, 7 states have (on average 13.571428571428571) internal successors, (95), 7 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:47,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:47,866 INFO L93 Difference]: Finished difference Result 521 states and 718 transitions. [2025-02-08 14:58:47,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 521 states and 718 transitions. [2025-02-08 14:58:47,867 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 512 [2025-02-08 14:58:47,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 521 states to 521 states and 718 transitions. [2025-02-08 14:58:47,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 521 [2025-02-08 14:58:47,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 521 [2025-02-08 14:58:47,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 521 states and 718 transitions. [2025-02-08 14:58:47,870 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:47,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 521 states and 718 transitions. [2025-02-08 14:58:47,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 521 states and 718 transitions. [2025-02-08 14:58:47,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 521 to 520. [2025-02-08 14:58:47,876 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 520 states, 516 states have (on average 1.377906976744186) internal successors, (711), 515 states have internal predecessors, (711), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:47,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 717 transitions. [2025-02-08 14:58:47,879 INFO L240 hiAutomatonCegarLoop]: Abstraction has 520 states and 717 transitions. [2025-02-08 14:58:47,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-08 14:58:47,880 INFO L432 stractBuchiCegarLoop]: Abstraction has 520 states and 717 transitions. [2025-02-08 14:58:47,881 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-02-08 14:58:47,881 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 520 states and 717 transitions. [2025-02-08 14:58:47,882 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 511 [2025-02-08 14:58:47,882 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:47,882 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:47,883 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:47,883 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:47,883 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:47,884 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:47,884 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:47,884 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 19 times [2025-02-08 14:58:47,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:47,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1643081640] [2025-02-08 14:58:47,884 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-02-08 14:58:47,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:47,892 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:47,893 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:47,893 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:47,894 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:47,894 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:47,896 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:47,898 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:47,898 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:47,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:47,904 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:47,905 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:47,905 INFO L85 PathProgramCache]: Analyzing trace with hash 860106596, now seen corresponding path program 1 times [2025-02-08 14:58:47,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:47,905 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [515694429] [2025-02-08 14:58:47,905 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:47,905 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:47,937 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 95 statements into 1 equivalence classes. [2025-02-08 14:58:48,015 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 95 of 95 statements. [2025-02-08 14:58:48,016 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:48,016 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:48,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:48,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:48,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [515694429] [2025-02-08 14:58:48,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [515694429] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:48,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:48,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-02-08 14:58:48,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [992698501] [2025-02-08 14:58:48,296 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:48,297 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:48,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:48,297 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-02-08 14:58:48,298 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-02-08 14:58:48,298 INFO L87 Difference]: Start difference. First operand 520 states and 717 transitions. cyclomatic complexity: 201 Second operand has 7 states, 7 states have (on average 13.571428571428571) internal successors, (95), 7 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:48,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:48,874 INFO L93 Difference]: Finished difference Result 527 states and 723 transitions. [2025-02-08 14:58:48,874 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 527 states and 723 transitions. [2025-02-08 14:58:48,876 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 518 [2025-02-08 14:58:48,878 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 527 states to 527 states and 723 transitions. [2025-02-08 14:58:48,878 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 527 [2025-02-08 14:58:48,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 527 [2025-02-08 14:58:48,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 527 states and 723 transitions. [2025-02-08 14:58:48,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:48,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 527 states and 723 transitions. [2025-02-08 14:58:48,880 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states and 723 transitions. [2025-02-08 14:58:48,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 520. [2025-02-08 14:58:48,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 520 states, 516 states have (on average 1.375968992248062) internal successors, (710), 515 states have internal predecessors, (710), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:48,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 716 transitions. [2025-02-08 14:58:48,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 520 states and 716 transitions. [2025-02-08 14:58:48,887 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-02-08 14:58:48,888 INFO L432 stractBuchiCegarLoop]: Abstraction has 520 states and 716 transitions. [2025-02-08 14:58:48,888 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-02-08 14:58:48,888 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 520 states and 716 transitions. [2025-02-08 14:58:48,889 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 511 [2025-02-08 14:58:48,889 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:48,889 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:48,890 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:48,890 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:48,890 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:48,890 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:48,891 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:48,891 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 20 times [2025-02-08 14:58:48,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:48,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609773855] [2025-02-08 14:58:48,891 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-02-08 14:58:48,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:48,898 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:48,901 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:48,901 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:48,901 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:48,901 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:48,904 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:48,906 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:48,906 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:48,906 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:48,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:48,915 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:48,915 INFO L85 PathProgramCache]: Analyzing trace with hash 440028075, now seen corresponding path program 1 times [2025-02-08 14:58:48,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:48,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2141491559] [2025-02-08 14:58:48,916 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:48,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:48,946 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:58:49,030 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:58:49,031 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:49,031 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:49,467 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:49,468 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:49,468 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2141491559] [2025-02-08 14:58:49,468 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2141491559] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:49,468 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:49,468 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-02-08 14:58:49,468 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [914756715] [2025-02-08 14:58:49,468 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:49,469 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:49,469 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:49,469 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-02-08 14:58:49,470 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2025-02-08 14:58:49,470 INFO L87 Difference]: Start difference. First operand 520 states and 716 transitions. cyclomatic complexity: 200 Second operand has 11 states, 11 states have (on average 8.727272727272727) internal successors, (96), 11 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:50,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:50,362 INFO L93 Difference]: Finished difference Result 536 states and 736 transitions. [2025-02-08 14:58:50,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 536 states and 736 transitions. [2025-02-08 14:58:50,364 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 527 [2025-02-08 14:58:50,365 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 536 states to 536 states and 736 transitions. [2025-02-08 14:58:50,366 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 536 [2025-02-08 14:58:50,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 536 [2025-02-08 14:58:50,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 536 states and 736 transitions. [2025-02-08 14:58:50,366 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:50,367 INFO L218 hiAutomatonCegarLoop]: Abstraction has 536 states and 736 transitions. [2025-02-08 14:58:50,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 536 states and 736 transitions. [2025-02-08 14:58:50,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 536 to 523. [2025-02-08 14:58:50,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 523 states, 519 states have (on average 1.3737957610789981) internal successors, (713), 518 states have internal predecessors, (713), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:50,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 523 states to 523 states and 719 transitions. [2025-02-08 14:58:50,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 523 states and 719 transitions. [2025-02-08 14:58:50,374 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:50,374 INFO L432 stractBuchiCegarLoop]: Abstraction has 523 states and 719 transitions. [2025-02-08 14:58:50,374 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-02-08 14:58:50,375 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 523 states and 719 transitions. [2025-02-08 14:58:50,376 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 514 [2025-02-08 14:58:50,376 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:50,376 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:50,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:50,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:50,377 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:50,377 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise44#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise45#1;assume main_#t~bitwise45#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:50,378 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:50,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 21 times [2025-02-08 14:58:50,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:50,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532780064] [2025-02-08 14:58:50,378 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-02-08 14:58:50,378 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:50,385 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:50,387 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:50,387 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-02-08 14:58:50,387 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:50,387 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:50,389 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:50,390 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:50,390 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:50,390 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:50,395 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:50,396 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:50,396 INFO L85 PathProgramCache]: Analyzing trace with hash -1068870374, now seen corresponding path program 1 times [2025-02-08 14:58:50,396 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:50,396 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1652658962] [2025-02-08 14:58:50,396 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:50,396 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:50,427 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:58:50,517 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:58:50,517 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:50,517 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:50,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:50,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:50,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1652658962] [2025-02-08 14:58:50,952 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1652658962] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:50,952 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:50,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-08 14:58:50,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [892275185] [2025-02-08 14:58:50,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:50,953 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:50,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:50,953 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-08 14:58:50,953 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-02-08 14:58:50,954 INFO L87 Difference]: Start difference. First operand 523 states and 719 transitions. cyclomatic complexity: 200 Second operand has 10 states, 10 states have (on average 9.6) internal successors, (96), 10 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:57,256 WARN L539 Checker$ProtectedHtc]: IncrementalHoareTripleChecker took 5.57s for a HTC check with result VALID. Formula has sorts [Bool, Int], hasArrays=false, hasNonlinArith=false, quantifiers [] [2025-02-08 14:58:57,744 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:57,744 INFO L93 Difference]: Finished difference Result 541 states and 741 transitions. [2025-02-08 14:58:57,744 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541 states and 741 transitions. [2025-02-08 14:58:57,746 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 532 [2025-02-08 14:58:57,748 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 541 states to 541 states and 741 transitions. [2025-02-08 14:58:57,748 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541 [2025-02-08 14:58:57,748 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541 [2025-02-08 14:58:57,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 541 states and 741 transitions. [2025-02-08 14:58:57,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:57,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 541 states and 741 transitions. [2025-02-08 14:58:57,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states and 741 transitions. [2025-02-08 14:58:57,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 528. [2025-02-08 14:58:57,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 528 states, 524 states have (on average 1.3721374045801527) internal successors, (719), 523 states have internal predecessors, (719), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:57,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528 states to 528 states and 725 transitions. [2025-02-08 14:58:57,757 INFO L240 hiAutomatonCegarLoop]: Abstraction has 528 states and 725 transitions. [2025-02-08 14:58:57,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:57,758 INFO L432 stractBuchiCegarLoop]: Abstraction has 528 states and 725 transitions. [2025-02-08 14:58:57,758 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-02-08 14:58:57,758 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 528 states and 725 transitions. [2025-02-08 14:58:57,759 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 519 [2025-02-08 14:58:57,761 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:57,761 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:57,762 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:57,762 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:57,762 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:57,762 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise43#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise44#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise45#1;assume main_#t~bitwise45#1 % 4294967296 <= main_~_ha_hashv~0#1 % 4294967296 + main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:57,763 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:57,763 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 22 times [2025-02-08 14:58:57,763 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:57,763 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [387890334] [2025-02-08 14:58:57,764 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-02-08 14:58:57,764 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:57,774 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 1 statements into 2 equivalence classes. [2025-02-08 14:58:57,775 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:57,775 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-02-08 14:58:57,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:57,775 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:57,778 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:57,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:57,779 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:57,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:57,783 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:57,784 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:57,785 INFO L85 PathProgramCache]: Analyzing trace with hash 2087658108, now seen corresponding path program 1 times [2025-02-08 14:58:57,785 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:57,785 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1384336108] [2025-02-08 14:58:57,785 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:57,785 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:57,817 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:58:57,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:58:57,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:57,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:58,351 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:58,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:58,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1384336108] [2025-02-08 14:58:58,351 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1384336108] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:58,351 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:58,351 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-02-08 14:58:58,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1862437175] [2025-02-08 14:58:58,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:58,352 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:58,352 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:58,352 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-02-08 14:58:58,352 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2025-02-08 14:58:58,352 INFO L87 Difference]: Start difference. First operand 528 states and 725 transitions. cyclomatic complexity: 201 Second operand has 10 states, 10 states have (on average 9.6) internal successors, (96), 10 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:58:59,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:58:59,426 INFO L93 Difference]: Finished difference Result 535 states and 735 transitions. [2025-02-08 14:58:59,426 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 535 states and 735 transitions. [2025-02-08 14:58:59,428 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 526 [2025-02-08 14:58:59,430 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 535 states to 535 states and 735 transitions. [2025-02-08 14:58:59,430 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 535 [2025-02-08 14:58:59,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 535 [2025-02-08 14:58:59,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 535 states and 735 transitions. [2025-02-08 14:58:59,431 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:58:59,431 INFO L218 hiAutomatonCegarLoop]: Abstraction has 535 states and 735 transitions. [2025-02-08 14:58:59,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 535 states and 735 transitions. [2025-02-08 14:58:59,436 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 535 to 528. [2025-02-08 14:58:59,436 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 528 states, 524 states have (on average 1.3721374045801527) internal successors, (719), 523 states have internal predecessors, (719), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:58:59,437 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 528 states to 528 states and 725 transitions. [2025-02-08 14:58:59,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 528 states and 725 transitions. [2025-02-08 14:58:59,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:58:59,438 INFO L432 stractBuchiCegarLoop]: Abstraction has 528 states and 725 transitions. [2025-02-08 14:58:59,438 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-02-08 14:58:59,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 528 states and 725 transitions. [2025-02-08 14:58:59,440 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 519 [2025-02-08 14:58:59,440 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:58:59,440 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:58:59,441 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:58:59,442 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:58:59,442 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:58:59,442 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise43#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise45#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise46#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise47#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:58:59,443 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:59,443 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 23 times [2025-02-08 14:58:59,443 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:59,443 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1959861700] [2025-02-08 14:58:59,443 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-02-08 14:58:59,443 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:59,451 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:59,452 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:59,452 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-02-08 14:58:59,452 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:59,452 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:58:59,457 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:58:59,461 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:58:59,462 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:59,462 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:58:59,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:58:59,468 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:58:59,468 INFO L85 PathProgramCache]: Analyzing trace with hash -429526052, now seen corresponding path program 1 times [2025-02-08 14:58:59,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:58:59,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670019349] [2025-02-08 14:58:59,469 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:58:59,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:58:59,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:58:59,587 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:58:59,587 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:58:59,587 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:58:59,780 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-02-08 14:58:59,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-02-08 14:58:59,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1670019349] [2025-02-08 14:58:59,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1670019349] provided 1 perfect and 0 imperfect interpolant sequences [2025-02-08 14:58:59,780 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-02-08 14:58:59,780 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-02-08 14:58:59,780 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148882601] [2025-02-08 14:58:59,780 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-02-08 14:58:59,781 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-02-08 14:58:59,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-02-08 14:58:59,782 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-02-08 14:58:59,782 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-02-08 14:58:59,782 INFO L87 Difference]: Start difference. First operand 528 states and 725 transitions. cyclomatic complexity: 201 Second operand has 9 states, 9 states have (on average 10.666666666666666) internal successors, (96), 9 states have internal predecessors, (96), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-02-08 14:59:00,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-02-08 14:59:00,613 INFO L93 Difference]: Finished difference Result 573 states and 789 transitions. [2025-02-08 14:59:00,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 573 states and 789 transitions. [2025-02-08 14:59:00,614 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 564 [2025-02-08 14:59:00,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 573 states to 573 states and 789 transitions. [2025-02-08 14:59:00,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 573 [2025-02-08 14:59:00,616 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 573 [2025-02-08 14:59:00,616 INFO L73 IsDeterministic]: Start isDeterministic. Operand 573 states and 789 transitions. [2025-02-08 14:59:00,617 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-02-08 14:59:00,617 INFO L218 hiAutomatonCegarLoop]: Abstraction has 573 states and 789 transitions. [2025-02-08 14:59:00,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 573 states and 789 transitions. [2025-02-08 14:59:00,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 573 to 540. [2025-02-08 14:59:00,622 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 540 states, 536 states have (on average 1.3694029850746268) internal successors, (734), 535 states have internal predecessors, (734), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-02-08 14:59:00,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 540 states to 540 states and 740 transitions. [2025-02-08 14:59:00,624 INFO L240 hiAutomatonCegarLoop]: Abstraction has 540 states and 740 transitions. [2025-02-08 14:59:00,624 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-02-08 14:59:00,625 INFO L432 stractBuchiCegarLoop]: Abstraction has 540 states and 740 transitions. [2025-02-08 14:59:00,625 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-02-08 14:59:00,625 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 540 states and 740 transitions. [2025-02-08 14:59:00,626 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 531 [2025-02-08 14:59:00,626 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-02-08 14:59:00,626 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-02-08 14:59:00,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1] [2025-02-08 14:59:00,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-02-08 14:59:00,629 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);~count_int~0 := 0;assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem5#1, main_#t~malloc6#1.base, main_#t~malloc6#1.offset, main_#t~mem7#1, main_#t~mem8#1, main_#t~mem9#1, main_#t~mem11#1, main_#t~mem10#1, main_#t~mem12#1, main_#t~mem13#1, main_#t~mem15#1, main_#t~mem14#1, main_#t~mem16#1, main_#t~mem17#1, main_#t~mem19#1, main_#t~mem18#1, main_#t~mem20#1, main_#t~mem21#1, main_#t~bitwise22#1, main_#t~bitwise23#1, main_#t~bitwise24#1, main_#t~bitwise25#1, main_#t~bitwise26#1, main_#t~bitwise27#1, main_#t~bitwise28#1, main_#t~bitwise29#1, main_#t~bitwise30#1, main_#t~switch31#1, main_#t~mem32#1, main_#t~mem33#1, main_#t~mem34#1, main_#t~mem35#1, main_#t~mem36#1, main_#t~mem37#1, main_#t~mem38#1, main_#t~mem39#1, main_#t~mem40#1, main_#t~mem41#1, main_#t~mem42#1, main_#t~bitwise43#1, main_#t~bitwise44#1, main_#t~bitwise45#1, main_#t~bitwise46#1, main_#t~bitwise47#1, main_#t~bitwise48#1, main_#t~bitwise49#1, main_#t~bitwise50#1, main_#t~bitwise51#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~malloc52#1.base, main_#t~malloc52#1.offset, main_#t~mem53#1.base, main_#t~mem53#1.offset, main_#t~mem54#1.base, main_#t~mem54#1.offset, main_#t~memset~res55#1.base, main_#t~memset~res55#1.offset, main_#t~mem56#1.base, main_#t~mem56#1.offset, main_#t~mem57#1.base, main_#t~mem57#1.offset, main_#t~mem58#1.base, main_#t~mem58#1.offset, main_#t~mem59#1.base, main_#t~mem59#1.offset, main_#t~mem60#1.base, main_#t~mem60#1.offset, main_#t~malloc61#1.base, main_#t~malloc61#1.offset, main_#t~mem62#1.base, main_#t~mem62#1.offset, main_#t~mem63#1.base, main_#t~mem63#1.offset, main_#t~mem64#1.base, main_#t~mem64#1.offset, main_#t~mem65#1.base, main_#t~mem65#1.offset, main_#t~mem66#1.base, main_#t~mem66#1.offset, main_#t~mem67#1.base, main_#t~mem67#1.offset, main_#t~memset~res68#1.base, main_#t~memset~res68#1.offset, main_#t~mem69#1.base, main_#t~mem69#1.offset, main_#t~mem70#1.base, main_#t~mem70#1.offset, main_#t~mem71#1.base, main_#t~mem71#1.offset, main_#t~mem72#1.base, main_#t~mem72#1.offset, main_#t~mem73#1, main_#t~mem74#1.base, main_#t~mem74#1.offset, main_#t~mem75#1.base, main_#t~mem75#1.offset, main_#t~mem76#1.base, main_#t~mem76#1.offset, main_#t~mem77#1.base, main_#t~mem77#1.offset, main_#t~mem78#1, main_#t~post79#1, main_#t~mem80#1.base, main_#t~mem80#1.offset, main_#t~mem81#1, main_#t~bitwise82#1, main_#t~mem83#1.base, main_#t~mem83#1.offset, main_#t~mem84#1.base, main_#t~mem84#1.offset, main_#t~mem85#1, main_#t~post86#1, main_#t~mem87#1.base, main_#t~mem87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem91#1, main_#t~mem90#1, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1, main_#t~short94#1, main_#t~mem95#1.base, main_#t~mem95#1.offset, main_#t~mem96#1, main_#t~malloc97#1.base, main_#t~malloc97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1, main_#t~memset~res100#1.base, main_#t~memset~res100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem105#1, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1, main_#t~bitwise106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem110#1, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1, main_#t~bitwise111#1, main_#t~mem112#1.base, main_#t~mem112#1.offset, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~mem115#1.base, main_#t~mem115#1.offset, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1.base, main_#t~mem118#1.offset, main_#t~mem121#1, main_#t~mem119#1.base, main_#t~mem119#1.offset, main_#t~mem120#1, main_#t~bitwise122#1, main_#t~mem123#1, main_#t~pre124#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~mem127#1.base, main_#t~mem127#1.offset, main_#t~mem128#1, main_#t~post129#1, main_#t~mem133#1, main_#t~mem131#1, main_#t~mem130#1.base, main_#t~mem130#1.offset, main_#t~mem132#1, main_#t~mem134#1, main_#t~post135#1, main_#t~mem136#1.base, main_#t~mem136#1.offset, main_#t~mem137#1.base, main_#t~mem137#1.offset, main_#t~mem138#1.base, main_#t~mem138#1.offset, main_#t~post139#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1.base, main_#t~mem141#1.offset, main_#t~mem142#1.base, main_#t~mem142#1.offset, main_#t~mem143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1, main_#t~post146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem152#1, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem151#1, main_#t~ite155#1, main_#t~mem153#1.base, main_#t~mem153#1.offset, main_#t~mem154#1, main_#t~mem156#1.base, main_#t~mem156#1.offset, main_#t~mem157#1, main_#t~mem158#1.base, main_#t~mem158#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~mem161#1, main_#t~post162#1, main_#t~mem163#1, main_#t~mem165#1, main_#t~mem164#1, main_#t~mem166#1, main_#t~mem167#1, main_#t~mem169#1, main_#t~mem168#1, main_#t~mem170#1, main_#t~mem171#1, main_#t~mem173#1, main_#t~mem172#1, main_#t~mem174#1, main_#t~mem175#1, main_#t~bitwise176#1, main_#t~bitwise177#1, main_#t~bitwise178#1, main_#t~bitwise179#1, main_#t~bitwise180#1, main_#t~bitwise181#1, main_#t~bitwise182#1, main_#t~bitwise183#1, main_#t~bitwise184#1, main_#t~switch185#1, main_#t~mem186#1, main_#t~mem187#1, main_#t~mem188#1, main_#t~mem189#1, main_#t~mem190#1, main_#t~mem191#1, main_#t~mem192#1, main_#t~mem193#1, main_#t~mem194#1, main_#t~mem195#1, main_#t~mem196#1, main_#t~bitwise197#1, main_#t~bitwise198#1, main_#t~bitwise199#1, main_#t~bitwise200#1, main_#t~bitwise201#1, main_#t~bitwise202#1, main_#t~bitwise203#1, main_#t~bitwise204#1, main_#t~bitwise205#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem206#1.base, main_#t~mem206#1.offset, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~mem209#1.base, main_#t~mem209#1.offset, main_#t~mem210#1.base, main_#t~mem210#1.offset, main_#t~mem211#1.base, main_#t~mem211#1.offset, main_#t~mem212#1.base, main_#t~mem212#1.offset, main_#t~mem213#1.base, main_#t~mem213#1.offset, main_#t~mem214#1.base, main_#t~mem214#1.offset, main_#t~mem215#1.base, main_#t~mem215#1.offset, main_#t~mem216#1, main_#t~mem217#1, main_#t~mem218#1, main_#t~short219#1, main_#t~mem220#1.base, main_#t~mem220#1.offset, main_#t~nondet221#1, main_#t~mem222#1.base, main_#t~mem222#1.offset, main_#t~mem223#1.base, main_#t~mem223#1.offset, main_#t~mem224#1.base, main_#t~mem224#1.offset, main_#t~mem225#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem226#1.base, main_#t~mem226#1.offset, main_#t~mem227#1.base, main_#t~mem227#1.offset, main_#t~short228#1, main_#t~mem229#1.base, main_#t~mem229#1.offset, main_#t~mem230#1.base, main_#t~mem230#1.offset, main_#t~mem231#1.base, main_#t~mem231#1.offset, main_#t~mem232#1.base, main_#t~mem232#1.offset, main_#t~mem233#1.base, main_#t~mem233#1.offset, main_#t~mem234#1.base, main_#t~mem234#1.offset, main_#t~mem235#1.base, main_#t~mem235#1.offset, main_#t~mem236#1.base, main_#t~mem236#1.offset, main_#t~mem237#1, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1.base, main_#t~mem239#1.offset, main_#t~mem240#1.base, main_#t~mem240#1.offset, main_#t~mem241#1, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1, main_#t~mem248#1.base, main_#t~mem248#1.offset, main_#t~mem251#1, main_#t~mem249#1.base, main_#t~mem249#1.offset, main_#t~mem250#1, main_#t~bitwise252#1, main_#t~mem253#1.base, main_#t~mem253#1.offset, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1, main_#t~post256#1, main_#t~mem257#1.base, main_#t~mem257#1.offset, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~mem260#1.base, main_#t~mem260#1.offset, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1.base, main_#t~mem264#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1, main_#t~post267#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1, main_#t~mem270#1, main_#t~ite272#1.base, main_#t~ite272#1.offset, main_#t~mem271#1.base, main_#t~mem271#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~short275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1.base, main_#t~mem281#1.offset, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~mem285#1.base, main_#t~mem285#1.offset, main_#t~mem286#1.base, main_#t~mem286#1.offset, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1, main_#t~mem289#1.base, main_#t~mem289#1.offset, main_#t~mem290#1.base, main_#t~mem290#1.offset, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem298#1, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1, main_#t~bitwise299#1, main_#t~mem300#1.base, main_#t~mem300#1.offset, main_#t~mem301#1.base, main_#t~mem301#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem306#1.base, main_#t~mem306#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~mem309#1.base, main_#t~mem309#1.offset, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~post314#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite316#1.base, main_#t~ite316#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#2(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-02-08 14:59:00,630 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem5#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem5#1 < 10;havoc main_#t~mem5#1;call main_#t~malloc6#1.base, main_#t~malloc6#1.offset := #Ultimate.allocOnHeap(40);main_~user~0#1.base, main_~user~0#1.offset := main_#t~malloc6#1.base, main_#t~malloc6#1.offset;havoc main_#t~malloc6#1.base, main_#t~malloc6#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem7#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem7#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem7#1;call main_#t~mem8#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem9#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem8#1 * main_#t~mem9#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem8#1;havoc main_#t~mem9#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch31#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch31#1;" "main_#t~switch31#1 := main_#t~switch31#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem39#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem39#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem40#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem40#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem41#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem41#1 % 256 % 4294967296);" "main_#t~switch31#1 := main_#t~switch31#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch31#1;call main_#t~mem42#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem42#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem42#1 % 256 % 4294967296 else main_#t~mem42#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;havoc main_#t~switch31#1;havoc main_#t~mem32#1;havoc main_#t~mem33#1;havoc main_#t~mem34#1;havoc main_#t~mem35#1;havoc main_#t~mem36#1;havoc main_#t~mem37#1;havoc main_#t~mem38#1;havoc main_#t~mem39#1;havoc main_#t~mem40#1;havoc main_#t~mem41#1;havoc main_#t~mem42#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise43#1;assume main_#t~bitwise43#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise43#1;havoc main_#t~bitwise43#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise44#1;assume main_#t~bitwise44#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise44#1;havoc main_#t~bitwise44#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise45#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise45#1;havoc main_#t~bitwise45#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise46#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise46#1;havoc main_#t~bitwise46#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise47#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise47#1;havoc main_#t~bitwise47#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise48#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise48#1;havoc main_#t~bitwise48#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise49#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise49#1;havoc main_#t~bitwise49#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise50#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise50#1;havoc main_#t~bitwise50#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise51#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise51#1;havoc main_#t~bitwise51#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem69#1.base, main_#t~mem69#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem69#1.base, main_#t~mem69#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem69#1.base, main_#t~mem69#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem70#1.base, main_#t~mem70#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem71#1.base, main_#t~mem71#1.offset := read~$Pointer$#0(main_#t~mem70#1.base, 16 + main_#t~mem70#1.offset, 4);call main_#t~mem72#1.base, main_#t~mem72#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem73#1 := read~int#0(main_#t~mem72#1.base, 20 + main_#t~mem72#1.offset, 4);call write~$Pointer$#0(main_#t~mem71#1.base, main_#t~mem71#1.offset - main_#t~mem73#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem70#1.base, main_#t~mem70#1.offset;havoc main_#t~mem71#1.base, main_#t~mem71#1.offset;havoc main_#t~mem72#1.base, main_#t~mem72#1.offset;havoc main_#t~mem73#1;call main_#t~mem74#1.base, main_#t~mem74#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem75#1.base, main_#t~mem75#1.offset := read~$Pointer$#0(main_#t~mem74#1.base, 16 + main_#t~mem74#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem75#1.base, 8 + main_#t~mem75#1.offset, 4);havoc main_#t~mem74#1.base, main_#t~mem74#1.offset;havoc main_#t~mem75#1.base, main_#t~mem75#1.offset;call main_#t~mem76#1.base, main_#t~mem76#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem76#1.base, 16 + main_#t~mem76#1.offset, 4);havoc main_#t~mem76#1.base, main_#t~mem76#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem77#1.base, main_#t~mem77#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem78#1 := read~int#0(main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);main_#t~post79#1 := main_#t~mem78#1;call write~int#0(1 + main_#t~post79#1, main_#t~mem77#1.base, 12 + main_#t~mem77#1.offset, 4);havoc main_#t~mem77#1.base, main_#t~mem77#1.offset;havoc main_#t~mem78#1;havoc main_#t~post79#1;" "assume true;call main_#t~mem80#1.base, main_#t~mem80#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem81#1 := read~int#0(main_#t~mem80#1.base, 4 + main_#t~mem80#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem81#1 - 1) % 4294967296;main_#t~bitwise82#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise82#1;havoc main_#t~mem80#1.base, main_#t~mem80#1.offset;havoc main_#t~mem81#1;havoc main_#t~bitwise82#1;" "assume !false;" "assume true;call main_#t~mem83#1.base, main_#t~mem83#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem84#1.base, main_#t~mem84#1.offset := read~$Pointer$#0(main_#t~mem83#1.base, main_#t~mem83#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem84#1.base, main_#t~mem84#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem83#1.base, main_#t~mem83#1.offset;havoc main_#t~mem84#1.base, main_#t~mem84#1.offset;call main_#t~mem85#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post86#1 := main_#t~mem85#1;call write~int#0(1 + main_#t~post86#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem85#1;havoc main_#t~post86#1;call main_#t~mem87#1.base, main_#t~mem87#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem87#1.base, main_#t~mem87#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem87#1.base, main_#t~mem87#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem88#1.base, main_#t~mem88#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume !(main_#t~mem88#1.base != 0 || main_#t~mem88#1.offset != 0);havoc main_#t~mem88#1.base, main_#t~mem88#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem91#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem90#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short94#1 := main_#t~mem91#1 % 4294967296 >= 10 * (1 + main_#t~mem90#1) % 4294967296;" "assume main_#t~short94#1;call main_#t~mem92#1.base, main_#t~mem92#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem93#1 := read~int#0(main_#t~mem92#1.base, 36 + main_#t~mem92#1.offset, 4);main_#t~short94#1 := 0 == main_#t~mem93#1 % 4294967296;" "assume !main_#t~short94#1;havoc main_#t~mem91#1;havoc main_#t~mem90#1;havoc main_#t~mem92#1.base, main_#t~mem92#1.offset;havoc main_#t~mem93#1;havoc main_#t~short94#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem159#1.base, main_#t~mem159#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem160#1 := read~int#0(main_#t~mem159#1.base, 12 + main_#t~mem159#1.offset, 4);assume { :begin_inline_test_int } true;test_int_#in~a#1 := (if main_#t~mem160#1 % 4294967296 % 4294967296 <= 2147483647 then main_#t~mem160#1 % 4294967296 % 4294967296 else main_#t~mem160#1 % 4294967296 % 4294967296 - 4294967296);havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;test_int_~a#1 := test_int_#in~a#1;test_int_#t~post3#1 := ~count_int~0;~count_int~0 := 1 + test_int_#t~post3#1;test_int_#t~switch4#1 := 0 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 1 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 2 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 3 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 4 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 5 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 6 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 7 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 8 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 9 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 10 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 11 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 12 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 13 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;test_int_#t~switch4#1 := test_int_#t~switch4#1 || 14 == test_int_#t~post3#1;" "assume !test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1;havoc test_int_#t~switch4#1;havoc test_int_#t~post3#1, test_int_#t~switch4#1, test_int_~a#1;havoc test_int_#in~a#1;assume { :end_inline_test_int } true;havoc main_#t~mem159#1.base, main_#t~mem159#1.offset;havoc main_#t~mem160#1;call main_#t~mem161#1 := read~int#2(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post162#1 := main_#t~mem161#1;call write~int#2(1 + main_#t~post162#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem161#1;havoc main_#t~post162#1;" [2025-02-08 14:59:00,630 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:59:00,630 INFO L85 PathProgramCache]: Analyzing trace with hash 1094, now seen corresponding path program 24 times [2025-02-08 14:59:00,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:59:00,630 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850185354] [2025-02-08 14:59:00,630 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-02-08 14:59:00,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:59:00,639 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:59:00,642 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:59:00,642 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-02-08 14:59:00,642 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:59:00,642 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-02-08 14:59:00,645 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 1 statements into 1 equivalence classes. [2025-02-08 14:59:00,645 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 1 of 1 statements. [2025-02-08 14:59:00,646 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:59:00,646 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-02-08 14:59:00,650 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-02-08 14:59:00,651 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-02-08 14:59:00,651 INFO L85 PathProgramCache]: Analyzing trace with hash -689850901, now seen corresponding path program 1 times [2025-02-08 14:59:00,651 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-02-08 14:59:00,651 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [649436922] [2025-02-08 14:59:00,651 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-02-08 14:59:00,651 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-02-08 14:59:00,683 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 96 statements into 1 equivalence classes. [2025-02-08 14:59:00,772 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 96 of 96 statements. [2025-02-08 14:59:00,772 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-02-08 14:59:00,772 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-02-08 14:59:13,156 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)