./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/termination-15/array16_alloca_fixed.i --full-output --architecture 64bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/termination-15/array16_alloca_fixed.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 64bit --witnessprinter.graph.data.programhash 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 15:42:00,169 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 15:42:00,226 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-64bit-Automizer_Default.epf [2025-03-04 15:42:00,231 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 15:42:00,231 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 15:42:00,231 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 15:42:00,252 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 15:42:00,254 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 15:42:00,254 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 15:42:00,254 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 15:42:00,255 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 15:42:00,255 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 15:42:00,255 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 15:42:00,255 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 15:42:00,255 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 15:42:00,255 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 15:42:00,256 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 15:42:00,256 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 15:42:00,257 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 15:42:00,257 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 15:42:00,258 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 15:42:00,258 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 15:42:00,258 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 15:42:00,258 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 64bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 2a580f3a42bca030605af1bbd4c6a77550e46d88a6197c1e34cf45bb050eadef [2025-03-04 15:42:00,495 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 15:42:00,501 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 15:42:00,504 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 15:42:00,504 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 15:42:00,505 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 15:42:00,506 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2025-03-04 15:42:01,695 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eb25b9241/0f7ba331686a4e39b0852d4f66447d17/FLAG0af425f78 [2025-03-04 15:42:01,941 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 15:42:01,941 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/termination-15/array16_alloca_fixed.i [2025-03-04 15:42:01,951 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eb25b9241/0f7ba331686a4e39b0852d4f66447d17/FLAG0af425f78 [2025-03-04 15:42:02,239 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/eb25b9241/0f7ba331686a4e39b0852d4f66447d17 [2025-03-04 15:42:02,241 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 15:42:02,242 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 15:42:02,243 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 15:42:02,243 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 15:42:02,246 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 15:42:02,247 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,247 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2e08c711 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02, skipping insertion in model container [2025-03-04 15:42:02,247 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,266 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 15:42:02,417 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:42:02,424 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 15:42:02,454 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 15:42:02,476 INFO L204 MainTranslator]: Completed translation [2025-03-04 15:42:02,477 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02 WrapperNode [2025-03-04 15:42:02,477 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 15:42:02,477 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 15:42:02,478 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 15:42:02,478 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 15:42:02,481 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,487 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,500 INFO L138 Inliner]: procedures = 151, calls = 10, calls flagged for inlining = 2, calls inlined = 2, statements flattened = 49 [2025-03-04 15:42:02,501 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 15:42:02,501 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 15:42:02,502 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 15:42:02,502 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 15:42:02,506 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,506 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,507 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,513 INFO L175 MemorySlicer]: Split 4 memory accesses to 1 slices as follows [4]. 100 percent of accesses are in the largest equivalence class. The 0 initializations are split as follows [0]. The 2 writes are split as follows [2]. [2025-03-04 15:42:02,513 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,513 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,515 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,516 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,516 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,517 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,518 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 15:42:02,518 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 15:42:02,518 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 15:42:02,518 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 15:42:02,519 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (1/1) ... [2025-03-04 15:42:02,522 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:02,531 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:02,543 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:02,545 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 15:42:02,564 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-04 15:42:02,564 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-04 15:42:02,565 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-04 15:42:02,565 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 15:42:02,565 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 15:42:02,565 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 15:42:02,615 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 15:42:02,616 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 15:42:02,717 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L368: call ULTIMATE.dealloc(main_#t~malloc206#1.base, main_#t~malloc206#1.offset);havoc main_#t~malloc206#1.base, main_#t~malloc206#1.offset; [2025-03-04 15:42:02,724 INFO L? ?]: Removed 8 outVars from TransFormulas that were not future-live. [2025-03-04 15:42:02,724 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 15:42:02,730 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 15:42:02,730 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 15:42:02,731 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:42:02 BoogieIcfgContainer [2025-03-04 15:42:02,731 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 15:42:02,731 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 15:42:02,731 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 15:42:02,736 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 15:42:02,736 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:42:02,736 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 03:42:02" (1/3) ... [2025-03-04 15:42:02,738 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1578d8c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:42:02, skipping insertion in model container [2025-03-04 15:42:02,738 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:42:02,738 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 03:42:02" (2/3) ... [2025-03-04 15:42:02,739 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@1578d8c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 03:42:02, skipping insertion in model container [2025-03-04 15:42:02,739 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 15:42:02,739 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:42:02" (3/3) ... [2025-03-04 15:42:02,740 INFO L363 chiAutomizerObserver]: Analyzing ICFG array16_alloca_fixed.i [2025-03-04 15:42:02,781 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 15:42:02,781 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 15:42:02,782 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 15:42:02,782 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 15:42:02,782 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 15:42:02,783 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 15:42:02,783 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 15:42:02,783 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 15:42:02,786 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:02,799 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2025-03-04 15:42:02,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:02,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:02,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-03-04 15:42:02,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:42:02,803 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 15:42:02,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:02,805 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5 [2025-03-04 15:42:02,805 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:02,805 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:02,805 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1] [2025-03-04 15:42:02,805 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 15:42:02,808 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" [2025-03-04 15:42:02,810 INFO L754 eck$LassoCheckResult]: Loop: "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" [2025-03-04 15:42:02,814 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:02,814 INFO L85 PathProgramCache]: Analyzing trace with hash 48637714, now seen corresponding path program 1 times [2025-03-04 15:42:02,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:02,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844893846] [2025-03-04 15:42:02,820 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:02,820 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:02,862 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:42:02,880 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:42:02,881 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,881 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,881 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:02,884 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:42:02,887 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:42:02,887 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,887 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,899 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:02,901 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:02,901 INFO L85 PathProgramCache]: Analyzing trace with hash 40649, now seen corresponding path program 1 times [2025-03-04 15:42:02,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:02,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [147841181] [2025-03-04 15:42:02,902 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:02,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:02,910 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:42:02,921 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:42:02,922 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,922 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,923 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:02,926 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:42:02,934 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:42:02,935 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,935 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,937 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:02,940 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:02,940 INFO L85 PathProgramCache]: Analyzing trace with hash 1562169880, now seen corresponding path program 1 times [2025-03-04 15:42:02,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:02,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [505184528] [2025-03-04 15:42:02,940 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:02,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:02,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 15:42:02,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 15:42:02,975 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,975 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,975 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:02,979 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 8 statements into 1 equivalence classes. [2025-03-04 15:42:02,991 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 8 of 8 statements. [2025-03-04 15:42:02,994 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:02,995 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:02,997 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:03,238 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 15:42:03,239 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 15:42:03,239 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 15:42:03,239 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 15:42:03,239 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 15:42:03,239 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:03,239 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 15:42:03,239 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 15:42:03,242 INFO L132 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration1_Lasso [2025-03-04 15:42:03,242 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 15:42:03,242 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 15:42:03,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,260 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,388 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,390 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,392 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,397 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,399 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,401 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:03,579 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 15:42:03,581 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 15:42:03,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:03,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:03,584 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:03,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-04 15:42:03,586 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:42:03,598 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:42:03,598 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:42:03,598 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:42:03,598 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:42:03,599 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:42:03,601 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:42:03,601 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:42:03,603 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:42:03,608 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-04 15:42:03,608 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:03,608 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:03,611 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:03,612 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-04 15:42:03,613 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:42:03,623 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:42:03,624 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:42:03,624 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:42:03,624 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:42:03,627 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:42:03,627 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:42:03,630 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:42:03,637 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-04 15:42:03,637 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:03,637 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:03,639 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:03,641 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-04 15:42:03,642 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:42:03,652 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:42:03,652 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:42:03,652 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:42:03,652 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:42:03,664 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:42:03,664 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:42:03,674 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 15:42:03,701 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2025-03-04 15:42:03,703 INFO L444 ModelExtractionUtils]: 3 out of 19 variables were initially zero. Simplification set additionally 12 variables to zero. [2025-03-04 15:42:03,704 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:03,704 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:03,707 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:03,709 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-04 15:42:03,710 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 15:42:03,722 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-04 15:42:03,722 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 15:42:03,723 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~arr~0#1.offset, v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1, ULTIMATE.start_main_~i~0#1) = -1*ULTIMATE.start_main_~arr~0#1.offset + 1*v_rep(select #length ULTIMATE.start_main_~arr~0#1.base)_1 - 4*ULTIMATE.start_main_~i~0#1 Supporting invariants [] [2025-03-04 15:42:03,729 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:03,740 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2025-03-04 15:42:03,749 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: #length [2025-03-04 15:42:03,749 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] [2025-03-04 15:42:03,750 WARN L970 BoogieBacktranslator]: Unfinished Backtranslation: Unknown variable: ~arr~0!offset [2025-03-04 15:42:03,762 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:03,772 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 5 statements into 1 equivalence classes. [2025-03-04 15:42:03,777 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 5 of 5 statements. [2025-03-04 15:42:03,778 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:03,778 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:03,779 INFO L256 TraceCheckSpWp]: Trace formula consists of 26 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 15:42:03,779 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:03,800 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 15:42:03,805 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 15:42:03,805 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:03,805 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:03,806 INFO L256 TraceCheckSpWp]: Trace formula consists of 24 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 15:42:03,806 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:03,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:03,844 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-03-04 15:42:03,846 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:03,878 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand has 13 states, 12 states have (on average 1.5) internal successors, (18), 12 states have internal predecessors, (18), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0). Second operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 20 states and 28 transitions. Complement of second has 5 states. [2025-03-04 15:42:03,880 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 15:42:03,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 2.6666666666666665) internal successors, (8), 3 states have internal predecessors, (8), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:03,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2025-03-04 15:42:03,891 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 5 letters. Loop has 3 letters. [2025-03-04 15:42:03,892 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:03,892 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 8 letters. Loop has 3 letters. [2025-03-04 15:42:03,893 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:03,893 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 5 letters. Loop has 6 letters. [2025-03-04 15:42:03,893 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:03,893 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20 states and 28 transitions. [2025-03-04 15:42:03,894 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:03,896 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20 states to 12 states and 17 transitions. [2025-03-04 15:42:03,896 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2025-03-04 15:42:03,897 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9 [2025-03-04 15:42:03,897 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12 states and 17 transitions. [2025-03-04 15:42:03,897 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:42:03,897 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12 states and 17 transitions. [2025-03-04 15:42:03,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states and 17 transitions. [2025-03-04 15:42:03,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 11. [2025-03-04 15:42:03,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.4545454545454546) internal successors, (16), 10 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:03,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 16 transitions. [2025-03-04 15:42:03,915 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 16 transitions. [2025-03-04 15:42:03,915 INFO L432 stractBuchiCegarLoop]: Abstraction has 11 states and 16 transitions. [2025-03-04 15:42:03,915 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 15:42:03,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 16 transitions. [2025-03-04 15:42:03,915 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:03,916 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:03,916 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:03,916 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1] [2025-03-04 15:42:03,916 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:03,917 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" [2025-03-04 15:42:03,917 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:03,917 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:03,917 INFO L85 PathProgramCache]: Analyzing trace with hash 1507769141, now seen corresponding path program 1 times [2025-03-04 15:42:03,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:03,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [740824161] [2025-03-04 15:42:03,917 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:03,918 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:03,923 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 6 statements into 1 equivalence classes. [2025-03-04 15:42:03,929 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 6 of 6 statements. [2025-03-04 15:42:03,929 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:03,929 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:03,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:03,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:03,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [740824161] [2025-03-04 15:42:03,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [740824161] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:42:03,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 15:42:03,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 15:42:03,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1636952416] [2025-03-04 15:42:03,980 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:42:03,981 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:03,981 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:03,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 1 times [2025-03-04 15:42:03,981 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:03,981 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1725849486] [2025-03-04 15:42:03,981 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:03,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:03,984 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:03,986 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:03,987 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:03,987 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:03,987 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:03,987 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:03,990 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:03,990 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:03,990 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:03,995 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:04,039 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:04,040 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 15:42:04,040 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-03-04 15:42:04,041 INFO L87 Difference]: Start difference. First operand 11 states and 16 transitions. cyclomatic complexity: 7 Second operand has 4 states, 3 states have (on average 2.0) internal successors, (6), 4 states have internal predecessors, (6), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:04,059 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:04,060 INFO L93 Difference]: Finished difference Result 13 states and 18 transitions. [2025-03-04 15:42:04,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13 states and 18 transitions. [2025-03-04 15:42:04,060 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:04,060 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13 states to 13 states and 18 transitions. [2025-03-04 15:42:04,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8 [2025-03-04 15:42:04,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8 [2025-03-04 15:42:04,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13 states and 18 transitions. [2025-03-04 15:42:04,061 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:42:04,061 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13 states and 18 transitions. [2025-03-04 15:42:04,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states and 18 transitions. [2025-03-04 15:42:04,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 11. [2025-03-04 15:42:04,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11 states, 11 states have (on average 1.3636363636363635) internal successors, (15), 10 states have internal predecessors, (15), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:04,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11 states to 11 states and 15 transitions. [2025-03-04 15:42:04,062 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11 states and 15 transitions. [2025-03-04 15:42:04,062 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 15:42:04,063 INFO L432 stractBuchiCegarLoop]: Abstraction has 11 states and 15 transitions. [2025-03-04 15:42:04,063 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 15:42:04,063 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11 states and 15 transitions. [2025-03-04 15:42:04,063 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:04,063 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:04,063 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:04,063 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:04,063 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:04,064 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" [2025-03-04 15:42:04,064 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:04,064 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:04,064 INFO L85 PathProgramCache]: Analyzing trace with hash 1182626992, now seen corresponding path program 1 times [2025-03-04 15:42:04,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:04,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1660573127] [2025-03-04 15:42:04,064 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:04,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:04,068 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 15:42:04,074 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 15:42:04,074 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,074 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,074 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:04,076 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 15:42:04,081 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 15:42:04,081 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,081 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,083 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:04,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:04,083 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 2 times [2025-03-04 15:42:04,083 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:04,083 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [853781199] [2025-03-04 15:42:04,084 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:04,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:04,089 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:04,094 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:04,096 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:04,096 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,096 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:04,098 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:04,101 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:04,103 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,103 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,104 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:04,105 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:04,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1661793938, now seen corresponding path program 1 times [2025-03-04 15:42:04,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:04,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2101663051] [2025-03-04 15:42:04,106 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:04,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:04,111 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 15:42:04,129 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 15:42:04,130 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,130 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:04,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 15:42:04,148 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 15:42:04,149 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:04,151 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:04,241 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-04 15:42:04,357 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 15:42:04,358 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 15:42:04,358 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 15:42:04,358 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 15:42:04,358 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 15:42:04,358 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:04,358 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 15:42:04,358 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 15:42:04,358 INFO L132 ssoRankerPreferences]: Filename of dumped script: array16_alloca_fixed.i_Iteration3_Lasso [2025-03-04 15:42:04,358 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 15:42:04,358 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 15:42:04,360 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,448 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,452 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,453 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,454 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,455 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,457 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,458 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 15:42:04,617 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 15:42:04,618 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 15:42:04,618 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:04,618 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:04,621 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:04,622 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-04 15:42:04,623 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:42:04,634 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:42:04,634 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 15:42:04,634 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:42:04,634 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:42:04,634 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:42:04,635 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 15:42:04,635 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 15:42:04,637 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 15:42:04,643 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:04,644 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:04,644 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:04,646 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:04,647 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-04 15:42:04,649 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 15:42:04,659 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 15:42:04,660 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 15:42:04,660 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 15:42:04,660 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 15:42:04,665 INFO L401 nArgumentSynthesizer]: We have 6 Motzkin's Theorem applications. [2025-03-04 15:42:04,666 INFO L402 nArgumentSynthesizer]: A total of 2 supporting invariants were added. [2025-03-04 15:42:04,673 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 15:42:04,693 INFO L443 ModelExtractionUtils]: Simplification made 12 calls to the SMT solver. [2025-03-04 15:42:04,693 INFO L444 ModelExtractionUtils]: 1 out of 19 variables were initially zero. Simplification set additionally 15 variables to zero. [2025-03-04 15:42:04,693 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 15:42:04,693 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:04,695 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 15:42:04,696 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-04 15:42:04,696 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 15:42:04,707 INFO L438 nArgumentSynthesizer]: Removed 2 redundant supporting invariants from a total of 2. [2025-03-04 15:42:04,707 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 15:42:04,707 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(ULTIMATE.start_main_~length~0#1, ULTIMATE.start_main_~j~0#1) = 1*ULTIMATE.start_main_~length~0#1 - 1*ULTIMATE.start_main_~j~0#1 Supporting invariants [] [2025-03-04 15:42:04,713 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2025-03-04 15:42:04,725 INFO L156 tatePredicateManager]: 3 out of 3 supporting invariants were superfluous and have been removed [2025-03-04 15:42:04,735 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:04,740 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 15:42:04,746 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 15:42:04,746 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,747 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:04,747 INFO L256 TraceCheckSpWp]: Trace formula consists of 44 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 15:42:04,747 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:04,761 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:04,763 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:04,763 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,763 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:04,765 INFO L256 TraceCheckSpWp]: Trace formula consists of 14 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 15:42:04,765 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:04,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:04,777 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2025-03-04 15:42:04,778 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 6 Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 3 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:04,796 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 11 states and 15 transitions. cyclomatic complexity: 6. Second operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 3 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 15 states and 21 transitions. Complement of second has 5 states. [2025-03-04 15:42:04,797 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 15:42:04,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3 states, 3 states have (on average 3.6666666666666665) internal successors, (11), 3 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:04,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 13 transitions. [2025-03-04 15:42:04,797 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 9 letters. Loop has 2 letters. [2025-03-04 15:42:04,797 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:04,797 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 11 letters. Loop has 2 letters. [2025-03-04 15:42:04,798 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:04,798 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 13 transitions. Stem has 9 letters. Loop has 4 letters. [2025-03-04 15:42:04,798 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 15:42:04,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15 states and 21 transitions. [2025-03-04 15:42:04,798 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:04,798 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15 states to 15 states and 21 transitions. [2025-03-04 15:42:04,798 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9 [2025-03-04 15:42:04,798 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10 [2025-03-04 15:42:04,798 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15 states and 21 transitions. [2025-03-04 15:42:04,798 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:04,798 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15 states and 21 transitions. [2025-03-04 15:42:04,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15 states and 21 transitions. [2025-03-04 15:42:04,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15 to 15. [2025-03-04 15:42:04,799 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15 states, 15 states have (on average 1.4) internal successors, (21), 14 states have internal predecessors, (21), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:04,799 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 21 transitions. [2025-03-04 15:42:04,799 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15 states and 21 transitions. [2025-03-04 15:42:04,799 INFO L432 stractBuchiCegarLoop]: Abstraction has 15 states and 21 transitions. [2025-03-04 15:42:04,799 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 15:42:04,799 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15 states and 21 transitions. [2025-03-04 15:42:04,800 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:04,800 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:04,800 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:04,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:04,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:04,800 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:04,800 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:04,800 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:04,800 INFO L85 PathProgramCache]: Analyzing trace with hash -1661793937, now seen corresponding path program 1 times [2025-03-04 15:42:04,800 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:04,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [923093956] [2025-03-04 15:42:04,803 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:04,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:04,808 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 15:42:04,827 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 15:42:04,828 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:04,828 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:04,921 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-03-04 15:42:05,127 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,127 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:05,127 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [923093956] [2025-03-04 15:42:05,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [923093956] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:05,127 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1913451560] [2025-03-04 15:42:05,128 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:05,128 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:05,128 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:05,130 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:05,131 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Waiting until timeout for monitored process [2025-03-04 15:42:05,156 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 15:42:05,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 15:42:05,164 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,164 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:05,166 INFO L256 TraceCheckSpWp]: Trace formula consists of 55 conjuncts, 13 conjuncts are in the unsatisfiable core [2025-03-04 15:42:05,167 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:05,193 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:05,230 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:05,238 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,238 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:05,288 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 16 [2025-03-04 15:42:05,294 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 14 [2025-03-04 15:42:05,297 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1913451560] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:05,298 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:05,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 6, 6] total 15 [2025-03-04 15:42:05,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796448067] [2025-03-04 15:42:05,298 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:05,298 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:05,298 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:05,298 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 3 times [2025-03-04 15:42:05,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:05,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [105466656] [2025-03-04 15:42:05,299 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:05,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:05,301 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:05,303 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:05,303 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:42:05,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:05,303 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:05,303 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:05,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:05,305 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:05,306 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:05,341 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:05,341 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2025-03-04 15:42:05,342 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=184, Unknown=0, NotChecked=0, Total=240 [2025-03-04 15:42:05,342 INFO L87 Difference]: Start difference. First operand 15 states and 21 transitions. cyclomatic complexity: 9 Second operand has 16 states, 15 states have (on average 1.5333333333333334) internal successors, (23), 16 states have internal predecessors, (23), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:05,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:05,435 INFO L93 Difference]: Finished difference Result 28 states and 39 transitions. [2025-03-04 15:42:05,435 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 39 transitions. [2025-03-04 15:42:05,436 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-04 15:42:05,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 27 states and 38 transitions. [2025-03-04 15:42:05,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-04 15:42:05,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-04 15:42:05,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 27 states and 38 transitions. [2025-03-04 15:42:05,436 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:05,436 INFO L218 hiAutomatonCegarLoop]: Abstraction has 27 states and 38 transitions. [2025-03-04 15:42:05,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states and 38 transitions. [2025-03-04 15:42:05,437 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 20. [2025-03-04 15:42:05,437 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20 states, 20 states have (on average 1.45) internal successors, (29), 19 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:05,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 29 transitions. [2025-03-04 15:42:05,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20 states and 29 transitions. [2025-03-04 15:42:05,438 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 15:42:05,438 INFO L432 stractBuchiCegarLoop]: Abstraction has 20 states and 29 transitions. [2025-03-04 15:42:05,438 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 15:42:05,438 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20 states and 29 transitions. [2025-03-04 15:42:05,439 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:05,439 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:05,439 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:05,439 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:05,439 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:05,439 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:05,439 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:05,440 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:05,440 INFO L85 PathProgramCache]: Analyzing trace with hash 743859885, now seen corresponding path program 1 times [2025-03-04 15:42:05,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:05,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1418005848] [2025-03-04 15:42:05,440 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:05,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:05,443 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-04 15:42:05,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:42:05,447 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,447 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:05,504 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,505 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:05,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1418005848] [2025-03-04 15:42:05,505 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1418005848] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:05,505 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1663405442] [2025-03-04 15:42:05,505 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:05,505 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:05,505 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:05,507 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:05,508 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Waiting until timeout for monitored process [2025-03-04 15:42:05,533 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 13 statements into 1 equivalence classes. [2025-03-04 15:42:05,541 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 13 of 13 statements. [2025-03-04 15:42:05,541 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,541 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:05,541 INFO L256 TraceCheckSpWp]: Trace formula consists of 67 conjuncts, 6 conjuncts are in the unsatisfiable core [2025-03-04 15:42:05,542 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:05,576 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,576 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:05,603 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:05,603 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1663405442] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:05,603 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:05,603 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6] total 10 [2025-03-04 15:42:05,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722330416] [2025-03-04 15:42:05,603 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:05,603 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:05,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:05,604 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 4 times [2025-03-04 15:42:05,604 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:05,604 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037441908] [2025-03-04 15:42:05,604 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:05,604 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:05,606 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:42:05,608 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:05,609 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:42:05,609 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:05,609 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:05,609 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:05,612 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:05,612 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,612 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:05,612 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:05,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:05,651 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 15:42:05,651 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2025-03-04 15:42:05,651 INFO L87 Difference]: Start difference. First operand 20 states and 29 transitions. cyclomatic complexity: 13 Second operand has 10 states, 10 states have (on average 2.4) internal successors, (24), 10 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:05,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:05,688 INFO L93 Difference]: Finished difference Result 28 states and 38 transitions. [2025-03-04 15:42:05,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28 states and 38 transitions. [2025-03-04 15:42:05,689 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:05,690 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28 states to 25 states and 35 transitions. [2025-03-04 15:42:05,690 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:05,691 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:05,691 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25 states and 35 transitions. [2025-03-04 15:42:05,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:05,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25 states and 35 transitions. [2025-03-04 15:42:05,692 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states and 35 transitions. [2025-03-04 15:42:05,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 22. [2025-03-04 15:42:05,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22 states, 22 states have (on average 1.4090909090909092) internal successors, (31), 21 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:05,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 31 transitions. [2025-03-04 15:42:05,694 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-04 15:42:05,694 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 15:42:05,694 INFO L432 stractBuchiCegarLoop]: Abstraction has 22 states and 31 transitions. [2025-03-04 15:42:05,694 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 15:42:05,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22 states and 31 transitions. [2025-03-04 15:42:05,695 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:05,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:05,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:05,695 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:05,695 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:05,695 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:05,695 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:05,695 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:05,695 INFO L85 PathProgramCache]: Analyzing trace with hash 1702227283, now seen corresponding path program 1 times [2025-03-04 15:42:05,695 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:05,695 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [527313390] [2025-03-04 15:42:05,695 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:05,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:05,702 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-04 15:42:05,714 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-04 15:42:05,714 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:05,714 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:06,036 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:06,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:06,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [527313390] [2025-03-04 15:42:06,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [527313390] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:06,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1653474696] [2025-03-04 15:42:06,036 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:06,037 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:06,037 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:06,038 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:06,040 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Waiting until timeout for monitored process [2025-03-04 15:42:06,070 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 14 statements into 1 equivalence classes. [2025-03-04 15:42:06,080 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 14 of 14 statements. [2025-03-04 15:42:06,080 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:06,080 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:06,081 INFO L256 TraceCheckSpWp]: Trace formula consists of 77 conjuncts, 18 conjuncts are in the unsatisfiable core [2025-03-04 15:42:06,082 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:06,098 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:06,153 INFO L349 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2025-03-04 15:42:06,153 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2025-03-04 15:42:06,169 INFO L349 Elim1Store]: treesize reduction 25, result has 21.9 percent of original size [2025-03-04 15:42:06,169 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 33 treesize of output 13 [2025-03-04 15:42:06,202 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:06,213 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:06,213 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:06,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 23 [2025-03-04 15:42:06,378 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 44 [2025-03-04 15:42:06,396 INFO L134 CoverageAnalysis]: Checked inductivity of 5 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:06,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1653474696] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:06,396 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:06,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8] total 20 [2025-03-04 15:42:06,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793033718] [2025-03-04 15:42:06,396 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:06,397 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:06,397 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:06,397 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 5 times [2025-03-04 15:42:06,397 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:06,397 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1862317997] [2025-03-04 15:42:06,397 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:42:06,397 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:06,400 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:06,401 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:06,401 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:06,401 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:06,401 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:06,402 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:06,403 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:06,403 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:06,403 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:06,406 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:06,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:06,451 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2025-03-04 15:42:06,452 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=343, Unknown=0, NotChecked=0, Total=420 [2025-03-04 15:42:06,452 INFO L87 Difference]: Start difference. First operand 22 states and 31 transitions. cyclomatic complexity: 13 Second operand has 21 states, 20 states have (on average 1.6) internal successors, (32), 21 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:06,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:06,567 INFO L93 Difference]: Finished difference Result 24 states and 32 transitions. [2025-03-04 15:42:06,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24 states and 32 transitions. [2025-03-04 15:42:06,567 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:06,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24 states to 23 states and 31 transitions. [2025-03-04 15:42:06,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:06,568 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:06,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 23 states and 31 transitions. [2025-03-04 15:42:06,568 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:06,568 INFO L218 hiAutomatonCegarLoop]: Abstraction has 23 states and 31 transitions. [2025-03-04 15:42:06,568 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 23 states and 31 transitions. [2025-03-04 15:42:06,569 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 23 to 18. [2025-03-04 15:42:06,569 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18 states, 18 states have (on average 1.3333333333333333) internal successors, (24), 17 states have internal predecessors, (24), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:06,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 24 transitions. [2025-03-04 15:42:06,569 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18 states and 24 transitions. [2025-03-04 15:42:06,570 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 15:42:06,570 INFO L432 stractBuchiCegarLoop]: Abstraction has 18 states and 24 transitions. [2025-03-04 15:42:06,570 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 15:42:06,570 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18 states and 24 transitions. [2025-03-04 15:42:06,571 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:06,571 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:06,571 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:06,571 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:06,571 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:06,571 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:06,571 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:06,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:06,572 INFO L85 PathProgramCache]: Analyzing trace with hash 345382098, now seen corresponding path program 2 times [2025-03-04 15:42:06,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:06,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [483353839] [2025-03-04 15:42:06,572 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:06,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:06,577 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 16 statements into 2 equivalence classes. [2025-03-04 15:42:06,592 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 16 of 16 statements. [2025-03-04 15:42:06,593 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:06,593 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:06,896 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:06,896 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:06,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [483353839] [2025-03-04 15:42:06,896 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [483353839] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:06,896 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1302363371] [2025-03-04 15:42:06,896 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:06,896 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:06,896 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:06,899 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:06,912 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Waiting until timeout for monitored process [2025-03-04 15:42:06,943 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 16 statements into 2 equivalence classes. [2025-03-04 15:42:06,952 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 16 of 16 statements. [2025-03-04 15:42:06,952 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:06,952 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:06,953 INFO L256 TraceCheckSpWp]: Trace formula consists of 82 conjuncts, 21 conjuncts are in the unsatisfiable core [2025-03-04 15:42:06,954 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:06,994 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:07,071 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:07,079 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:07,079 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:07,160 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:07,162 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:07,177 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:07,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1302363371] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:07,178 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:07,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 8] total 21 [2025-03-04 15:42:07,178 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2146655487] [2025-03-04 15:42:07,178 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:07,178 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:07,178 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:07,178 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 6 times [2025-03-04 15:42:07,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:07,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [838475982] [2025-03-04 15:42:07,178 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:42:07,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:07,181 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:07,183 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:07,183 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:42:07,183 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:07,183 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:07,183 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:07,184 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:07,185 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:07,185 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:07,185 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:07,220 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:07,220 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-04 15:42:07,220 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=388, Unknown=0, NotChecked=0, Total=462 [2025-03-04 15:42:07,221 INFO L87 Difference]: Start difference. First operand 18 states and 24 transitions. cyclomatic complexity: 9 Second operand has 22 states, 21 states have (on average 1.7142857142857142) internal successors, (36), 22 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:07,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:07,498 INFO L93 Difference]: Finished difference Result 39 states and 52 transitions. [2025-03-04 15:42:07,498 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 39 states and 52 transitions. [2025-03-04 15:42:07,499 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-04 15:42:07,499 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 39 states to 38 states and 51 transitions. [2025-03-04 15:42:07,499 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15 [2025-03-04 15:42:07,499 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15 [2025-03-04 15:42:07,499 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38 states and 51 transitions. [2025-03-04 15:42:07,499 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:07,499 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38 states and 51 transitions. [2025-03-04 15:42:07,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states and 51 transitions. [2025-03-04 15:42:07,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 25. [2025-03-04 15:42:07,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25 states, 25 states have (on average 1.36) internal successors, (34), 24 states have internal predecessors, (34), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:07,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25 states to 25 states and 34 transitions. [2025-03-04 15:42:07,500 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25 states and 34 transitions. [2025-03-04 15:42:07,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2025-03-04 15:42:07,503 INFO L432 stractBuchiCegarLoop]: Abstraction has 25 states and 34 transitions. [2025-03-04 15:42:07,503 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 15:42:07,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25 states and 34 transitions. [2025-03-04 15:42:07,503 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:07,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:07,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:07,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:07,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:07,503 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:07,503 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:07,504 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:07,504 INFO L85 PathProgramCache]: Analyzing trace with hash 1199713616, now seen corresponding path program 3 times [2025-03-04 15:42:07,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:07,504 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800874936] [2025-03-04 15:42:07,504 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:07,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:07,510 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 18 statements into 3 equivalence classes. [2025-03-04 15:42:07,521 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 18 of 18 statements. [2025-03-04 15:42:07,521 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-04 15:42:07,522 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:07,581 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:07,581 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:07,581 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800874936] [2025-03-04 15:42:07,582 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800874936] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:07,582 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [448611329] [2025-03-04 15:42:07,582 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:07,582 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:07,582 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:07,585 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:07,586 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Waiting until timeout for monitored process [2025-03-04 15:42:07,612 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 18 statements into 3 equivalence classes. [2025-03-04 15:42:07,622 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) and asserted 18 of 18 statements. [2025-03-04 15:42:07,623 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2025-03-04 15:42:07,623 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:07,623 INFO L256 TraceCheckSpWp]: Trace formula consists of 94 conjuncts, 8 conjuncts are in the unsatisfiable core [2025-03-04 15:42:07,624 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:07,670 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:07,670 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:07,705 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:07,705 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [448611329] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:07,705 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:07,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8] total 13 [2025-03-04 15:42:07,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [496934779] [2025-03-04 15:42:07,706 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:07,706 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:07,707 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:07,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 7 times [2025-03-04 15:42:07,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:07,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1844661637] [2025-03-04 15:42:07,707 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:42:07,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:07,708 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:07,709 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:07,709 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:07,710 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:07,710 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:07,710 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:07,716 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:07,716 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:07,716 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:07,717 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:07,764 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:07,765 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 15:42:07,765 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2025-03-04 15:42:07,765 INFO L87 Difference]: Start difference. First operand 25 states and 34 transitions. cyclomatic complexity: 13 Second operand has 13 states, 13 states have (on average 2.3846153846153846) internal successors, (31), 13 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:07,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:07,801 INFO L93 Difference]: Finished difference Result 35 states and 45 transitions. [2025-03-04 15:42:07,801 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 35 states and 45 transitions. [2025-03-04 15:42:07,801 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:07,801 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 35 states to 30 states and 40 transitions. [2025-03-04 15:42:07,801 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:07,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:07,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 40 transitions. [2025-03-04 15:42:07,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:07,802 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 40 transitions. [2025-03-04 15:42:07,802 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 40 transitions. [2025-03-04 15:42:07,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 27. [2025-03-04 15:42:07,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27 states, 27 states have (on average 1.3333333333333333) internal successors, (36), 26 states have internal predecessors, (36), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:07,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 36 transitions. [2025-03-04 15:42:07,803 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27 states and 36 transitions. [2025-03-04 15:42:07,803 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-04 15:42:07,804 INFO L432 stractBuchiCegarLoop]: Abstraction has 27 states and 36 transitions. [2025-03-04 15:42:07,804 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 15:42:07,804 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27 states and 36 transitions. [2025-03-04 15:42:07,804 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:07,804 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:07,804 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:07,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:07,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:07,805 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:07,805 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:07,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:07,805 INFO L85 PathProgramCache]: Analyzing trace with hash -304267956, now seen corresponding path program 1 times [2025-03-04 15:42:07,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:07,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [179815471] [2025-03-04 15:42:07,805 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:07,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:07,809 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-03-04 15:42:07,819 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-03-04 15:42:07,819 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:07,819 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:08,087 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:08,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:08,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [179815471] [2025-03-04 15:42:08,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [179815471] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:08,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1640083448] [2025-03-04 15:42:08,088 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:08,088 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:08,088 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:08,090 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:08,092 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Waiting until timeout for monitored process [2025-03-04 15:42:08,119 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 19 statements into 1 equivalence classes. [2025-03-04 15:42:08,130 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 19 of 19 statements. [2025-03-04 15:42:08,130 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:08,130 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:08,130 INFO L256 TraceCheckSpWp]: Trace formula consists of 104 conjuncts, 22 conjuncts are in the unsatisfiable core [2025-03-04 15:42:08,132 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:08,145 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-04 15:42:08,188 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-04 15:42:08,188 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-04 15:42:08,206 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-04 15:42:08,206 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-04 15:42:08,233 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-04 15:42:08,241 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:08,241 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:08,362 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:08,366 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:08,372 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:08,372 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1640083448] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:08,372 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:08,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10] total 16 [2025-03-04 15:42:08,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [201681454] [2025-03-04 15:42:08,373 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:08,373 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:08,373 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:08,373 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 8 times [2025-03-04 15:42:08,373 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:08,373 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1616362041] [2025-03-04 15:42:08,373 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:08,373 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:08,375 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:08,376 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:08,376 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:08,376 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:08,376 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:08,377 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:08,378 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:08,378 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:08,378 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:08,379 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:08,416 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:08,417 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-04 15:42:08,417 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=222, Unknown=0, NotChecked=0, Total=272 [2025-03-04 15:42:08,417 INFO L87 Difference]: Start difference. First operand 27 states and 36 transitions. cyclomatic complexity: 13 Second operand has 17 states, 16 states have (on average 2.0) internal successors, (32), 17 states have internal predecessors, (32), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:08,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:08,532 INFO L93 Difference]: Finished difference Result 31 states and 40 transitions. [2025-03-04 15:42:08,532 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31 states and 40 transitions. [2025-03-04 15:42:08,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:08,532 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31 states to 30 states and 39 transitions. [2025-03-04 15:42:08,533 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:08,533 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:08,533 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30 states and 39 transitions. [2025-03-04 15:42:08,533 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:08,533 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30 states and 39 transitions. [2025-03-04 15:42:08,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states and 39 transitions. [2025-03-04 15:42:08,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 23. [2025-03-04 15:42:08,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 23 states, 23 states have (on average 1.3043478260869565) internal successors, (30), 22 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:08,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 23 states to 23 states and 30 transitions. [2025-03-04 15:42:08,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 23 states and 30 transitions. [2025-03-04 15:42:08,536 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2025-03-04 15:42:08,536 INFO L432 stractBuchiCegarLoop]: Abstraction has 23 states and 30 transitions. [2025-03-04 15:42:08,536 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 15:42:08,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 23 states and 30 transitions. [2025-03-04 15:42:08,537 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:08,537 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:08,537 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:08,537 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:08,537 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:08,537 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:08,537 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:08,537 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:08,537 INFO L85 PathProgramCache]: Analyzing trace with hash 2143782475, now seen corresponding path program 4 times [2025-03-04 15:42:08,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:08,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [232137530] [2025-03-04 15:42:08,537 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:08,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:08,546 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 21 statements into 2 equivalence classes. [2025-03-04 15:42:08,561 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 20 of 21 statements. [2025-03-04 15:42:08,561 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 15:42:08,561 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:08,780 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:08,780 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:08,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [232137530] [2025-03-04 15:42:08,780 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [232137530] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:08,780 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1208127787] [2025-03-04 15:42:08,781 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:08,781 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:08,781 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:08,783 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:08,784 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Waiting until timeout for monitored process [2025-03-04 15:42:08,816 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 21 statements into 2 equivalence classes. [2025-03-04 15:42:08,825 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 20 of 21 statements. [2025-03-04 15:42:08,825 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 15:42:08,825 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:08,826 INFO L256 TraceCheckSpWp]: Trace formula consists of 93 conjuncts, 21 conjuncts are in the unsatisfiable core [2025-03-04 15:42:08,827 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:08,839 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-04 15:42:08,905 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-04 15:42:08,916 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:08,916 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:08,993 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:08,995 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:09,009 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:09,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1208127787] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:09,009 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:09,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10] total 16 [2025-03-04 15:42:09,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811318995] [2025-03-04 15:42:09,009 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:09,009 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:09,010 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,010 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 9 times [2025-03-04 15:42:09,010 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [933353295] [2025-03-04 15:42:09,010 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:09,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,011 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:09,012 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:09,013 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:42:09,013 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,013 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:09,013 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:09,014 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:09,014 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,014 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,015 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:09,049 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:09,050 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2025-03-04 15:42:09,050 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=226, Unknown=0, NotChecked=0, Total=272 [2025-03-04 15:42:09,050 INFO L87 Difference]: Start difference. First operand 23 states and 30 transitions. cyclomatic complexity: 10 Second operand has 17 states, 16 states have (on average 2.0625) internal successors, (33), 17 states have internal predecessors, (33), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,206 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:09,206 INFO L93 Difference]: Finished difference Result 40 states and 52 transitions. [2025-03-04 15:42:09,206 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40 states and 52 transitions. [2025-03-04 15:42:09,207 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-04 15:42:09,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40 states to 39 states and 51 transitions. [2025-03-04 15:42:09,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-04 15:42:09,207 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-04 15:42:09,207 INFO L73 IsDeterministic]: Start isDeterministic. Operand 39 states and 51 transitions. [2025-03-04 15:42:09,208 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:09,208 INFO L218 hiAutomatonCegarLoop]: Abstraction has 39 states and 51 transitions. [2025-03-04 15:42:09,208 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states and 51 transitions. [2025-03-04 15:42:09,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 30. [2025-03-04 15:42:09,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30 states, 30 states have (on average 1.3333333333333333) internal successors, (40), 29 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 40 transitions. [2025-03-04 15:42:09,209 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30 states and 40 transitions. [2025-03-04 15:42:09,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 15:42:09,210 INFO L432 stractBuchiCegarLoop]: Abstraction has 30 states and 40 transitions. [2025-03-04 15:42:09,210 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 15:42:09,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30 states and 40 transitions. [2025-03-04 15:42:09,210 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:09,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:09,210 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:09,211 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:09,211 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:09,211 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:09,211 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:09,211 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,211 INFO L85 PathProgramCache]: Analyzing trace with hash -1409344375, now seen corresponding path program 5 times [2025-03-04 15:42:09,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [978377739] [2025-03-04 15:42:09,211 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:42:09,211 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,215 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 23 statements into 4 equivalence classes. [2025-03-04 15:42:09,225 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 23 of 23 statements. [2025-03-04 15:42:09,225 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-04 15:42:09,225 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:09,311 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:09,311 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:09,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [978377739] [2025-03-04 15:42:09,311 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [978377739] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:09,311 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [222410588] [2025-03-04 15:42:09,311 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:42:09,311 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:09,312 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:09,314 INFO L229 MonitoredProcess]: Starting monitored process 16 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:09,315 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Waiting until timeout for monitored process [2025-03-04 15:42:09,350 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 23 statements into 4 equivalence classes. [2025-03-04 15:42:09,369 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) and asserted 23 of 23 statements. [2025-03-04 15:42:09,369 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2025-03-04 15:42:09,369 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:09,370 INFO L256 TraceCheckSpWp]: Trace formula consists of 121 conjuncts, 10 conjuncts are in the unsatisfiable core [2025-03-04 15:42:09,371 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:09,433 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:09,433 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:09,481 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 9 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:09,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [222410588] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:09,482 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:09,482 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11] total 15 [2025-03-04 15:42:09,482 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744947891] [2025-03-04 15:42:09,482 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:09,482 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:09,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 10 times [2025-03-04 15:42:09,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748464436] [2025-03-04 15:42:09,482 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:09,482 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,484 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:42:09,485 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:09,485 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:42:09,485 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,485 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:09,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:09,487 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:09,487 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:09,528 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:09,528 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2025-03-04 15:42:09,528 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=151, Unknown=0, NotChecked=0, Total=210 [2025-03-04 15:42:09,529 INFO L87 Difference]: Start difference. First operand 30 states and 40 transitions. cyclomatic complexity: 14 Second operand has 15 states, 15 states have (on average 2.0) internal successors, (30), 15 states have internal predecessors, (30), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:09,616 INFO L93 Difference]: Finished difference Result 72 states and 93 transitions. [2025-03-04 15:42:09,616 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 72 states and 93 transitions. [2025-03-04 15:42:09,617 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 9 [2025-03-04 15:42:09,618 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 72 states to 64 states and 83 transitions. [2025-03-04 15:42:09,618 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 23 [2025-03-04 15:42:09,618 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 27 [2025-03-04 15:42:09,618 INFO L73 IsDeterministic]: Start isDeterministic. Operand 64 states and 83 transitions. [2025-03-04 15:42:09,618 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:09,618 INFO L218 hiAutomatonCegarLoop]: Abstraction has 64 states and 83 transitions. [2025-03-04 15:42:09,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states and 83 transitions. [2025-03-04 15:42:09,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 58. [2025-03-04 15:42:09,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 58 states, 58 states have (on average 1.3103448275862069) internal successors, (76), 57 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,623 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 76 transitions. [2025-03-04 15:42:09,623 INFO L240 hiAutomatonCegarLoop]: Abstraction has 58 states and 76 transitions. [2025-03-04 15:42:09,623 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-04 15:42:09,624 INFO L432 stractBuchiCegarLoop]: Abstraction has 58 states and 76 transitions. [2025-03-04 15:42:09,624 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 15:42:09,624 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 58 states and 76 transitions. [2025-03-04 15:42:09,624 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 8 [2025-03-04 15:42:09,624 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:09,624 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:09,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:09,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1] [2025-03-04 15:42:09,624 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume main_~length~0#1 < 1;main_~length~0#1 := 1;" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:09,624 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:09,625 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,625 INFO L85 PathProgramCache]: Analyzing trace with hash -694080175, now seen corresponding path program 1 times [2025-03-04 15:42:09,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [410000450] [2025-03-04 15:42:09,625 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:09,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,629 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 15:42:09,633 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 15:42:09,633 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,633 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:09,663 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 1 proven. 1 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2025-03-04 15:42:09,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:09,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [410000450] [2025-03-04 15:42:09,663 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [410000450] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:09,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [2050158843] [2025-03-04 15:42:09,663 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:09,663 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:09,663 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:09,666 INFO L229 MonitoredProcess]: Starting monitored process 17 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:09,667 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Waiting until timeout for monitored process [2025-03-04 15:42:09,711 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 22 statements into 1 equivalence classes. [2025-03-04 15:42:09,722 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 22 of 22 statements. [2025-03-04 15:42:09,722 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,722 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:09,723 INFO L256 TraceCheckSpWp]: Trace formula consists of 122 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 15:42:09,723 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:09,751 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2025-03-04 15:42:09,751 INFO L308 TraceCheckSpWp]: Omiting computation of backward sequence because forward sequence was already perfect [2025-03-04 15:42:09,751 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [2050158843] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 15:42:09,751 INFO L185 FreeRefinementEngine]: Found 1 perfect and 1 imperfect interpolant sequences. [2025-03-04 15:42:09,751 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [5] total 7 [2025-03-04 15:42:09,752 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [752263854] [2025-03-04 15:42:09,752 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 15:42:09,752 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:09,752 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,752 INFO L85 PathProgramCache]: Analyzing trace with hash 1107262, now seen corresponding path program 1 times [2025-03-04 15:42:09,752 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091447527] [2025-03-04 15:42:09,752 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 15:42:09,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,754 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-04 15:42:09,755 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-04 15:42:09,756 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,756 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,756 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:09,756 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 4 statements into 1 equivalence classes. [2025-03-04 15:42:09,757 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 4 of 4 statements. [2025-03-04 15:42:09,757 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:09,757 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:09,758 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:09,823 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:09,824 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 15:42:09,824 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2025-03-04 15:42:09,824 INFO L87 Difference]: Start difference. First operand 58 states and 76 transitions. cyclomatic complexity: 25 Second operand has 5 states, 5 states have (on average 3.2) internal successors, (16), 5 states have internal predecessors, (16), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:09,842 INFO L93 Difference]: Finished difference Result 38 states and 48 transitions. [2025-03-04 15:42:09,842 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 48 transitions. [2025-03-04 15:42:09,842 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:09,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 32 states and 41 transitions. [2025-03-04 15:42:09,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:09,843 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:09,843 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32 states and 41 transitions. [2025-03-04 15:42:09,843 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:09,843 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2025-03-04 15:42:09,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states and 41 transitions. [2025-03-04 15:42:09,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2025-03-04 15:42:09,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32 states, 32 states have (on average 1.28125) internal successors, (41), 31 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:09,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 41 transitions. [2025-03-04 15:42:09,844 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32 states and 41 transitions. [2025-03-04 15:42:09,845 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 15:42:09,845 INFO L432 stractBuchiCegarLoop]: Abstraction has 32 states and 41 transitions. [2025-03-04 15:42:09,845 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 15:42:09,845 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32 states and 41 transitions. [2025-03-04 15:42:09,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:09,845 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:09,845 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:09,846 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:09,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:09,846 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:09,846 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:09,846 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:09,846 INFO L85 PathProgramCache]: Analyzing trace with hash 965793903, now seen corresponding path program 2 times [2025-03-04 15:42:09,846 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:09,846 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291085478] [2025-03-04 15:42:09,847 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:09,847 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:09,851 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 2 equivalence classes. [2025-03-04 15:42:09,860 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 15:42:09,860 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:09,860 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:10,128 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:10,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:10,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291085478] [2025-03-04 15:42:10,129 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291085478] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:10,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1243980454] [2025-03-04 15:42:10,129 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:10,129 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:10,129 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:10,131 INFO L229 MonitoredProcess]: Starting monitored process 18 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:10,133 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Waiting until timeout for monitored process [2025-03-04 15:42:10,165 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 24 statements into 2 equivalence classes. [2025-03-04 15:42:10,179 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 24 of 24 statements. [2025-03-04 15:42:10,179 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:10,179 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:10,180 INFO L256 TraceCheckSpWp]: Trace formula consists of 131 conjuncts, 30 conjuncts are in the unsatisfiable core [2025-03-04 15:42:10,182 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:10,256 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:10,326 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-04 15:42:10,327 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-04 15:42:10,334 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-04 15:42:10,335 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-04 15:42:10,444 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:10,457 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:10,457 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:10,608 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-04 15:42:10,613 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2025-03-04 15:42:10,624 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:10,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1243980454] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:10,624 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:10,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 13, 12] total 26 [2025-03-04 15:42:10,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1780843138] [2025-03-04 15:42:10,624 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:10,624 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:10,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:10,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 11 times [2025-03-04 15:42:10,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:10,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233975282] [2025-03-04 15:42:10,625 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:42:10,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:10,626 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:10,628 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:10,628 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:10,628 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:10,628 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:10,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:10,629 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:10,629 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:10,629 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:10,630 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:10,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:10,667 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2025-03-04 15:42:10,667 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=600, Unknown=0, NotChecked=0, Total=702 [2025-03-04 15:42:10,668 INFO L87 Difference]: Start difference. First operand 32 states and 41 transitions. cyclomatic complexity: 13 Second operand has 27 states, 26 states have (on average 1.9230769230769231) internal successors, (50), 27 states have internal predecessors, (50), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:10,844 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:10,844 INFO L93 Difference]: Finished difference Result 38 states and 47 transitions. [2025-03-04 15:42:10,844 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38 states and 47 transitions. [2025-03-04 15:42:10,845 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:10,845 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38 states to 37 states and 46 transitions. [2025-03-04 15:42:10,845 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:10,845 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:10,845 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37 states and 46 transitions. [2025-03-04 15:42:10,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:10,845 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37 states and 46 transitions. [2025-03-04 15:42:10,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states and 46 transitions. [2025-03-04 15:42:10,846 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 28. [2025-03-04 15:42:10,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28 states, 28 states have (on average 1.25) internal successors, (35), 27 states have internal predecessors, (35), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:10,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 35 transitions. [2025-03-04 15:42:10,846 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28 states and 35 transitions. [2025-03-04 15:42:10,848 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-04 15:42:10,848 INFO L432 stractBuchiCegarLoop]: Abstraction has 28 states and 35 transitions. [2025-03-04 15:42:10,848 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 15:42:10,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28 states and 35 transitions. [2025-03-04 15:42:10,849 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:10,849 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:10,849 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:10,849 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:10,849 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:10,849 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:10,849 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:10,849 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:10,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1381947282, now seen corresponding path program 6 times [2025-03-04 15:42:10,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:10,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [673415140] [2025-03-04 15:42:10,850 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:42:10,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:10,854 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 26 statements into 5 equivalence classes. [2025-03-04 15:42:10,874 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 15:42:10,875 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-03-04 15:42:10,875 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:11,162 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 2 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:11,163 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:11,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [673415140] [2025-03-04 15:42:11,163 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [673415140] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:11,163 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [219058779] [2025-03-04 15:42:11,163 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:42:11,163 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:11,163 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:11,165 INFO L229 MonitoredProcess]: Starting monitored process 19 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:11,166 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Waiting until timeout for monitored process [2025-03-04 15:42:11,200 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 26 statements into 5 equivalence classes. [2025-03-04 15:42:11,217 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 15:42:11,217 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2025-03-04 15:42:11,217 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:11,218 INFO L256 TraceCheckSpWp]: Trace formula consists of 136 conjuncts, 29 conjuncts are in the unsatisfiable core [2025-03-04 15:42:11,219 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:11,296 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:11,424 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:11,435 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:11,435 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:11,563 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:11,568 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:11,624 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 0 proven. 34 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:11,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [219058779] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:11,624 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:11,624 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 12] total 33 [2025-03-04 15:42:11,624 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1904442774] [2025-03-04 15:42:11,624 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:11,624 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:11,624 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:11,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 12 times [2025-03-04 15:42:11,624 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:11,624 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [149333431] [2025-03-04 15:42:11,624 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 15:42:11,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:11,626 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:11,627 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:11,627 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 15:42:11,627 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:11,627 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:11,628 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:11,628 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:11,628 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:11,628 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:11,629 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:11,662 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:11,662 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2025-03-04 15:42:11,663 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=136, Invalid=986, Unknown=0, NotChecked=0, Total=1122 [2025-03-04 15:42:11,663 INFO L87 Difference]: Start difference. First operand 28 states and 35 transitions. cyclomatic complexity: 10 Second operand has 34 states, 33 states have (on average 2.0) internal successors, (66), 34 states have internal predecessors, (66), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:12,256 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:12,257 INFO L93 Difference]: Finished difference Result 63 states and 77 transitions. [2025-03-04 15:42:12,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 63 states and 77 transitions. [2025-03-04 15:42:12,257 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-04 15:42:12,258 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 63 states to 50 states and 63 transitions. [2025-03-04 15:42:12,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-04 15:42:12,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-04 15:42:12,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 50 states and 63 transitions. [2025-03-04 15:42:12,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:12,258 INFO L218 hiAutomatonCegarLoop]: Abstraction has 50 states and 63 transitions. [2025-03-04 15:42:12,258 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states and 63 transitions. [2025-03-04 15:42:12,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 37. [2025-03-04 15:42:12,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37 states, 37 states have (on average 1.2702702702702702) internal successors, (47), 36 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:12,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 47 transitions. [2025-03-04 15:42:12,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37 states and 47 transitions. [2025-03-04 15:42:12,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2025-03-04 15:42:12,259 INFO L432 stractBuchiCegarLoop]: Abstraction has 37 states and 47 transitions. [2025-03-04 15:42:12,259 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 15:42:12,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37 states and 47 transitions. [2025-03-04 15:42:12,260 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:12,260 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:12,260 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:12,260 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:12,260 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:12,260 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:12,260 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:12,261 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:12,261 INFO L85 PathProgramCache]: Analyzing trace with hash 558015400, now seen corresponding path program 3 times [2025-03-04 15:42:12,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:12,261 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1728213488] [2025-03-04 15:42:12,261 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:12,261 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:12,266 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 29 statements into 6 equivalence classes. [2025-03-04 15:42:12,294 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 15:42:12,294 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-04 15:42:12,294 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:12,623 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:12,624 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:12,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1728213488] [2025-03-04 15:42:12,624 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1728213488] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:12,624 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1042586773] [2025-03-04 15:42:12,624 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:12,624 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:12,624 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:12,626 INFO L229 MonitoredProcess]: Starting monitored process 20 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:12,627 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Waiting until timeout for monitored process [2025-03-04 15:42:12,664 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 29 statements into 6 equivalence classes. [2025-03-04 15:42:12,689 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 15:42:12,690 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2025-03-04 15:42:12,690 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:12,691 INFO L256 TraceCheckSpWp]: Trace formula consists of 158 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-03-04 15:42:12,692 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:12,781 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 1 [2025-03-04 15:42:12,852 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-04 15:42:12,853 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-04 15:42:12,860 INFO L190 IndexEqualityManager]: detected not equals via solver [2025-03-04 15:42:12,860 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 13 [2025-03-04 15:42:12,996 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 9 [2025-03-04 15:42:13,010 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:13,010 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:13,156 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:13,157 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:13,168 INFO L134 CoverageAnalysis]: Checked inductivity of 47 backedges. 0 proven. 47 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:13,168 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1042586773] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:13,168 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:13,168 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 15, 14] total 30 [2025-03-04 15:42:13,168 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [642298368] [2025-03-04 15:42:13,168 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:13,168 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:13,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:13,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 13 times [2025-03-04 15:42:13,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:13,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1007829608] [2025-03-04 15:42:13,169 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:42:13,169 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:13,171 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:13,172 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:13,172 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:13,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:13,172 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:13,172 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:13,188 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:13,188 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:13,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:13,189 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:13,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:13,222 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2025-03-04 15:42:13,222 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=815, Unknown=0, NotChecked=0, Total=930 [2025-03-04 15:42:13,222 INFO L87 Difference]: Start difference. First operand 37 states and 47 transitions. cyclomatic complexity: 14 Second operand has 31 states, 30 states have (on average 2.0) internal successors, (60), 31 states have internal predecessors, (60), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:13,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:13,458 INFO L93 Difference]: Finished difference Result 45 states and 55 transitions. [2025-03-04 15:42:13,458 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45 states and 55 transitions. [2025-03-04 15:42:13,458 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:13,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45 states to 44 states and 54 transitions. [2025-03-04 15:42:13,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:13,458 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:13,458 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44 states and 54 transitions. [2025-03-04 15:42:13,459 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:13,459 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44 states and 54 transitions. [2025-03-04 15:42:13,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states and 54 transitions. [2025-03-04 15:42:13,459 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 33. [2025-03-04 15:42:13,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33 states, 33 states have (on average 1.2424242424242424) internal successors, (41), 32 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:13,460 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 41 transitions. [2025-03-04 15:42:13,460 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33 states and 41 transitions. [2025-03-04 15:42:13,460 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2025-03-04 15:42:13,460 INFO L432 stractBuchiCegarLoop]: Abstraction has 33 states and 41 transitions. [2025-03-04 15:42:13,460 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 15:42:13,460 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33 states and 41 transitions. [2025-03-04 15:42:13,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:13,461 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:13,461 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:13,461 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [5, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:13,461 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:13,461 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:13,461 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:13,463 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:13,463 INFO L85 PathProgramCache]: Analyzing trace with hash -911516377, now seen corresponding path program 7 times [2025-03-04 15:42:13,463 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:13,463 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [805499640] [2025-03-04 15:42:13,463 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:42:13,463 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:13,469 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 15:42:13,485 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 15:42:13,485 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:13,485 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:13,763 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:13,763 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:13,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [805499640] [2025-03-04 15:42:13,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [805499640] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:13,763 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [483134007] [2025-03-04 15:42:13,763 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 15:42:13,763 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:13,763 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:13,765 INFO L229 MonitoredProcess]: Starting monitored process 21 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:13,766 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Waiting until timeout for monitored process [2025-03-04 15:42:13,804 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 15:42:13,820 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 15:42:13,820 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:13,820 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:13,821 INFO L256 TraceCheckSpWp]: Trace formula consists of 163 conjuncts, 36 conjuncts are in the unsatisfiable core [2025-03-04 15:42:13,822 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:13,825 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 3 [2025-03-04 15:42:13,830 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 3 [2025-03-04 15:42:13,849 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-04 15:42:13,942 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-04 15:42:13,964 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:13,964 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:14,023 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 18 [2025-03-04 15:42:14,024 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 14 [2025-03-04 15:42:14,052 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:14,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [483134007] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:14,052 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:14,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 15] total 23 [2025-03-04 15:42:14,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535701092] [2025-03-04 15:42:14,053 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:14,053 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:14,053 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:14,053 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 14 times [2025-03-04 15:42:14,053 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:14,053 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670322716] [2025-03-04 15:42:14,053 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:14,053 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:14,054 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:14,055 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:14,055 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:14,055 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:14,055 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:14,056 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:14,057 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:14,057 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:14,057 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:14,058 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:14,085 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:14,085 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2025-03-04 15:42:14,085 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=483, Unknown=0, NotChecked=0, Total=552 [2025-03-04 15:42:14,085 INFO L87 Difference]: Start difference. First operand 33 states and 41 transitions. cyclomatic complexity: 11 Second operand has 24 states, 23 states have (on average 2.130434782608696) internal successors, (49), 24 states have internal predecessors, (49), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:14,291 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:14,291 INFO L93 Difference]: Finished difference Result 54 states and 67 transitions. [2025-03-04 15:42:14,291 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 54 states and 67 transitions. [2025-03-04 15:42:14,291 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 4 [2025-03-04 15:42:14,291 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 54 states to 53 states and 66 transitions. [2025-03-04 15:42:14,292 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14 [2025-03-04 15:42:14,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14 [2025-03-04 15:42:14,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53 states and 66 transitions. [2025-03-04 15:42:14,292 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:14,292 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53 states and 66 transitions. [2025-03-04 15:42:14,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states and 66 transitions. [2025-03-04 15:42:14,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 40. [2025-03-04 15:42:14,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40 states, 40 states have (on average 1.275) internal successors, (51), 39 states have internal predecessors, (51), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:14,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 51 transitions. [2025-03-04 15:42:14,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40 states and 51 transitions. [2025-03-04 15:42:14,295 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-04 15:42:14,295 INFO L432 stractBuchiCegarLoop]: Abstraction has 40 states and 51 transitions. [2025-03-04 15:42:14,295 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 15:42:14,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40 states and 51 transitions. [2025-03-04 15:42:14,295 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:14,295 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:14,295 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:14,296 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:14,296 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:14,296 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:14,296 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:14,297 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:14,298 INFO L85 PathProgramCache]: Analyzing trace with hash 206089317, now seen corresponding path program 8 times [2025-03-04 15:42:14,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:14,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1328175719] [2025-03-04 15:42:14,298 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:14,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:14,302 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-03-04 15:42:14,312 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-03-04 15:42:14,312 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:14,312 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:14,442 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 21 proven. 44 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:14,442 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:14,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1328175719] [2025-03-04 15:42:14,442 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1328175719] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:14,442 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [649046688] [2025-03-04 15:42:14,442 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 15:42:14,442 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:14,442 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:14,445 INFO L229 MonitoredProcess]: Starting monitored process 22 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:14,446 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Waiting until timeout for monitored process [2025-03-04 15:42:14,484 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 33 statements into 2 equivalence classes. [2025-03-04 15:42:14,501 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) and asserted 33 of 33 statements. [2025-03-04 15:42:14,501 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2025-03-04 15:42:14,501 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:14,502 INFO L256 TraceCheckSpWp]: Trace formula consists of 175 conjuncts, 14 conjuncts are in the unsatisfiable core [2025-03-04 15:42:14,503 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:14,616 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:14,617 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:14,704 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 30 proven. 35 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:14,705 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [649046688] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:14,705 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:14,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14] total 22 [2025-03-04 15:42:14,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [592643460] [2025-03-04 15:42:14,705 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:14,705 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:14,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:14,706 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 15 times [2025-03-04 15:42:14,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:14,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029142500] [2025-03-04 15:42:14,706 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:14,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:14,707 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:14,708 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:14,708 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 15:42:14,708 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:14,709 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:14,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:14,710 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:14,712 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:14,712 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:14,713 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:14,748 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:14,748 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2025-03-04 15:42:14,748 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=347, Unknown=0, NotChecked=0, Total=462 [2025-03-04 15:42:14,749 INFO L87 Difference]: Start difference. First operand 40 states and 51 transitions. cyclomatic complexity: 15 Second operand has 22 states, 22 states have (on average 2.3636363636363638) internal successors, (52), 22 states have internal predecessors, (52), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:14,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:14,836 INFO L93 Difference]: Finished difference Result 56 states and 68 transitions. [2025-03-04 15:42:14,836 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 68 transitions. [2025-03-04 15:42:14,836 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:14,837 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 45 states and 57 transitions. [2025-03-04 15:42:14,837 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:14,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:14,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45 states and 57 transitions. [2025-03-04 15:42:14,837 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:14,837 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45 states and 57 transitions. [2025-03-04 15:42:14,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states and 57 transitions. [2025-03-04 15:42:14,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 42. [2025-03-04 15:42:14,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42 states, 42 states have (on average 1.2619047619047619) internal successors, (53), 41 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:14,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 53 transitions. [2025-03-04 15:42:14,838 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42 states and 53 transitions. [2025-03-04 15:42:14,840 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2025-03-04 15:42:14,841 INFO L432 stractBuchiCegarLoop]: Abstraction has 42 states and 53 transitions. [2025-03-04 15:42:14,841 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 15:42:14,841 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42 states and 53 transitions. [2025-03-04 15:42:14,841 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:14,841 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:14,841 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:14,842 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 5, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:14,842 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:14,842 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume 0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2);havoc main_#t~mem208#1;call write~int#0(0, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:14,842 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:14,842 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:14,842 INFO L85 PathProgramCache]: Analyzing trace with hash -1396265589, now seen corresponding path program 4 times [2025-03-04 15:42:14,842 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:14,842 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1477390461] [2025-03-04 15:42:14,842 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:14,842 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:14,849 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 34 statements into 2 equivalence classes. [2025-03-04 15:42:14,861 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 33 of 34 statements. [2025-03-04 15:42:14,861 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 15:42:14,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:15,290 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:15,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:15,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1477390461] [2025-03-04 15:42:15,291 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1477390461] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:15,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [776381796] [2025-03-04 15:42:15,291 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:15,291 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:15,291 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:15,293 INFO L229 MonitoredProcess]: Starting monitored process 23 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:15,295 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Waiting until timeout for monitored process [2025-03-04 15:42:15,335 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 34 statements into 2 equivalence classes. [2025-03-04 15:42:15,351 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 33 of 34 statements. [2025-03-04 15:42:15,351 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 15:42:15,351 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:15,352 INFO L256 TraceCheckSpWp]: Trace formula consists of 169 conjuncts, 34 conjuncts are in the unsatisfiable core [2025-03-04 15:42:15,354 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:15,371 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 1 [2025-03-04 15:42:15,423 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-04 15:42:15,423 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-04 15:42:15,434 INFO L349 Elim1Store]: treesize reduction 27, result has 25.0 percent of original size [2025-03-04 15:42:15,434 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 1 case distinctions, treesize of input 35 treesize of output 15 [2025-03-04 15:42:15,533 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 9 [2025-03-04 15:42:15,547 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:15,547 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:15,728 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-04 15:42:15,730 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2025-03-04 15:42:15,744 INFO L134 CoverageAnalysis]: Checked inductivity of 71 backedges. 0 proven. 71 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:15,744 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [776381796] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:15,744 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:15,744 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16] total 25 [2025-03-04 15:42:15,745 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1194036219] [2025-03-04 15:42:15,745 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:15,745 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:15,745 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:15,745 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 16 times [2025-03-04 15:42:15,745 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:15,745 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1558014975] [2025-03-04 15:42:15,745 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 15:42:15,745 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:15,747 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 15:42:15,748 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:15,748 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 15:42:15,748 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:15,748 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:15,748 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:15,749 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:15,749 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:15,749 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:15,750 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:15,782 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:15,783 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2025-03-04 15:42:15,783 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=576, Unknown=0, NotChecked=0, Total=650 [2025-03-04 15:42:15,783 INFO L87 Difference]: Start difference. First operand 42 states and 53 transitions. cyclomatic complexity: 15 Second operand has 26 states, 25 states have (on average 2.12) internal successors, (53), 26 states have internal predecessors, (53), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:15,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:15,992 INFO L93 Difference]: Finished difference Result 52 states and 63 transitions. [2025-03-04 15:42:15,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52 states and 63 transitions. [2025-03-04 15:42:15,993 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:15,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52 states to 51 states and 62 transitions. [2025-03-04 15:42:15,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11 [2025-03-04 15:42:15,994 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11 [2025-03-04 15:42:15,994 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51 states and 62 transitions. [2025-03-04 15:42:15,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 15:42:15,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51 states and 62 transitions. [2025-03-04 15:42:15,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states and 62 transitions. [2025-03-04 15:42:15,995 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 38. [2025-03-04 15:42:15,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38 states, 38 states have (on average 1.236842105263158) internal successors, (47), 37 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:15,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 47 transitions. [2025-03-04 15:42:15,995 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38 states and 47 transitions. [2025-03-04 15:42:15,995 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2025-03-04 15:42:15,995 INFO L432 stractBuchiCegarLoop]: Abstraction has 38 states and 47 transitions. [2025-03-04 15:42:15,995 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 15:42:15,996 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38 states and 47 transitions. [2025-03-04 15:42:15,996 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 2 [2025-03-04 15:42:15,996 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 15:42:15,996 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 15:42:15,996 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [6, 6, 6, 6, 5, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 15:42:15,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 15:42:15,996 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~nondet205#1, main_#t~malloc206#1.base, main_#t~malloc206#1.offset, main_#t~nondet207#1, main_#t~mem208#1, main_#t~post209#1, main_#t~mem210#1, main_#t~post211#1, main_#t~post212#1, main_~i~0#1, main_~j~0#1, main_~length~0#1, main_~arr~0#1.base, main_~arr~0#1.offset;havoc main_~i~0#1;havoc main_~j~0#1;havoc main_#t~nondet205#1;main_~length~0#1 := main_#t~nondet205#1;havoc main_#t~nondet205#1;" "assume !(main_~length~0#1 < 1);" "call main_#t~malloc206#1.base, main_#t~malloc206#1.offset := #Ultimate.allocOnStack(4 * main_~length~0#1 % 18446744073709551616);main_~arr~0#1.base, main_~arr~0#1.offset := main_#t~malloc206#1.base, main_#t~malloc206#1.offset;" "assume !(main_~arr~0#1.base == 0 && main_~arr~0#1.offset == 0);main_~i~0#1 := 0;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume main_~i~0#1 < main_~length~0#1;havoc main_#t~nondet207#1;call write~int#0(main_#t~nondet207#1, main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);havoc main_#t~nondet207#1;call main_#t~mem208#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~i~0#1, 4);" "assume !(0 != (if main_#t~mem208#1 < 0 && 0 != main_#t~mem208#1 % 2 then main_#t~mem208#1 % 2 - 2 else main_#t~mem208#1 % 2));havoc main_#t~mem208#1;" "main_#t~post209#1 := main_~i~0#1;main_~i~0#1 := 1 + main_#t~post209#1;havoc main_#t~post209#1;" "assume !(main_~i~0#1 < main_~length~0#1);main_~j~0#1 := 0;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume !(0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2));havoc main_#t~mem210#1;main_#t~post212#1 := main_~j~0#1;main_~j~0#1 := main_#t~post212#1 - 1;havoc main_#t~post212#1;" [2025-03-04 15:42:15,996 INFO L754 eck$LassoCheckResult]: Loop: "assume 0 <= main_~j~0#1 && main_~j~0#1 < main_~length~0#1;call main_#t~mem210#1 := read~int#0(main_~arr~0#1.base, main_~arr~0#1.offset + 4 * main_~j~0#1, 4);" "assume 0 == (if main_#t~mem210#1 < 0 && 0 != main_#t~mem210#1 % 2 then main_#t~mem210#1 % 2 - 2 else main_#t~mem210#1 % 2);havoc main_#t~mem210#1;main_#t~post211#1 := main_~j~0#1;main_~j~0#1 := 1 + main_#t~post211#1;havoc main_#t~post211#1;" [2025-03-04 15:42:15,997 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:15,997 INFO L85 PathProgramCache]: Analyzing trace with hash -273883638, now seen corresponding path program 9 times [2025-03-04 15:42:15,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:15,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1681045030] [2025-03-04 15:42:15,997 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:15,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:16,002 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 7 equivalence classes. [2025-03-04 15:42:16,032 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 15:42:16,032 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2025-03-04 15:42:16,032 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:16,381 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 12 proven. 69 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:16,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 15:42:16,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1681045030] [2025-03-04 15:42:16,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1681045030] provided 0 perfect and 1 imperfect interpolant sequences [2025-03-04 15:42:16,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleZ3 [1561600005] [2025-03-04 15:42:16,382 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 15:42:16,382 INFO L173 SolverBuilder]: Constructing external solver with command: z3 -smt2 -in SMTLIB2_COMPLIANT=true [2025-03-04 15:42:16,382 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 15:42:16,384 INFO L229 MonitoredProcess]: Starting monitored process 24 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (exit command is (exit), workingDir is null) [2025-03-04 15:42:16,386 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Waiting until timeout for monitored process [2025-03-04 15:42:16,427 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 36 statements into 7 equivalence classes. [2025-03-04 15:42:16,455 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 15:42:16,455 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2025-03-04 15:42:16,456 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 15:42:16,457 INFO L256 TraceCheckSpWp]: Trace formula consists of 190 conjuncts, 24 conjuncts are in the unsatisfiable core [2025-03-04 15:42:16,458 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 15:42:16,488 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 1 [2025-03-04 15:42:16,808 INFO L349 Elim1Store]: treesize reduction 5, result has 37.5 percent of original size [2025-03-04 15:42:16,808 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 1 case distinctions, treesize of input 25 treesize of output 12 [2025-03-04 15:42:16,821 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 25 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:16,821 INFO L312 TraceCheckSpWp]: Computing backward predicates... [2025-03-04 15:42:17,148 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2025-03-04 15:42:17,150 INFO L378 Elim1Store]: Elim1 eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 14 [2025-03-04 15:42:17,184 INFO L134 CoverageAnalysis]: Checked inductivity of 81 backedges. 20 proven. 61 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 15:42:17,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleZ3 [1561600005] provided 0 perfect and 2 imperfect interpolant sequences [2025-03-04 15:42:17,185 INFO L185 FreeRefinementEngine]: Found 0 perfect and 3 imperfect interpolant sequences. [2025-03-04 15:42:17,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17] total 34 [2025-03-04 15:42:17,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2026282881] [2025-03-04 15:42:17,185 INFO L85 oduleStraightlineAll]: Using 3 imperfect interpolants to construct interpolant automaton [2025-03-04 15:42:17,185 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 15:42:17,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 15:42:17,185 INFO L85 PathProgramCache]: Analyzing trace with hash 1151, now seen corresponding path program 17 times [2025-03-04 15:42:17,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 15:42:17,186 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [78552212] [2025-03-04 15:42:17,186 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 15:42:17,186 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 15:42:17,187 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:17,188 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:17,188 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 15:42:17,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:17,188 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 15:42:17,189 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 15:42:17,190 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 15:42:17,190 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 15:42:17,190 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 15:42:17,191 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 15:42:17,225 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 15:42:17,225 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2025-03-04 15:42:17,226 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=212, Invalid=978, Unknown=0, NotChecked=0, Total=1190 [2025-03-04 15:42:17,226 INFO L87 Difference]: Start difference. First operand 38 states and 47 transitions. cyclomatic complexity: 12 Second operand has 35 states, 34 states have (on average 2.0294117647058822) internal successors, (69), 35 states have internal predecessors, (69), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 15:42:17,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 15:42:17,900 INFO L93 Difference]: Finished difference Result 56 states and 66 transitions. [2025-03-04 15:42:17,900 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 56 states and 66 transitions. [2025-03-04 15:42:17,900 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-04 15:42:17,900 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 56 states to 0 states and 0 transitions. [2025-03-04 15:42:17,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2025-03-04 15:42:17,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2025-03-04 15:42:17,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2025-03-04 15:42:17,901 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 15:42:17,901 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 15:42:17,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 15:42:17,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2025-03-04 15:42:17,903 INFO L432 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 15:42:17,903 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 15:42:17,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2025-03-04 15:42:17,903 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-04 15:42:17,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2025-03-04 15:42:17,908 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 03:42:17 BoogieIcfgContainer [2025-03-04 15:42:17,908 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 15:42:17,909 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 15:42:17,909 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 15:42:17,909 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 15:42:17,909 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 03:42:02" (3/4) ... [2025-03-04 15:42:17,911 INFO L149 WitnessPrinter]: No result that supports witness generation found [2025-03-04 15:42:17,911 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 15:42:17,912 INFO L158 Benchmark]: Toolchain (without parser) took 15669.84ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 103.6MB in the beginning and 213.1MB in the end (delta: -109.5MB). Peak memory consumption was 181.4MB. Max. memory is 16.1GB. [2025-03-04 15:42:17,912 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 126.8MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:42:17,912 INFO L158 Benchmark]: CACSL2BoogieTranslator took 233.86ms. Allocated memory is still 142.6MB. Free memory was 103.6MB in the beginning and 85.6MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-04 15:42:17,912 INFO L158 Benchmark]: Boogie Procedure Inliner took 23.25ms. Allocated memory is still 142.6MB. Free memory was 85.6MB in the beginning and 83.3MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 15:42:17,913 INFO L158 Benchmark]: Boogie Preprocessor took 16.36ms. Allocated memory is still 142.6MB. Free memory was 83.3MB in the beginning and 82.3MB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:42:17,913 INFO L158 Benchmark]: IcfgBuilder took 212.57ms. Allocated memory is still 142.6MB. Free memory was 82.3MB in the beginning and 70.8MB in the end (delta: 11.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 15:42:17,913 INFO L158 Benchmark]: BuchiAutomizer took 15176.91ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 69.8MB in the beginning and 213.2MB in the end (delta: -143.4MB). Peak memory consumption was 147.8MB. Max. memory is 16.1GB. [2025-03-04 15:42:17,913 INFO L158 Benchmark]: Witness Printer took 2.82ms. Allocated memory is still 427.8MB. Free memory was 213.2MB in the beginning and 213.1MB in the end (delta: 129.3kB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 15:42:17,914 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 201.3MB. Free memory is still 126.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 233.86ms. Allocated memory is still 142.6MB. Free memory was 103.6MB in the beginning and 85.6MB in the end (delta: 18.0MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 23.25ms. Allocated memory is still 142.6MB. Free memory was 85.6MB in the beginning and 83.3MB in the end (delta: 2.3MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Preprocessor took 16.36ms. Allocated memory is still 142.6MB. Free memory was 83.3MB in the beginning and 82.3MB in the end (delta: 1.0MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 212.57ms. Allocated memory is still 142.6MB. Free memory was 82.3MB in the beginning and 70.8MB in the end (delta: 11.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 15176.91ms. Allocated memory was 142.6MB in the beginning and 427.8MB in the end (delta: 285.2MB). Free memory was 69.8MB in the beginning and 213.2MB in the end (delta: -143.4MB). Peak memory consumption was 147.8MB. Max. memory is 16.1GB. * Witness Printer took 2.82ms. Allocated memory is still 427.8MB. Free memory was 213.2MB in the beginning and 213.1MB in the end (delta: 129.3kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Unknown variable: #length - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Cannot backtranslate array access to array IdentifierExpression[#length,GLOBAL] - GenericResult: Unfinished Backtranslation Unfinished Backtranslation: Unknown variable: ~arr~0!offset * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 19 terminating modules (17 trivial, 2 deterministic, 0 nondeterministic). One deterministic module has affine ranking function null and consists of 3 locations. One deterministic module has affine ranking function (((long) -1 * j) + length) and consists of 3 locations. 17 modules have a trivial ranking function, the largest among these consists of 35 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 15.1s and 20 iterations. TraceHistogramMax:6. Analysis of lassos took 11.6s. Construction of modules took 1.6s. Büchi inclusion checks took 1.7s. Highest rank in rank-based complementation 3. Minimization of det autom 3. Minimization of nondet autom 16. Automata minimization 0.0s AutomataMinimizationTime, 18 MinimizatonAttempts, 118 StatesRemovedByMinimization, 16 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [2, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 586 SdHoareTripleChecker+Valid, 2.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 584 mSDsluCounter, 983 SdHoareTripleChecker+Invalid, 1.7s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 826 mSDsCounter, 213 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 3870 IncrementalHoareTripleChecker+Invalid, 4083 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 213 mSolverCounterUnsat, 157 mSDtfsCounter, 3870 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc0 concLT0 SILN0 SILU17 SILI0 SILT0 lasso2 LassoPreprocessingBenchmarks: Lassos: inital105 mio100 ax100 hnf100 lsp100 ukn82 mio100 lsp56 div180 bol100 ite100 ukn100 eq150 hnf94 smp64 dnf100 smp100 tf100 neg100 sie100 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 22ms VariablesStem: 2 VariablesLoop: 0 DisjunctsStem: 1 DisjunctsLoop: 1 SupportingInvariants: 2 MotzkinApplications: 6 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2025-03-04 15:42:17,926 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (24)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:18,129 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (23)] Ended with exit code 0 [2025-03-04 15:42:18,329 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (22)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:18,530 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (21)] Ended with exit code 0 [2025-03-04 15:42:18,730 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (20)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:18,930 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (19)] Ended with exit code 0 [2025-03-04 15:42:19,130 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (18)] Ended with exit code 0 [2025-03-04 15:42:19,331 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (17)] Ended with exit code 0 [2025-03-04 15:42:19,531 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (16)] Ended with exit code 0 [2025-03-04 15:42:19,731 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (15)] Ended with exit code 0 [2025-03-04 15:42:19,932 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (14)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:20,132 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (13)] Ended with exit code 0 [2025-03-04 15:42:20,332 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (12)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:20,532 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (11)] Ended with exit code 0 [2025-03-04 15:42:20,733 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (10)] Ended with exit code 0 [2025-03-04 15:42:20,933 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 -smt2 -in SMTLIB2_COMPLIANT=true (9)] Forceful destruction successful, exit code 0 [2025-03-04 15:42:21,134 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE