./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/kundu2.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/kundu2.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:19:47,148 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:19:47,204 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:19:47,210 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:19:47,211 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:19:47,212 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:19:47,258 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:19:47,258 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:19:47,258 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:19:47,259 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:19:47,259 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:19:47,259 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:19:47,259 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:19:47,261 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:19:47,261 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:19:47,261 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:19:47,261 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:19:47,261 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:19:47,261 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:19:47,262 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:19:47,263 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:19:47,263 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:19:47,263 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:19:47,263 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:19:47,264 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:19:47,264 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 87760fc84dfa44e1b5109b35af0fae7e5f68f814afbb1ba90e7b46e4e9e3b4bf [2025-03-04 16:19:47,537 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:19:47,545 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:19:47,547 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:19:47,548 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:19:47,549 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:19:47,549 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/kundu2.cil.c [2025-03-04 16:19:48,752 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8185de28d/3c7ce76f95df4b3588f206383df5bc1c/FLAG3175cf75f [2025-03-04 16:19:48,999 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:19:49,001 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/kundu2.cil.c [2025-03-04 16:19:49,033 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8185de28d/3c7ce76f95df4b3588f206383df5bc1c/FLAG3175cf75f [2025-03-04 16:19:49,308 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/8185de28d/3c7ce76f95df4b3588f206383df5bc1c [2025-03-04 16:19:49,311 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:19:49,312 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:19:49,313 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:49,313 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:19:49,316 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:19:49,317 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,318 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a665fc4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49, skipping insertion in model container [2025-03-04 16:19:49,319 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,337 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:19:49,488 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:49,500 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:19:49,527 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:19:49,540 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:19:49,540 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49 WrapperNode [2025-03-04 16:19:49,541 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:19:49,541 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:49,542 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:19:49,542 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:19:49,546 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,551 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,582 INFO L138 Inliner]: procedures = 34, calls = 41, calls flagged for inlining = 36, calls inlined = 49, statements flattened = 520 [2025-03-04 16:19:49,582 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:19:49,582 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:19:49,582 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:19:49,583 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:19:49,591 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,591 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,593 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,601 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:19:49,602 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,602 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,606 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,610 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,611 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,612 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,616 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:19:49,616 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:19:49,616 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:19:49,616 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:19:49,617 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (1/1) ... [2025-03-04 16:19:49,624 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:19:49,638 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:19:49,648 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:19:49,651 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:19:49,669 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:19:49,669 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:19:49,669 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:19:49,670 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:19:49,732 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:19:49,733 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:19:50,138 INFO L? ?]: Removed 101 outVars from TransFormulas that were not future-live. [2025-03-04 16:19:50,138 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:19:50,149 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:19:50,149 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:19:50,150 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:50 BoogieIcfgContainer [2025-03-04 16:19:50,150 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:19:50,151 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:19:50,151 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:19:50,155 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:19:50,156 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:50,156 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:19:49" (1/3) ... [2025-03-04 16:19:50,157 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@730f6da9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:50, skipping insertion in model container [2025-03-04 16:19:50,157 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:50,157 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:19:49" (2/3) ... [2025-03-04 16:19:50,157 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@730f6da9 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:19:50, skipping insertion in model container [2025-03-04 16:19:50,157 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:19:50,157 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:50" (3/3) ... [2025-03-04 16:19:50,158 INFO L363 chiAutomizerObserver]: Analyzing ICFG kundu2.cil.c [2025-03-04 16:19:50,200 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:19:50,201 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:19:50,201 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:19:50,201 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:19:50,201 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:19:50,202 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:19:50,202 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:19:50,202 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:19:50,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 200 states, 199 states have (on average 1.4522613065326633) internal successors, (289), 199 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,222 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2025-03-04 16:19:50,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:50,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:50,228 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,228 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,228 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:19:50,229 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 200 states, 199 states have (on average 1.4522613065326633) internal successors, (289), 199 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 163 [2025-03-04 16:19:50,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:50,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:50,235 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,235 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,240 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~P_1_i~0);~P_1_st~0 := 2;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:50,241 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume !true;" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:50,244 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,245 INFO L85 PathProgramCache]: Analyzing trace with hash -1698192512, now seen corresponding path program 1 times [2025-03-04 16:19:50,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1073712139] [2025-03-04 16:19:50,252 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,253 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,311 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:50,330 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:50,330 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,330 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1073712139] [2025-03-04 16:19:50,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1073712139] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:50,423 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [540965812] [2025-03-04 16:19:50,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,426 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:50,427 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,427 INFO L85 PathProgramCache]: Analyzing trace with hash 1252521716, now seen corresponding path program 1 times [2025-03-04 16:19:50,427 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,428 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601647517] [2025-03-04 16:19:50,428 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,428 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,438 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 37 statements into 1 equivalence classes. [2025-03-04 16:19:50,440 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 37 of 37 statements. [2025-03-04 16:19:50,442 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,442 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,456 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601647517] [2025-03-04 16:19:50,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601647517] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:50,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1342933002] [2025-03-04 16:19:50,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,460 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:50,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:50,478 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:50,478 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:50,480 INFO L87 Difference]: Start difference. First operand has 200 states, 199 states have (on average 1.4522613065326633) internal successors, (289), 199 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:50,532 INFO L93 Difference]: Finished difference Result 192 states and 274 transitions. [2025-03-04 16:19:50,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 192 states and 274 transitions. [2025-03-04 16:19:50,538 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,546 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 192 states to 184 states and 266 transitions. [2025-03-04 16:19:50,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184 [2025-03-04 16:19:50,548 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184 [2025-03-04 16:19:50,548 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 266 transitions. [2025-03-04 16:19:50,549 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:50,549 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 266 transitions. [2025-03-04 16:19:50,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 266 transitions. [2025-03-04 16:19:50,572 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 184. [2025-03-04 16:19:50,573 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184 states, 184 states have (on average 1.4456521739130435) internal successors, (266), 183 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 266 transitions. [2025-03-04 16:19:50,576 INFO L240 hiAutomatonCegarLoop]: Abstraction has 184 states and 266 transitions. [2025-03-04 16:19:50,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:50,581 INFO L432 stractBuchiCegarLoop]: Abstraction has 184 states and 266 transitions. [2025-03-04 16:19:50,581 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:19:50,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184 states and 266 transitions. [2025-03-04 16:19:50,582 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,582 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:50,582 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:50,583 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,583 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,583 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume !(1 == ~P_2_i~0);~P_2_st~0 := 2;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:50,583 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:50,585 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,585 INFO L85 PathProgramCache]: Analyzing trace with hash -1631185759, now seen corresponding path program 1 times [2025-03-04 16:19:50,587 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,587 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513737799] [2025-03-04 16:19:50,587 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,587 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,595 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:50,605 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:50,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1513737799] [2025-03-04 16:19:50,639 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1513737799] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,639 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,639 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:50,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794921166] [2025-03-04 16:19:50,639 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,639 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:50,640 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,640 INFO L85 PathProgramCache]: Analyzing trace with hash -1431657590, now seen corresponding path program 1 times [2025-03-04 16:19:50,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1952568272] [2025-03-04 16:19:50,640 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,646 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:50,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:50,657 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,657 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,743 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,743 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,743 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1952568272] [2025-03-04 16:19:50,743 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1952568272] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,743 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,743 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:50,743 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1645001119] [2025-03-04 16:19:50,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,744 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:50,744 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:50,744 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:50,744 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:50,744 INFO L87 Difference]: Start difference. First operand 184 states and 266 transitions. cyclomatic complexity: 83 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,755 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:50,756 INFO L93 Difference]: Finished difference Result 184 states and 265 transitions. [2025-03-04 16:19:50,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 265 transitions. [2025-03-04 16:19:50,757 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,758 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 184 states and 265 transitions. [2025-03-04 16:19:50,758 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184 [2025-03-04 16:19:50,758 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184 [2025-03-04 16:19:50,758 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 265 transitions. [2025-03-04 16:19:50,758 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:50,759 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 265 transitions. [2025-03-04 16:19:50,759 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 265 transitions. [2025-03-04 16:19:50,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 184. [2025-03-04 16:19:50,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184 states, 184 states have (on average 1.440217391304348) internal successors, (265), 183 states have internal predecessors, (265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 265 transitions. [2025-03-04 16:19:50,764 INFO L240 hiAutomatonCegarLoop]: Abstraction has 184 states and 265 transitions. [2025-03-04 16:19:50,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:50,764 INFO L432 stractBuchiCegarLoop]: Abstraction has 184 states and 265 transitions. [2025-03-04 16:19:50,765 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:19:50,765 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184 states and 265 transitions. [2025-03-04 16:19:50,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:50,767 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:50,767 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,769 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume !(1 == ~C_1_i~0);~C_1_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:50,769 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:50,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1419017056, now seen corresponding path program 1 times [2025-03-04 16:19:50,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [332200271] [2025-03-04 16:19:50,770 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,780 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:50,783 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:50,785 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,786 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,815 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,815 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [332200271] [2025-03-04 16:19:50,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [332200271] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:50,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1701040537] [2025-03-04 16:19:50,816 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,816 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:50,816 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,816 INFO L85 PathProgramCache]: Analyzing trace with hash -1431657590, now seen corresponding path program 2 times [2025-03-04 16:19:50,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1032167571] [2025-03-04 16:19:50,816 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:50,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,822 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:50,825 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:50,829 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:50,829 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,893 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,893 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,894 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1032167571] [2025-03-04 16:19:50,894 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1032167571] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,894 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,894 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:50,894 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [261457353] [2025-03-04 16:19:50,894 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,894 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:50,895 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:50,895 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:50,895 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:50,895 INFO L87 Difference]: Start difference. First operand 184 states and 265 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:50,907 INFO L93 Difference]: Finished difference Result 184 states and 264 transitions. [2025-03-04 16:19:50,908 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 184 states and 264 transitions. [2025-03-04 16:19:50,909 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,910 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 184 states to 184 states and 264 transitions. [2025-03-04 16:19:50,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 184 [2025-03-04 16:19:50,911 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 184 [2025-03-04 16:19:50,911 INFO L73 IsDeterministic]: Start isDeterministic. Operand 184 states and 264 transitions. [2025-03-04 16:19:50,912 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:50,912 INFO L218 hiAutomatonCegarLoop]: Abstraction has 184 states and 264 transitions. [2025-03-04 16:19:50,913 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states and 264 transitions. [2025-03-04 16:19:50,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 184. [2025-03-04 16:19:50,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 184 states, 184 states have (on average 1.434782608695652) internal successors, (264), 183 states have internal predecessors, (264), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:50,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 264 transitions. [2025-03-04 16:19:50,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 184 states and 264 transitions. [2025-03-04 16:19:50,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:50,924 INFO L432 stractBuchiCegarLoop]: Abstraction has 184 states and 264 transitions. [2025-03-04 16:19:50,926 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:19:50,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 184 states and 264 transitions. [2025-03-04 16:19:50,927 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 151 [2025-03-04 16:19:50,927 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:50,927 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:50,928 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,928 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:50,928 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:50,928 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume 1 == ~P_1_pc~0;" "assume 1 == ~P_1_ev~0;is_P_1_triggered_~__retres1~0#1 := 1;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:50,929 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,929 INFO L85 PathProgramCache]: Analyzing trace with hash -837893951, now seen corresponding path program 1 times [2025-03-04 16:19:50,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [555727071] [2025-03-04 16:19:50,929 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:50,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,935 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:50,940 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:50,940 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:50,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:50,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:50,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:50,976 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [555727071] [2025-03-04 16:19:50,976 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [555727071] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:50,976 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:50,976 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:50,976 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1275558274] [2025-03-04 16:19:50,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:50,976 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:50,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:50,976 INFO L85 PathProgramCache]: Analyzing trace with hash -1431657590, now seen corresponding path program 3 times [2025-03-04 16:19:50,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:50,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [302456934] [2025-03-04 16:19:50,976 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:50,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:50,981 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:50,984 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:50,986 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:50,986 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [302456934] [2025-03-04 16:19:51,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [302456934] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1123449885] [2025-03-04 16:19:51,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,029 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,029 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:51,030 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:51,030 INFO L87 Difference]: Start difference. First operand 184 states and 264 transitions. cyclomatic complexity: 81 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 3 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:51,071 INFO L93 Difference]: Finished difference Result 329 states and 468 transitions. [2025-03-04 16:19:51,072 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 329 states and 468 transitions. [2025-03-04 16:19:51,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 297 [2025-03-04 16:19:51,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 329 states to 329 states and 468 transitions. [2025-03-04 16:19:51,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 329 [2025-03-04 16:19:51,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 329 [2025-03-04 16:19:51,076 INFO L73 IsDeterministic]: Start isDeterministic. Operand 329 states and 468 transitions. [2025-03-04 16:19:51,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:51,082 INFO L218 hiAutomatonCegarLoop]: Abstraction has 329 states and 468 transitions. [2025-03-04 16:19:51,082 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states and 468 transitions. [2025-03-04 16:19:51,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 325. [2025-03-04 16:19:51,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 325 states, 325 states have (on average 1.4246153846153846) internal successors, (463), 324 states have internal predecessors, (463), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 325 states to 325 states and 463 transitions. [2025-03-04 16:19:51,095 INFO L240 hiAutomatonCegarLoop]: Abstraction has 325 states and 463 transitions. [2025-03-04 16:19:51,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:51,098 INFO L432 stractBuchiCegarLoop]: Abstraction has 325 states and 463 transitions. [2025-03-04 16:19:51,098 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:19:51,099 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 325 states and 463 transitions. [2025-03-04 16:19:51,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 293 [2025-03-04 16:19:51,102 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:51,102 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:51,102 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,102 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,102 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume 1 == ~P_2_pc~0;" "assume 1 == ~P_2_ev~0;is_P_2_triggered_~__retres1~1#1 := 1;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:51,103 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:51,103 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,103 INFO L85 PathProgramCache]: Analyzing trace with hash 311778884, now seen corresponding path program 1 times [2025-03-04 16:19:51,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [481128191] [2025-03-04 16:19:51,103 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:51,115 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:51,115 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,115 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [481128191] [2025-03-04 16:19:51,143 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [481128191] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,143 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:51,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [418337586] [2025-03-04 16:19:51,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,144 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:51,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,144 INFO L85 PathProgramCache]: Analyzing trace with hash 1248281552, now seen corresponding path program 1 times [2025-03-04 16:19:51,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [687890963] [2025-03-04 16:19:51,144 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,148 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:51,154 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:51,154 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,220 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,220 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [687890963] [2025-03-04 16:19:51,220 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [687890963] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,220 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1073072882] [2025-03-04 16:19:51,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,221 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,221 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,221 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:51,221 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:51,221 INFO L87 Difference]: Start difference. First operand 325 states and 463 transitions. cyclomatic complexity: 139 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:51,310 INFO L93 Difference]: Finished difference Result 749 states and 1054 transitions. [2025-03-04 16:19:51,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 749 states and 1054 transitions. [2025-03-04 16:19:51,315 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 686 [2025-03-04 16:19:51,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 749 states to 749 states and 1054 transitions. [2025-03-04 16:19:51,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 749 [2025-03-04 16:19:51,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 749 [2025-03-04 16:19:51,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 749 states and 1054 transitions. [2025-03-04 16:19:51,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:51,322 INFO L218 hiAutomatonCegarLoop]: Abstraction has 749 states and 1054 transitions. [2025-03-04 16:19:51,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 749 states and 1054 transitions. [2025-03-04 16:19:51,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 749 to 575. [2025-03-04 16:19:51,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 575 states, 575 states have (on average 1.4156521739130434) internal successors, (814), 574 states have internal predecessors, (814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 575 states to 575 states and 814 transitions. [2025-03-04 16:19:51,341 INFO L240 hiAutomatonCegarLoop]: Abstraction has 575 states and 814 transitions. [2025-03-04 16:19:51,341 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:19:51,342 INFO L432 stractBuchiCegarLoop]: Abstraction has 575 states and 814 transitions. [2025-03-04 16:19:51,342 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:19:51,342 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 575 states and 814 transitions. [2025-03-04 16:19:51,344 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2025-03-04 16:19:51,344 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:51,344 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:51,345 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,345 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,345 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:51,345 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume 1 == ~C_1_pc~0;" "assume 1 == ~e~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:51,348 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,349 INFO L85 PathProgramCache]: Analyzing trace with hash -239789561, now seen corresponding path program 1 times [2025-03-04 16:19:51,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488761216] [2025-03-04 16:19:51,349 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,349 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,353 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:19:51,359 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:19:51,360 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,360 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488761216] [2025-03-04 16:19:51,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488761216] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,389 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:19:51,389 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648032624] [2025-03-04 16:19:51,389 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,390 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:51,390 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,390 INFO L85 PathProgramCache]: Analyzing trace with hash 1248281552, now seen corresponding path program 2 times [2025-03-04 16:19:51,390 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,390 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1548674469] [2025-03-04 16:19:51,390 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:51,390 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,394 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:51,396 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:51,396 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:51,396 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,425 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,425 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1548674469] [2025-03-04 16:19:51,425 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1548674469] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,425 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,425 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,425 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505731106] [2025-03-04 16:19:51,425 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,425 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,426 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:19:51,426 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:19:51,426 INFO L87 Difference]: Start difference. First operand 575 states and 814 transitions. cyclomatic complexity: 240 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:51,522 INFO L93 Difference]: Finished difference Result 1340 states and 1860 transitions. [2025-03-04 16:19:51,522 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1340 states and 1860 transitions. [2025-03-04 16:19:51,529 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1286 [2025-03-04 16:19:51,534 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1340 states to 1340 states and 1860 transitions. [2025-03-04 16:19:51,534 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1340 [2025-03-04 16:19:51,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1340 [2025-03-04 16:19:51,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1340 states and 1860 transitions. [2025-03-04 16:19:51,536 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:51,537 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1340 states and 1860 transitions. [2025-03-04 16:19:51,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1340 states and 1860 transitions. [2025-03-04 16:19:51,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1340 to 1046. [2025-03-04 16:19:51,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1046 states, 1046 states have (on average 1.4005736137667304) internal successors, (1465), 1045 states have internal predecessors, (1465), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,550 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1046 states to 1046 states and 1465 transitions. [2025-03-04 16:19:51,550 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1046 states and 1465 transitions. [2025-03-04 16:19:51,551 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:19:51,551 INFO L432 stractBuchiCegarLoop]: Abstraction has 1046 states and 1465 transitions. [2025-03-04 16:19:51,551 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:19:51,551 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1046 states and 1465 transitions. [2025-03-04 16:19:51,555 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1016 [2025-03-04 16:19:51,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:51,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:51,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,556 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume 2 == ~C_1_pc~0;" "assume 1 == ~C_1_ev~0;is_C_1_triggered_~__retres1~2#1 := 1;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:51,556 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:51,558 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,558 INFO L85 PathProgramCache]: Analyzing trace with hash 324525047, now seen corresponding path program 1 times [2025-03-04 16:19:51,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [593885462] [2025-03-04 16:19:51,558 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,558 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,562 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:51,564 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:51,564 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,564 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [593885462] [2025-03-04 16:19:51,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [593885462] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:51,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [722811207] [2025-03-04 16:19:51,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,602 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:19:51,602 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,602 INFO L85 PathProgramCache]: Analyzing trace with hash 380573768, now seen corresponding path program 1 times [2025-03-04 16:19:51,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [692563806] [2025-03-04 16:19:51,602 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,605 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:19:51,607 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:19:51,607 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,607 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,638 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,638 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,638 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [692563806] [2025-03-04 16:19:51,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [692563806] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [619906080] [2025-03-04 16:19:51,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,638 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,639 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:51,639 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:51,639 INFO L87 Difference]: Start difference. First operand 1046 states and 1465 transitions. cyclomatic complexity: 420 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:51,680 INFO L93 Difference]: Finished difference Result 1557 states and 2154 transitions. [2025-03-04 16:19:51,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1557 states and 2154 transitions. [2025-03-04 16:19:51,690 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1528 [2025-03-04 16:19:51,697 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1557 states to 1557 states and 2154 transitions. [2025-03-04 16:19:51,698 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1557 [2025-03-04 16:19:51,717 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1557 [2025-03-04 16:19:51,717 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1557 states and 2154 transitions. [2025-03-04 16:19:51,718 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:51,718 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1557 states and 2154 transitions. [2025-03-04 16:19:51,719 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1557 states and 2154 transitions. [2025-03-04 16:19:51,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1557 to 1525. [2025-03-04 16:19:51,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1525 states, 1525 states have (on average 1.3862295081967213) internal successors, (2114), 1524 states have internal predecessors, (2114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1525 states to 1525 states and 2114 transitions. [2025-03-04 16:19:51,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1525 states and 2114 transitions. [2025-03-04 16:19:51,742 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:51,744 INFO L432 stractBuchiCegarLoop]: Abstraction has 1525 states and 2114 transitions. [2025-03-04 16:19:51,744 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:19:51,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1525 states and 2114 transitions. [2025-03-04 16:19:51,749 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1496 [2025-03-04 16:19:51,749 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:51,749 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:51,750 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,750 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,750 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:51,750 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:51,750 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,750 INFO L85 PathProgramCache]: Analyzing trace with hash 1154770426, now seen corresponding path program 1 times [2025-03-04 16:19:51,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,750 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [912914822] [2025-03-04 16:19:51,750 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,750 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,757 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:51,761 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:51,761 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,761 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:51,761 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:51,764 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:51,770 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:51,770 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:51,789 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:51,790 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,790 INFO L85 PathProgramCache]: Analyzing trace with hash 380573768, now seen corresponding path program 2 times [2025-03-04 16:19:51,790 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,790 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1213141392] [2025-03-04 16:19:51,790 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:51,790 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,794 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:19:51,797 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:19:51,797 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:51,797 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,826 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,826 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,826 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1213141392] [2025-03-04 16:19:51,826 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1213141392] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1874191593] [2025-03-04 16:19:51,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,827 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,827 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,827 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:51,827 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:51,827 INFO L87 Difference]: Start difference. First operand 1525 states and 2114 transitions. cyclomatic complexity: 590 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,872 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:51,873 INFO L93 Difference]: Finished difference Result 1609 states and 2198 transitions. [2025-03-04 16:19:51,873 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1609 states and 2198 transitions. [2025-03-04 16:19:51,879 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1580 [2025-03-04 16:19:51,884 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1609 states to 1609 states and 2198 transitions. [2025-03-04 16:19:51,884 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1609 [2025-03-04 16:19:51,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1609 [2025-03-04 16:19:51,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1609 states and 2198 transitions. [2025-03-04 16:19:51,887 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:51,887 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1609 states and 2198 transitions. [2025-03-04 16:19:51,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1609 states and 2198 transitions. [2025-03-04 16:19:51,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1609 to 1561. [2025-03-04 16:19:51,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1561 states, 1561 states have (on average 1.3773222293401666) internal successors, (2150), 1560 states have internal predecessors, (2150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:51,904 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1561 states to 1561 states and 2150 transitions. [2025-03-04 16:19:51,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1561 states and 2150 transitions. [2025-03-04 16:19:51,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:51,907 INFO L432 stractBuchiCegarLoop]: Abstraction has 1561 states and 2150 transitions. [2025-03-04 16:19:51,907 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:19:51,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1561 states and 2150 transitions. [2025-03-04 16:19:51,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1532 [2025-03-04 16:19:51,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:51,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:51,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:51,914 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:51,915 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume 0 != activate_threads_~tmp~1#1;~P_1_st~0 := 0;" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:51,915 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,915 INFO L85 PathProgramCache]: Analyzing trace with hash 1154770426, now seen corresponding path program 2 times [2025-03-04 16:19:51,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724134418] [2025-03-04 16:19:51,915 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:51,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,921 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:51,922 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:51,922 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:51,922 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:51,923 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:51,924 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:51,928 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:51,928 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,928 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:51,934 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:51,934 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:51,934 INFO L85 PathProgramCache]: Analyzing trace with hash 1865109969, now seen corresponding path program 1 times [2025-03-04 16:19:51,934 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:51,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749902893] [2025-03-04 16:19:51,936 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:51,936 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:51,941 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-04 16:19:51,945 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-04 16:19:51,945 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:51,945 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:51,989 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:51,989 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:51,989 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749902893] [2025-03-04 16:19:51,989 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749902893] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:51,989 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:51,990 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:19:51,990 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051212678] [2025-03-04 16:19:51,990 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:51,990 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:51,990 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:51,990 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:19:51,990 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:19:51,990 INFO L87 Difference]: Start difference. First operand 1561 states and 2150 transitions. cyclomatic complexity: 590 Second operand has 5 states, 5 states have (on average 9.0) internal successors, (45), 5 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,045 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:52,046 INFO L93 Difference]: Finished difference Result 1615 states and 2185 transitions. [2025-03-04 16:19:52,046 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1615 states and 2185 transitions. [2025-03-04 16:19:52,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1586 [2025-03-04 16:19:52,075 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1615 states to 1615 states and 2185 transitions. [2025-03-04 16:19:52,075 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1615 [2025-03-04 16:19:52,076 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1615 [2025-03-04 16:19:52,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1615 states and 2185 transitions. [2025-03-04 16:19:52,078 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:52,078 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1615 states and 2185 transitions. [2025-03-04 16:19:52,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1615 states and 2185 transitions. [2025-03-04 16:19:52,091 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1615 to 1615. [2025-03-04 16:19:52,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1615 states, 1615 states have (on average 1.3529411764705883) internal successors, (2185), 1614 states have internal predecessors, (2185), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1615 states to 1615 states and 2185 transitions. [2025-03-04 16:19:52,097 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1615 states and 2185 transitions. [2025-03-04 16:19:52,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:19:52,098 INFO L432 stractBuchiCegarLoop]: Abstraction has 1615 states and 2185 transitions. [2025-03-04 16:19:52,098 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:19:52,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1615 states and 2185 transitions. [2025-03-04 16:19:52,103 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1586 [2025-03-04 16:19:52,104 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:52,104 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:52,105 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,105 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,105 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:19:52,105 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume !(0 == ~P_1_st~0);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);exists_runnable_thread_~__retres1~3#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume !(0 != eval_~tmp___2~0#1);" "havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume 0 != activate_threads_~tmp___0~1#1;~P_2_st~0 := 0;" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume 0 != activate_threads_~tmp___1~1#1;~C_1_st~0 := 0;" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~2#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~2#1);" [2025-03-04 16:19:52,106 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,106 INFO L85 PathProgramCache]: Analyzing trace with hash 1154770426, now seen corresponding path program 3 times [2025-03-04 16:19:52,106 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2132718002] [2025-03-04 16:19:52,106 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:52,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,110 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:52,112 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:52,112 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:52,112 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,112 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,118 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:19:52,123 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:19:52,127 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,127 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,130 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,132 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,133 INFO L85 PathProgramCache]: Analyzing trace with hash 1610373424, now seen corresponding path program 1 times [2025-03-04 16:19:52,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837559484] [2025-03-04 16:19:52,133 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,137 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-04 16:19:52,138 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-04 16:19:52,138 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,138 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:52,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:52,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:52,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [837559484] [2025-03-04 16:19:52,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [837559484] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:52,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:52,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:52,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1693933147] [2025-03-04 16:19:52,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:52,157 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:19:52,157 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:52,157 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:52,157 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:52,157 INFO L87 Difference]: Start difference. First operand 1615 states and 2185 transitions. cyclomatic complexity: 571 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:52,189 INFO L93 Difference]: Finished difference Result 2535 states and 3383 transitions. [2025-03-04 16:19:52,189 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2535 states and 3383 transitions. [2025-03-04 16:19:52,199 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2486 [2025-03-04 16:19:52,206 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2535 states to 2535 states and 3383 transitions. [2025-03-04 16:19:52,208 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2535 [2025-03-04 16:19:52,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2535 [2025-03-04 16:19:52,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2535 states and 3383 transitions. [2025-03-04 16:19:52,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:52,213 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2535 states and 3383 transitions. [2025-03-04 16:19:52,214 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2535 states and 3383 transitions. [2025-03-04 16:19:52,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2535 to 2535. [2025-03-04 16:19:52,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2535 states, 2535 states have (on average 1.3345167652859962) internal successors, (3383), 2534 states have internal predecessors, (3383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2535 states to 2535 states and 3383 transitions. [2025-03-04 16:19:52,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2535 states and 3383 transitions. [2025-03-04 16:19:52,246 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:52,247 INFO L432 stractBuchiCegarLoop]: Abstraction has 2535 states and 3383 transitions. [2025-03-04 16:19:52,247 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:19:52,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2535 states and 3383 transitions. [2025-03-04 16:19:52,257 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 2486 [2025-03-04 16:19:52,258 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:52,258 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:52,259 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,259 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,259 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-04 16:19:52,259 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume !(0 == ~P_2_st~0);" "assume !(0 == ~C_1_st~0);" [2025-03-04 16:19:52,260 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,260 INFO L85 PathProgramCache]: Analyzing trace with hash 1632827289, now seen corresponding path program 1 times [2025-03-04 16:19:52,260 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468588152] [2025-03-04 16:19:52,260 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,266 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,269 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,269 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,270 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,273 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,277 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,277 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,277 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,283 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,284 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,284 INFO L85 PathProgramCache]: Analyzing trace with hash -1203946994, now seen corresponding path program 1 times [2025-03-04 16:19:52,284 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,284 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1336056483] [2025-03-04 16:19:52,284 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,284 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,286 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:19:52,289 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:19:52,289 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,289 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,289 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,290 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:19:52,291 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:19:52,291 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,292 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,294 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,295 INFO L85 PathProgramCache]: Analyzing trace with hash 726766502, now seen corresponding path program 1 times [2025-03-04 16:19:52,295 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,295 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31631869] [2025-03-04 16:19:52,295 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,295 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,300 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:19:52,303 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:19:52,303 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:52,321 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:52,321 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:52,321 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [31631869] [2025-03-04 16:19:52,321 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [31631869] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:52,321 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:52,322 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:19:52,322 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [999483817] [2025-03-04 16:19:52,322 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:52,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:52,366 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:52,366 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:52,367 INFO L87 Difference]: Start difference. First operand 2535 states and 3383 transitions. cyclomatic complexity: 851 Second operand has 3 states, 3 states have (on average 13.666666666666666) internal successors, (41), 3 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:52,440 INFO L93 Difference]: Finished difference Result 4166 states and 5494 transitions. [2025-03-04 16:19:52,440 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4166 states and 5494 transitions. [2025-03-04 16:19:52,454 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 4099 [2025-03-04 16:19:52,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4166 states to 4166 states and 5494 transitions. [2025-03-04 16:19:52,468 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4166 [2025-03-04 16:19:52,470 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4166 [2025-03-04 16:19:52,471 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4166 states and 5494 transitions. [2025-03-04 16:19:52,475 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:52,475 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4166 states and 5494 transitions. [2025-03-04 16:19:52,478 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4166 states and 5494 transitions. [2025-03-04 16:19:52,522 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4166 to 4038. [2025-03-04 16:19:52,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4038 states, 4038 states have (on average 1.3209509658246656) internal successors, (5334), 4037 states have internal predecessors, (5334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4038 states to 4038 states and 5334 transitions. [2025-03-04 16:19:52,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4038 states and 5334 transitions. [2025-03-04 16:19:52,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:52,541 INFO L432 stractBuchiCegarLoop]: Abstraction has 4038 states and 5334 transitions. [2025-03-04 16:19:52,542 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:19:52,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4038 states and 5334 transitions. [2025-03-04 16:19:52,554 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 3971 [2025-03-04 16:19:52,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:52,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:52,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,559 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-04 16:19:52,559 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume !(0 == ~C_1_st~0);" [2025-03-04 16:19:52,560 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,561 INFO L85 PathProgramCache]: Analyzing trace with hash 1632827289, now seen corresponding path program 2 times [2025-03-04 16:19:52,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1227506074] [2025-03-04 16:19:52,561 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:19:52,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,566 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,568 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,568 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:19:52,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,569 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,571 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,573 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,573 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,573 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,583 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,583 INFO L85 PathProgramCache]: Analyzing trace with hash 1332350377, now seen corresponding path program 1 times [2025-03-04 16:19:52,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2073809276] [2025-03-04 16:19:52,583 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,585 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 16:19:52,586 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 16:19:52,586 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,586 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,588 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 16:19:52,589 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 16:19:52,590 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,590 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,592 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,593 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1054926609, now seen corresponding path program 1 times [2025-03-04 16:19:52,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1969830612] [2025-03-04 16:19:52,594 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,598 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:19:52,600 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:19:52,601 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,601 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:19:52,619 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:19:52,620 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:19:52,620 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1969830612] [2025-03-04 16:19:52,620 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1969830612] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:19:52,620 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:19:52,620 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:19:52,620 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [613290745] [2025-03-04 16:19:52,620 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:19:52,660 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:19:52,661 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:19:52,661 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:19:52,661 INFO L87 Difference]: Start difference. First operand 4038 states and 5334 transitions. cyclomatic complexity: 1299 Second operand has 3 states, 2 states have (on average 21.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:19:52,725 INFO L93 Difference]: Finished difference Result 7028 states and 9196 transitions. [2025-03-04 16:19:52,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7028 states and 9196 transitions. [2025-03-04 16:19:52,757 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6925 [2025-03-04 16:19:52,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7028 states to 7028 states and 9196 transitions. [2025-03-04 16:19:52,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7028 [2025-03-04 16:19:52,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7028 [2025-03-04 16:19:52,791 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7028 states and 9196 transitions. [2025-03-04 16:19:52,799 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:19:52,800 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7028 states and 9196 transitions. [2025-03-04 16:19:52,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7028 states and 9196 transitions. [2025-03-04 16:19:52,877 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7028 to 7028. [2025-03-04 16:19:52,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7028 states, 7028 states have (on average 1.3084803642572567) internal successors, (9196), 7027 states have internal predecessors, (9196), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:19:52,903 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7028 states to 7028 states and 9196 transitions. [2025-03-04 16:19:52,904 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7028 states and 9196 transitions. [2025-03-04 16:19:52,904 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:19:52,904 INFO L432 stractBuchiCegarLoop]: Abstraction has 7028 states and 9196 transitions. [2025-03-04 16:19:52,905 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:19:52,905 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7028 states and 9196 transitions. [2025-03-04 16:19:52,926 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 6925 [2025-03-04 16:19:52,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:19:52,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:19:52,927 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,927 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:19:52,927 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(13, 2);call #Ultimate.allocInit(12, 3);~max_loop~0 := 0;~num~0 := 0;~i~0 := 0;~e~0 := 0;~timer~0 := 0;~data_0~0 := 0;~data_1~0 := 0;~P_1_pc~0 := 0;~P_1_st~0 := 0;~P_1_i~0 := 0;~P_1_ev~0 := 0;~P_2_pc~0 := 0;~P_2_st~0 := 0;~P_2_i~0 := 0;~P_2_ev~0 := 0;~C_1_pc~0 := 0;~C_1_st~0 := 0;~C_1_i~0 := 0;~C_1_ev~0 := 0;~C_1_pr~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~1#1;havoc main_~count~0#1;havoc main_~__retres2~1#1;~num~0 := 0;~i~0 := 0;~max_loop~0 := 2;~timer~0 := 0;~P_1_pc~0 := 0;~P_2_pc~0 := 0;~C_1_pc~0 := 0;main_~count~0#1 := 0;assume { :begin_inline_init_model } true;~P_1_i~0 := 1;~P_2_i~0 := 1;~C_1_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~2#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~2#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~P_1_i~0;~P_1_st~0 := 0;" "assume 1 == ~P_2_i~0;~P_2_st~0 := 0;" "assume 1 == ~C_1_i~0;~C_1_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp___1~1#1;assume { :begin_inline_is_P_1_triggered } true;havoc is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;havoc is_P_1_triggered_~__retres1~0#1;" "assume !(1 == ~P_1_pc~0);" "is_P_1_triggered_~__retres1~0#1 := 0;" "is_P_1_triggered_#res#1 := is_P_1_triggered_~__retres1~0#1;" "activate_threads_#t~ret9#1 := is_P_1_triggered_#res#1;havoc is_P_1_triggered_~__retres1~0#1;assume { :end_inline_is_P_1_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret9#1;havoc activate_threads_#t~ret9#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_P_2_triggered } true;havoc is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;havoc is_P_2_triggered_~__retres1~1#1;" "assume !(1 == ~P_2_pc~0);" "is_P_2_triggered_~__retres1~1#1 := 0;" "is_P_2_triggered_#res#1 := is_P_2_triggered_~__retres1~1#1;" "activate_threads_#t~ret10#1 := is_P_2_triggered_#res#1;havoc is_P_2_triggered_~__retres1~1#1;assume { :end_inline_is_P_2_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret10#1;havoc activate_threads_#t~ret10#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "assume { :begin_inline_is_C_1_triggered } true;havoc is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;havoc is_C_1_triggered_~__retres1~2#1;" "assume !(1 == ~C_1_pc~0);" "assume !(2 == ~C_1_pc~0);" "is_C_1_triggered_~__retres1~2#1 := 0;" "is_C_1_triggered_#res#1 := is_C_1_triggered_~__retres1~2#1;" "activate_threads_#t~ret11#1 := is_C_1_triggered_#res#1;havoc is_C_1_triggered_~__retres1~2#1;assume { :end_inline_is_C_1_triggered } true;activate_threads_~tmp___1~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1;" "assume !(0 != activate_threads_~tmp___1~1#1);" "havoc activate_threads_#t~ret9#1, activate_threads_#t~ret10#1, activate_threads_#t~ret11#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1, activate_threads_~tmp___1~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;" [2025-03-04 16:19:52,927 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;havoc exists_runnable_thread_~__retres1~3#1;" "assume 0 == ~P_1_st~0;exists_runnable_thread_~__retres1~3#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~3#1;" "eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~3#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___2~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1;" "assume 0 != eval_~tmp___2~0#1;" "assume 0 == ~P_1_st~0;havoc eval_#t~nondet6#1;eval_~tmp~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1;" "assume !(0 != eval_~tmp~0#1);" "assume 0 == ~P_2_st~0;havoc eval_#t~nondet7#1;eval_~tmp___0~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1;" "assume !(0 != eval_~tmp___0~0#1);" "assume 0 == ~C_1_st~0;havoc eval_#t~nondet8#1;eval_~tmp___1~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1;" "assume !(0 != eval_~tmp___1~0#1);" [2025-03-04 16:19:52,927 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,927 INFO L85 PathProgramCache]: Analyzing trace with hash 1632827289, now seen corresponding path program 3 times [2025-03-04 16:19:52,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1101780352] [2025-03-04 16:19:52,928 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:19:52,928 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,932 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,934 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,934 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:19:52,934 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,934 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,935 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:52,937 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:52,937 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,937 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,943 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,943 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,943 INFO L85 PathProgramCache]: Analyzing trace with hash -1646811112, now seen corresponding path program 1 times [2025-03-04 16:19:52,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691770302] [2025-03-04 16:19:52,943 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,944 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,947 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-04 16:19:52,948 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-04 16:19:52,948 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,948 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,948 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,949 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 12 statements into 1 equivalence classes. [2025-03-04 16:19:52,950 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 12 of 12 statements. [2025-03-04 16:19:52,950 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,950 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,951 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:52,951 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:19:52,952 INFO L85 PathProgramCache]: Analyzing trace with hash -1657013328, now seen corresponding path program 1 times [2025-03-04 16:19:52,952 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:19:52,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [797132353] [2025-03-04 16:19:52,953 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:19:52,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:19:52,957 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:19:52,960 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:19:52,960 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,960 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,960 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:52,962 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:19:52,964 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:19:52,964 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:52,964 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:52,970 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:19:53,603 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:53,606 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:53,606 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:53,606 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:53,606 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:19:53,613 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:19:53,616 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:19:53,616 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:19:53,617 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:19:53,692 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:19:53 BoogieIcfgContainer [2025-03-04 16:19:53,692 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:19:53,693 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:19:53,693 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:19:53,693 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:19:53,694 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:19:50" (3/4) ... [2025-03-04 16:19:53,695 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 16:19:53,741 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 16:19:53,741 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:19:53,741 INFO L158 Benchmark]: Toolchain (without parser) took 4429.27ms. Allocated memory was 142.6MB in the beginning and 302.0MB in the end (delta: 159.4MB). Free memory was 106.5MB in the beginning and 151.2MB in the end (delta: -44.7MB). Peak memory consumption was 110.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 128.5MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: CACSL2BoogieTranslator took 227.72ms. Allocated memory is still 142.6MB. Free memory was 106.5MB in the beginning and 91.9MB in the end (delta: 14.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: Boogie Procedure Inliner took 40.78ms. Allocated memory is still 142.6MB. Free memory was 91.9MB in the beginning and 89.8MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: Boogie Preprocessor took 33.22ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 87.9MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: IcfgBuilder took 533.81ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 56.3MB in the end (delta: 31.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. [2025-03-04 16:19:53,742 INFO L158 Benchmark]: BuchiAutomizer took 3541.79ms. Allocated memory was 142.6MB in the beginning and 302.0MB in the end (delta: 159.4MB). Free memory was 56.3MB in the beginning and 159.6MB in the end (delta: -103.2MB). Peak memory consumption was 51.7MB. Max. memory is 16.1GB. [2025-03-04 16:19:53,743 INFO L158 Benchmark]: Witness Printer took 48.09ms. Allocated memory is still 302.0MB. Free memory was 159.6MB in the beginning and 151.2MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:19:53,744 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24ms. Allocated memory is still 201.3MB. Free memory is still 128.5MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 227.72ms. Allocated memory is still 142.6MB. Free memory was 106.5MB in the beginning and 91.9MB in the end (delta: 14.6MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 40.78ms. Allocated memory is still 142.6MB. Free memory was 91.9MB in the beginning and 89.8MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 33.22ms. Allocated memory is still 142.6MB. Free memory was 89.8MB in the beginning and 87.9MB in the end (delta: 2.0MB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 533.81ms. Allocated memory is still 142.6MB. Free memory was 87.9MB in the beginning and 56.3MB in the end (delta: 31.5MB). Peak memory consumption was 33.6MB. Max. memory is 16.1GB. * BuchiAutomizer took 3541.79ms. Allocated memory was 142.6MB in the beginning and 302.0MB in the end (delta: 159.4MB). Free memory was 56.3MB in the beginning and 159.6MB in the end (delta: -103.2MB). Peak memory consumption was 51.7MB. Max. memory is 16.1GB. * Witness Printer took 48.09ms. Allocated memory is still 302.0MB. Free memory was 159.6MB in the beginning and 151.2MB in the end (delta: 8.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 12 terminating modules (12 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.12 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 7028 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 3.4s and 13 iterations. TraceHistogramMax:1. Analysis of lassos took 2.0s. Construction of modules took 0.2s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 0. Minimization of det autom 12. Minimization of nondet autom 0. Automata minimization 0.3s AutomataMinimizationTime, 12 MinimizatonAttempts, 680 StatesRemovedByMinimization, 6 NontrivialMinimizations. Non-live state removal took 0.2s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 2998 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 2998 mSDsluCounter, 6344 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 3315 mSDsCounter, 108 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 302 IncrementalHoareTripleChecker+Invalid, 410 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 108 mSolverCounterUnsat, 3029 mSDtfsCounter, 302 mSolverCounterSat, 0.1s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc2 concLT0 SILN0 SILU0 SILI7 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 356]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 356]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int max_loop ; [L26] int num ; [L27] int i ; [L28] int e ; [L29] int timer ; [L30] char data_0 ; [L31] char data_1 ; [L74] int P_1_pc; [L75] int P_1_st ; [L76] int P_1_i ; [L77] int P_1_ev ; [L132] int P_2_pc ; [L133] int P_2_st ; [L134] int P_2_i ; [L135] int P_2_ev ; [L200] int C_1_pc ; [L201] int C_1_st ; [L202] int C_1_i ; [L203] int C_1_ev ; [L204] int C_1_pr ; VAL [C_1_ev=0, C_1_i=0, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=0, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=0, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=0, num=0, timer=0] [L603] int count ; [L604] int __retres2 ; [L608] num = 0 [L609] i = 0 [L610] max_loop = 2 [L612] timer = 0 [L613] P_1_pc = 0 [L614] P_2_pc = 0 [L615] C_1_pc = 0 [L617] count = 0 [L618] CALL init_model() [L595] P_1_i = 1 [L596] P_2_i = 1 [L597] C_1_i = 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L618] RET init_model() [L619] CALL start_simulation() [L533] int kernel_st ; [L534] int tmp ; [L535] int tmp___0 ; [L539] kernel_st = 0 [L540] FCALL update_channels() [L541] CALL init_threads() [L304] COND TRUE (int )P_1_i == 1 [L305] P_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L309] COND TRUE (int )P_2_i == 1 [L310] P_2_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L314] COND TRUE (int )C_1_i == 1 [L315] C_1_st = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L541] RET init_threads() [L542] FCALL fire_delta_events() [L543] CALL activate_threads() [L469] int tmp ; [L470] int tmp___0 ; [L471] int tmp___1 ; [L475] CALL, EXPR is_P_1_triggered() [L114] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L117] COND FALSE !((int )P_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L127] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L129] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L475] RET, EXPR is_P_1_triggered() [L475] tmp = is_P_1_triggered() [L477] COND FALSE !(\read(tmp)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] CALL, EXPR is_P_2_triggered() [L182] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L185] COND FALSE !((int )P_2_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L195] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L197] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L483] RET, EXPR is_P_2_triggered() [L483] tmp___0 = is_P_2_triggered() [L485] COND FALSE !(\read(tmp___0)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] CALL, EXPR is_C_1_triggered() [L264] int __retres1 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L267] COND FALSE !((int )C_1_pc == 1) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L277] COND FALSE !((int )C_1_pc == 2) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L287] __retres1 = 0 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, __retres1=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L289] return (__retres1); VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, \result=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L491] RET, EXPR is_C_1_triggered() [L491] tmp___1 = is_C_1_triggered() [L493] COND FALSE !(\read(tmp___1)) VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L543] RET activate_threads() [L544] FCALL reset_delta_events() [L547] COND TRUE 1 VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] [L550] kernel_st = 1 [L551] CALL eval() [L349] int tmp ; [L350] int tmp___0 ; [L351] int tmp___1 ; [L352] int tmp___2 ; VAL [C_1_ev=0, C_1_i=1, C_1_pc=0, C_1_pr=0, C_1_st=0, P_1_ev=0, P_1_i=1, P_1_pc=0, P_1_st=0, P_2_ev=0, P_2_i=1, P_2_pc=0, P_2_st=0, data_0=0, data_1=0, e=0, i=0, max_loop=2, num=0, timer=0] Loop: [L356] COND TRUE 1 [L359] CALL, EXPR exists_runnable_thread() [L324] int __retres1 ; [L327] COND TRUE (int )P_1_st == 0 [L328] __retres1 = 1 [L345] return (__retres1); [L359] RET, EXPR exists_runnable_thread() [L359] tmp___2 = exists_runnable_thread() [L361] COND TRUE \read(tmp___2) [L366] COND TRUE (int )P_1_st == 0 [L368] tmp = __VERIFIER_nondet_int() [L370] COND FALSE !(\read(tmp)) [L381] COND TRUE (int )P_2_st == 0 [L383] tmp___0 = __VERIFIER_nondet_int() [L385] COND FALSE !(\read(tmp___0)) [L396] COND TRUE (int )C_1_st == 0 [L398] tmp___1 = __VERIFIER_nondet_int() [L400] COND FALSE !(\read(tmp___1)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 16:19:53,760 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)