./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:20:00,887 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:20:00,935 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:20:00,938 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:20:00,938 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:20:00,938 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:20:00,953 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:20:00,953 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:20:00,954 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:20:00,954 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:20:00,954 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:20:00,954 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:20:00,954 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:20:00,955 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:20:00,955 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:20:00,955 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:20:00,956 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:20:00,956 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 677126e8d6773c92cc337bfe0a3ec155f49f784424155f33a8c9c24ee0a42113 [2025-03-04 16:20:01,192 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:20:01,200 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:20:01,201 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:20:01,202 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:20:01,202 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:20:01,203 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2025-03-04 16:20:02,349 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ccbbf757/5c9916da8c5f49bda605b1fb2ab08c1d/FLAG8a0c0e146 [2025-03-04 16:20:02,634 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:20:02,635 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pc_sfifo_3.cil.c [2025-03-04 16:20:02,645 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ccbbf757/5c9916da8c5f49bda605b1fb2ab08c1d/FLAG8a0c0e146 [2025-03-04 16:20:02,930 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/0ccbbf757/5c9916da8c5f49bda605b1fb2ab08c1d [2025-03-04 16:20:02,933 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:20:02,934 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:20:02,935 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:20:02,935 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:20:02,938 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:20:02,938 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:20:02" (1/1) ... [2025-03-04 16:20:02,939 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a7971d4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:02, skipping insertion in model container [2025-03-04 16:20:02,939 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:20:02" (1/1) ... [2025-03-04 16:20:02,957 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:20:03,091 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:20:03,102 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:20:03,141 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:20:03,157 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:20:03,158 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03 WrapperNode [2025-03-04 16:20:03,158 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:20:03,159 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:20:03,159 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:20:03,159 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:20:03,164 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,172 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,196 INFO L138 Inliner]: procedures = 31, calls = 36, calls flagged for inlining = 31, calls inlined = 35, statements flattened = 398 [2025-03-04 16:20:03,197 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:20:03,198 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:20:03,198 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:20:03,198 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:20:03,203 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,204 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,206 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,222 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:20:03,222 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,223 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,231 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,235 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,240 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,241 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,243 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:20:03,247 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:20:03,247 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:20:03,247 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:20:03,252 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (1/1) ... [2025-03-04 16:20:03,256 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:03,266 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:03,276 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:03,278 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:20:03,294 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:20:03,294 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:20:03,294 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:20:03,294 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:20:03,343 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:20:03,345 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:20:03,659 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L217: do_read_c_~a~0#1 := ~a_t~0; [2025-03-04 16:20:03,659 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L218: assume 1 == ~q_free~0;~c_dr_st~0 := 2;~c_dr_pc~0 := 2;~a_t~0 := do_read_c_~a~0#1; [2025-03-04 16:20:03,659 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L218: assume !(1 == ~q_free~0); [2025-03-04 16:20:03,676 INFO L? ?]: Removed 54 outVars from TransFormulas that were not future-live. [2025-03-04 16:20:03,676 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:20:03,686 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:20:03,688 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:20:03,688 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:20:03 BoogieIcfgContainer [2025-03-04 16:20:03,689 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:20:03,690 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:20:03,690 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:20:03,694 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:20:03,695 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:03,695 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:20:02" (1/3) ... [2025-03-04 16:20:03,696 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@67849cfe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:20:03, skipping insertion in model container [2025-03-04 16:20:03,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:03,696 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:03" (2/3) ... [2025-03-04 16:20:03,696 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@67849cfe and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:20:03, skipping insertion in model container [2025-03-04 16:20:03,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:03,697 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:20:03" (3/3) ... [2025-03-04 16:20:03,698 INFO L363 chiAutomizerObserver]: Analyzing ICFG pc_sfifo_3.cil.c [2025-03-04 16:20:03,731 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:20:03,732 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:20:03,732 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:20:03,732 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:20:03,732 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:20:03,732 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:20:03,732 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:20:03,732 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:20:03,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 146 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 145 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:03,752 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2025-03-04 16:20:03,752 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:03,752 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:03,760 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:03,760 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:03,760 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:20:03,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 146 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 145 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:03,766 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 106 [2025-03-04 16:20:03,766 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:03,766 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:03,768 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:03,768 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:03,772 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~p_dw_i~0);~p_dw_st~0 := 2;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:03,772 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume !true;" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:03,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:03,776 INFO L85 PathProgramCache]: Analyzing trace with hash -1859495649, now seen corresponding path program 1 times [2025-03-04 16:20:03,781 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:03,781 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1183085615] [2025-03-04 16:20:03,781 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:03,782 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:03,835 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:20:03,852 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:20:03,852 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:03,852 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:03,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:03,941 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:03,941 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1183085615] [2025-03-04 16:20:03,942 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1183085615] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:03,942 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:03,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:03,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1455069102] [2025-03-04 16:20:03,944 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:03,946 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:03,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:03,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1524693563, now seen corresponding path program 1 times [2025-03-04 16:20:03,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:03,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1474417149] [2025-03-04 16:20:03,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:03,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:03,959 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 36 statements into 1 equivalence classes. [2025-03-04 16:20:03,960 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 36 of 36 statements. [2025-03-04 16:20:03,960 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:03,960 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:03,978 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:03,979 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:03,979 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1474417149] [2025-03-04 16:20:03,979 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1474417149] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:03,979 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:03,979 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:20:03,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804426344] [2025-03-04 16:20:03,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:03,981 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:03,982 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:04,001 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:04,002 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:04,003 INFO L87 Difference]: Start difference. First operand has 146 states, 145 states have (on average 1.5172413793103448) internal successors, (220), 145 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:04,028 INFO L93 Difference]: Finished difference Result 142 states and 209 transitions. [2025-03-04 16:20:04,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 142 states and 209 transitions. [2025-03-04 16:20:04,034 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:20:04,042 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 142 states to 136 states and 203 transitions. [2025-03-04 16:20:04,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2025-03-04 16:20:04,043 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2025-03-04 16:20:04,043 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 203 transitions. [2025-03-04 16:20:04,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:04,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 136 states and 203 transitions. [2025-03-04 16:20:04,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 203 transitions. [2025-03-04 16:20:04,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2025-03-04 16:20:04,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.4926470588235294) internal successors, (203), 135 states have internal predecessors, (203), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,075 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 203 transitions. [2025-03-04 16:20:04,076 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 203 transitions. [2025-03-04 16:20:04,078 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:04,081 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 203 transitions. [2025-03-04 16:20:04,081 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:20:04,081 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 203 transitions. [2025-03-04 16:20:04,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:20:04,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:04,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:04,083 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,083 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,087 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume !(1 == ~c_dr_i~0);~c_dr_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:04,087 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:04,088 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,088 INFO L85 PathProgramCache]: Analyzing trace with hash -2070846562, now seen corresponding path program 1 times [2025-03-04 16:20:04,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,088 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2087354295] [2025-03-04 16:20:04,088 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,088 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,097 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:20:04,106 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:20:04,106 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,106 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2087354295] [2025-03-04 16:20:04,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2087354295] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:04,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [154775323] [2025-03-04 16:20:04,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,156 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:04,156 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,156 INFO L85 PathProgramCache]: Analyzing trace with hash -1296593156, now seen corresponding path program 1 times [2025-03-04 16:20:04,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1595170953] [2025-03-04 16:20:04,156 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,161 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:04,172 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:04,173 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,173 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,218 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,219 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,219 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1595170953] [2025-03-04 16:20:04,219 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1595170953] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,219 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,219 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:04,219 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [491005987] [2025-03-04 16:20:04,219 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,219 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:04,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:04,220 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:04,220 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:04,220 INFO L87 Difference]: Start difference. First operand 136 states and 203 transitions. cyclomatic complexity: 68 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,232 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:04,235 INFO L93 Difference]: Finished difference Result 136 states and 202 transitions. [2025-03-04 16:20:04,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 136 states and 202 transitions. [2025-03-04 16:20:04,237 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:20:04,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 136 states to 136 states and 202 transitions. [2025-03-04 16:20:04,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 136 [2025-03-04 16:20:04,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 136 [2025-03-04 16:20:04,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 136 states and 202 transitions. [2025-03-04 16:20:04,238 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:04,238 INFO L218 hiAutomatonCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-03-04 16:20:04,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states and 202 transitions. [2025-03-04 16:20:04,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2025-03-04 16:20:04,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 136 states, 136 states have (on average 1.4852941176470589) internal successors, (202), 135 states have internal predecessors, (202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 202 transitions. [2025-03-04 16:20:04,245 INFO L240 hiAutomatonCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-03-04 16:20:04,245 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:04,246 INFO L432 stractBuchiCegarLoop]: Abstraction has 136 states and 202 transitions. [2025-03-04 16:20:04,246 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:20:04,246 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 136 states and 202 transitions. [2025-03-04 16:20:04,247 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 100 [2025-03-04 16:20:04,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:04,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:04,247 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,247 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,248 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:04,248 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume 1 == ~p_dw_pc~0;" "assume 1 == ~fast_clk_edge~0;is_do_write_p_triggered_~__retres1~0#1 := 1;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:04,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,248 INFO L85 PathProgramCache]: Analyzing trace with hash -1662022337, now seen corresponding path program 1 times [2025-03-04 16:20:04,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226763340] [2025-03-04 16:20:04,248 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,253 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 26 statements into 1 equivalence classes. [2025-03-04 16:20:04,263 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 26 of 26 statements. [2025-03-04 16:20:04,264 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,264 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,317 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226763340] [2025-03-04 16:20:04,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226763340] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:04,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1402032360] [2025-03-04 16:20:04,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,318 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:04,318 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,318 INFO L85 PathProgramCache]: Analyzing trace with hash -1296593156, now seen corresponding path program 2 times [2025-03-04 16:20:04,318 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,319 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [913314276] [2025-03-04 16:20:04,319 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:04,319 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,329 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:04,332 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:04,332 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:04,332 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,385 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,385 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,385 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [913314276] [2025-03-04 16:20:04,385 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [913314276] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,385 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,385 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:04,386 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749354109] [2025-03-04 16:20:04,386 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,386 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:04,386 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:04,386 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:04,386 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:04,386 INFO L87 Difference]: Start difference. First operand 136 states and 202 transitions. cyclomatic complexity: 67 Second operand has 3 states, 3 states have (on average 8.666666666666666) internal successors, (26), 3 states have internal predecessors, (26), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:04,461 INFO L93 Difference]: Finished difference Result 225 states and 324 transitions. [2025-03-04 16:20:04,461 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 225 states and 324 transitions. [2025-03-04 16:20:04,463 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2025-03-04 16:20:04,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 225 states to 225 states and 324 transitions. [2025-03-04 16:20:04,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 225 [2025-03-04 16:20:04,466 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 225 [2025-03-04 16:20:04,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 225 states and 324 transitions. [2025-03-04 16:20:04,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:04,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 225 states and 324 transitions. [2025-03-04 16:20:04,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states and 324 transitions. [2025-03-04 16:20:04,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 222. [2025-03-04 16:20:04,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 222 states, 222 states have (on average 1.445945945945946) internal successors, (321), 221 states have internal predecessors, (321), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 321 transitions. [2025-03-04 16:20:04,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 222 states and 321 transitions. [2025-03-04 16:20:04,479 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:04,479 INFO L432 stractBuchiCegarLoop]: Abstraction has 222 states and 321 transitions. [2025-03-04 16:20:04,479 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:20:04,480 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 222 states and 321 transitions. [2025-03-04 16:20:04,481 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 187 [2025-03-04 16:20:04,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:04,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:04,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,481 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,482 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:04,482 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume 1 == ~c_dr_pc~0;" "assume 1 == ~slow_clk_edge~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:04,482 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,482 INFO L85 PathProgramCache]: Analyzing trace with hash -619888774, now seen corresponding path program 1 times [2025-03-04 16:20:04,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,483 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1006938635] [2025-03-04 16:20:04,483 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,489 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-04 16:20:04,494 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-04 16:20:04,494 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,497 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1006938635] [2025-03-04 16:20:04,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1006938635] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:04,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [808202544] [2025-03-04 16:20:04,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,542 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:04,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,543 INFO L85 PathProgramCache]: Analyzing trace with hash -387989650, now seen corresponding path program 1 times [2025-03-04 16:20:04,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854599215] [2025-03-04 16:20:04,545 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,549 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:04,556 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:04,556 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,556 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,608 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,608 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,609 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854599215] [2025-03-04 16:20:04,609 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854599215] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,609 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,609 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:04,609 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [943832813] [2025-03-04 16:20:04,609 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,610 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:04,610 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:04,611 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:04,611 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:04,611 INFO L87 Difference]: Start difference. First operand 222 states and 321 transitions. cyclomatic complexity: 101 Second operand has 4 states, 4 states have (on average 6.75) internal successors, (27), 4 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:04,705 INFO L93 Difference]: Finished difference Result 479 states and 683 transitions. [2025-03-04 16:20:04,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 479 states and 683 transitions. [2025-03-04 16:20:04,708 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 431 [2025-03-04 16:20:04,710 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 479 states to 479 states and 683 transitions. [2025-03-04 16:20:04,710 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 479 [2025-03-04 16:20:04,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 479 [2025-03-04 16:20:04,711 INFO L73 IsDeterministic]: Start isDeterministic. Operand 479 states and 683 transitions. [2025-03-04 16:20:04,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:04,712 INFO L218 hiAutomatonCegarLoop]: Abstraction has 479 states and 683 transitions. [2025-03-04 16:20:04,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 479 states and 683 transitions. [2025-03-04 16:20:04,721 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 479 to 381. [2025-03-04 16:20:04,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 381 states, 381 states have (on average 1.4383202099737533) internal successors, (548), 380 states have internal predecessors, (548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 381 states to 381 states and 548 transitions. [2025-03-04 16:20:04,723 INFO L240 hiAutomatonCegarLoop]: Abstraction has 381 states and 548 transitions. [2025-03-04 16:20:04,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:04,725 INFO L432 stractBuchiCegarLoop]: Abstraction has 381 states and 548 transitions. [2025-03-04 16:20:04,725 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:20:04,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 381 states and 548 transitions. [2025-03-04 16:20:04,726 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 346 [2025-03-04 16:20:04,727 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:04,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:04,727 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,727 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,727 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume 2 == ~c_dr_pc~0;" "assume 1 == ~q_write_ev~0;is_do_read_c_triggered_~__retres1~1#1 := 1;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:04,727 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~q_read_ev~0;~q_read_ev~0 := 1;" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~q_read_ev~0;~q_read_ev~0 := 2;" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:04,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,728 INFO L85 PathProgramCache]: Analyzing trace with hash 1634102593, now seen corresponding path program 1 times [2025-03-04 16:20:04,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,729 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119108849] [2025-03-04 16:20:04,729 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,733 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:04,738 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:04,738 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,738 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119108849] [2025-03-04 16:20:04,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119108849] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:04,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [615240042] [2025-03-04 16:20:04,767 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,767 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:04,768 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1630951933, now seen corresponding path program 1 times [2025-03-04 16:20:04,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,768 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1511241829] [2025-03-04 16:20:04,768 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,774 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:20:04,792 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:20:04,793 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,793 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:04,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:04,825 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:04,825 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1511241829] [2025-03-04 16:20:04,825 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1511241829] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:04,826 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:04,826 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:04,826 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [378507098] [2025-03-04 16:20:04,826 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:04,826 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:04,826 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:04,827 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:04,827 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:04,827 INFO L87 Difference]: Start difference. First operand 381 states and 548 transitions. cyclomatic complexity: 169 Second operand has 4 states, 4 states have (on average 7.0) internal successors, (28), 4 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:04,891 INFO L93 Difference]: Finished difference Result 562 states and 777 transitions. [2025-03-04 16:20:04,891 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 562 states and 777 transitions. [2025-03-04 16:20:04,894 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-03-04 16:20:04,898 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 562 states to 562 states and 777 transitions. [2025-03-04 16:20:04,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 562 [2025-03-04 16:20:04,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 562 [2025-03-04 16:20:04,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 562 states and 777 transitions. [2025-03-04 16:20:04,900 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:04,900 INFO L218 hiAutomatonCegarLoop]: Abstraction has 562 states and 777 transitions. [2025-03-04 16:20:04,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 562 states and 777 transitions. [2025-03-04 16:20:04,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 562 to 556. [2025-03-04 16:20:04,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 556 states, 556 states have (on average 1.3866906474820144) internal successors, (771), 555 states have internal predecessors, (771), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:04,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 556 states to 556 states and 771 transitions. [2025-03-04 16:20:04,922 INFO L240 hiAutomatonCegarLoop]: Abstraction has 556 states and 771 transitions. [2025-03-04 16:20:04,923 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:04,924 INFO L432 stractBuchiCegarLoop]: Abstraction has 556 states and 771 transitions. [2025-03-04 16:20:04,924 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:20:04,924 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 556 states and 771 transitions. [2025-03-04 16:20:04,926 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 493 [2025-03-04 16:20:04,926 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:04,926 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:04,929 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,929 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:04,929 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:04,930 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:04,930 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,931 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 1 times [2025-03-04 16:20:04,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [546207180] [2025-03-04 16:20:04,931 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,938 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:04,940 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:04,940 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,940 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:04,940 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:04,942 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:04,943 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:04,944 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,944 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:04,962 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:04,963 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:04,963 INFO L85 PathProgramCache]: Analyzing trace with hash -2133503965, now seen corresponding path program 1 times [2025-03-04 16:20:04,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:04,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1196164015] [2025-03-04 16:20:04,963 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:04,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:04,971 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 43 statements into 1 equivalence classes. [2025-03-04 16:20:04,974 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 43 of 43 statements. [2025-03-04 16:20:04,974 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:04,974 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:05,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:05,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:05,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1196164015] [2025-03-04 16:20:05,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1196164015] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:05,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:05,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:05,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280888087] [2025-03-04 16:20:05,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:05,017 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:05,017 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:05,018 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:20:05,018 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:20:05,018 INFO L87 Difference]: Start difference. First operand 556 states and 771 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:05,060 INFO L93 Difference]: Finished difference Result 598 states and 813 transitions. [2025-03-04 16:20:05,060 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 598 states and 813 transitions. [2025-03-04 16:20:05,063 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 535 [2025-03-04 16:20:05,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 598 states to 598 states and 813 transitions. [2025-03-04 16:20:05,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 598 [2025-03-04 16:20:05,066 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 598 [2025-03-04 16:20:05,066 INFO L73 IsDeterministic]: Start isDeterministic. Operand 598 states and 813 transitions. [2025-03-04 16:20:05,067 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:05,067 INFO L218 hiAutomatonCegarLoop]: Abstraction has 598 states and 813 transitions. [2025-03-04 16:20:05,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states and 813 transitions. [2025-03-04 16:20:05,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 574. [2025-03-04 16:20:05,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 574 states, 574 states have (on average 1.3745644599303135) internal successors, (789), 573 states have internal predecessors, (789), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 574 states to 574 states and 789 transitions. [2025-03-04 16:20:05,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 574 states and 789 transitions. [2025-03-04 16:20:05,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:05,078 INFO L432 stractBuchiCegarLoop]: Abstraction has 574 states and 789 transitions. [2025-03-04 16:20:05,078 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:20:05,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 574 states and 789 transitions. [2025-03-04 16:20:05,080 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 511 [2025-03-04 16:20:05,080 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:05,080 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:05,080 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,080 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,080 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:05,083 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume 0 != activate_threads_~tmp~1#1;~p_dw_st~0 := 0;" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:05,083 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,084 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 2 times [2025-03-04 16:20:05,084 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,084 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530779428] [2025-03-04 16:20:05,084 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:05,084 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,088 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:05,094 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:05,094 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:05,094 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,094 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,095 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:05,097 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:05,098 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,098 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,102 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,102 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,102 INFO L85 PathProgramCache]: Analyzing trace with hash 531232814, now seen corresponding path program 1 times [2025-03-04 16:20:05,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1764661059] [2025-03-04 16:20:05,102 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,109 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:05,113 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:05,113 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,113 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:05,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:05,159 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:05,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1764661059] [2025-03-04 16:20:05,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1764661059] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:05,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:05,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:05,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1170231144] [2025-03-04 16:20:05,159 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:05,159 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:05,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:05,159 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:20:05,159 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:20:05,160 INFO L87 Difference]: Start difference. First operand 574 states and 789 transitions. cyclomatic complexity: 219 Second operand has 5 states, 5 states have (on average 8.8) internal successors, (44), 5 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:05,211 INFO L93 Difference]: Finished difference Result 592 states and 799 transitions. [2025-03-04 16:20:05,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 592 states and 799 transitions. [2025-03-04 16:20:05,213 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2025-03-04 16:20:05,216 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 592 states to 592 states and 799 transitions. [2025-03-04 16:20:05,216 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 592 [2025-03-04 16:20:05,216 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 592 [2025-03-04 16:20:05,216 INFO L73 IsDeterministic]: Start isDeterministic. Operand 592 states and 799 transitions. [2025-03-04 16:20:05,217 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:05,217 INFO L218 hiAutomatonCegarLoop]: Abstraction has 592 states and 799 transitions. [2025-03-04 16:20:05,217 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states and 799 transitions. [2025-03-04 16:20:05,221 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 592. [2025-03-04 16:20:05,222 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 592 states, 592 states have (on average 1.349662162162162) internal successors, (799), 591 states have internal predecessors, (799), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,224 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 592 states to 592 states and 799 transitions. [2025-03-04 16:20:05,224 INFO L240 hiAutomatonCegarLoop]: Abstraction has 592 states and 799 transitions. [2025-03-04 16:20:05,224 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:05,225 INFO L432 stractBuchiCegarLoop]: Abstraction has 592 states and 799 transitions. [2025-03-04 16:20:05,225 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:20:05,225 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 592 states and 799 transitions. [2025-03-04 16:20:05,226 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 529 [2025-03-04 16:20:05,226 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:05,227 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:05,227 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,227 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,227 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:20:05,227 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume !(0 == ~p_dw_st~0);" "assume !(0 == ~c_dr_st~0);exists_runnable_thread_~__retres1~2#1 := 0;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume !(0 != eval_~tmp___1~0#1);" "havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume 0 == ~q_write_ev~0;~q_write_ev~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume 0 != activate_threads_~tmp___0~1#1;~c_dr_st~0 := 0;" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume 1 == ~q_write_ev~0;~q_write_ev~0 := 2;" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "start_simulation_#t~ret13#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~4#1 := start_simulation_#t~ret13#1;havoc start_simulation_#t~ret13#1;" "assume !(0 == start_simulation_~tmp~4#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~3#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "stop_simulation_#t~ret12#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~3#1 := stop_simulation_#t~ret12#1;havoc stop_simulation_#t~ret12#1;" "assume 0 != stop_simulation_~tmp~3#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret14#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret12#1, stop_simulation_~tmp~3#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~3#1 := start_simulation_#t~ret14#1;havoc start_simulation_#t~ret14#1;" "assume !(0 != start_simulation_~tmp___0~3#1);" [2025-03-04 16:20:05,230 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,230 INFO L85 PathProgramCache]: Analyzing trace with hash 635994756, now seen corresponding path program 3 times [2025-03-04 16:20:05,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1363336889] [2025-03-04 16:20:05,230 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:05,231 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,234 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:05,236 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:05,236 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:05,237 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,237 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,238 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 28 statements into 1 equivalence classes. [2025-03-04 16:20:05,239 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 28 of 28 statements. [2025-03-04 16:20:05,240 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,240 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,247 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,248 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,248 INFO L85 PathProgramCache]: Analyzing trace with hash 464226061, now seen corresponding path program 1 times [2025-03-04 16:20:05,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1165296563] [2025-03-04 16:20:05,248 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,254 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:05,255 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:05,255 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,255 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:05,282 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:05,282 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:05,282 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1165296563] [2025-03-04 16:20:05,282 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1165296563] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:05,282 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:05,282 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:05,282 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [671475457] [2025-03-04 16:20:05,282 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:05,283 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:05,283 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:05,283 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:05,283 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:05,283 INFO L87 Difference]: Start difference. First operand 592 states and 799 transitions. cyclomatic complexity: 211 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:05,311 INFO L93 Difference]: Finished difference Result 813 states and 1072 transitions. [2025-03-04 16:20:05,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 813 states and 1072 transitions. [2025-03-04 16:20:05,314 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 744 [2025-03-04 16:20:05,317 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 813 states to 813 states and 1072 transitions. [2025-03-04 16:20:05,317 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 813 [2025-03-04 16:20:05,318 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 813 [2025-03-04 16:20:05,318 INFO L73 IsDeterministic]: Start isDeterministic. Operand 813 states and 1072 transitions. [2025-03-04 16:20:05,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:05,319 INFO L218 hiAutomatonCegarLoop]: Abstraction has 813 states and 1072 transitions. [2025-03-04 16:20:05,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 813 states and 1072 transitions. [2025-03-04 16:20:05,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 813 to 813. [2025-03-04 16:20:05,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 813 states, 813 states have (on average 1.3185731857318572) internal successors, (1072), 812 states have internal predecessors, (1072), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 813 states to 813 states and 1072 transitions. [2025-03-04 16:20:05,329 INFO L240 hiAutomatonCegarLoop]: Abstraction has 813 states and 1072 transitions. [2025-03-04 16:20:05,330 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:05,330 INFO L432 stractBuchiCegarLoop]: Abstraction has 813 states and 1072 transitions. [2025-03-04 16:20:05,330 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:20:05,330 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 813 states and 1072 transitions. [2025-03-04 16:20:05,333 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 744 [2025-03-04 16:20:05,333 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:05,333 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:05,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,334 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,334 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-03-04 16:20:05,334 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume !(0 == ~c_dr_st~0);" [2025-03-04 16:20:05,334 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,334 INFO L85 PathProgramCache]: Analyzing trace with hash 1305611587, now seen corresponding path program 1 times [2025-03-04 16:20:05,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1298486926] [2025-03-04 16:20:05,335 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,338 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:05,339 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:05,340 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,340 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,340 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,342 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:05,343 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:05,343 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,349 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,349 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,349 INFO L85 PathProgramCache]: Analyzing trace with hash 2141702457, now seen corresponding path program 1 times [2025-03-04 16:20:05,349 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,349 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [251716920] [2025-03-04 16:20:05,349 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,351 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:20:05,352 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:20:05,352 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,352 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,352 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,354 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:20:05,355 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:20:05,355 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,355 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,358 INFO L85 PathProgramCache]: Analyzing trace with hash 1405322807, now seen corresponding path program 1 times [2025-03-04 16:20:05,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1871495321] [2025-03-04 16:20:05,358 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,361 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:20:05,366 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:20:05,366 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,366 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:05,388 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:05,388 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:05,388 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1871495321] [2025-03-04 16:20:05,388 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1871495321] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:05,388 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:05,388 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:20:05,388 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13843974] [2025-03-04 16:20:05,388 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:05,432 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:05,432 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:05,432 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:05,432 INFO L87 Difference]: Start difference. First operand 813 states and 1072 transitions. cyclomatic complexity: 266 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:05,459 INFO L93 Difference]: Finished difference Result 931 states and 1218 transitions. [2025-03-04 16:20:05,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 931 states and 1218 transitions. [2025-03-04 16:20:05,463 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 858 [2025-03-04 16:20:05,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 931 states to 931 states and 1218 transitions. [2025-03-04 16:20:05,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 931 [2025-03-04 16:20:05,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 931 [2025-03-04 16:20:05,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 931 states and 1218 transitions. [2025-03-04 16:20:05,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:05,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 931 states and 1218 transitions. [2025-03-04 16:20:05,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 931 states and 1218 transitions. [2025-03-04 16:20:05,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 931 to 822. [2025-03-04 16:20:05,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 822 states, 822 states have (on average 1.316301703163017) internal successors, (1082), 821 states have internal predecessors, (1082), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:05,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 822 states to 822 states and 1082 transitions. [2025-03-04 16:20:05,478 INFO L240 hiAutomatonCegarLoop]: Abstraction has 822 states and 1082 transitions. [2025-03-04 16:20:05,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:05,478 INFO L432 stractBuchiCegarLoop]: Abstraction has 822 states and 1082 transitions. [2025-03-04 16:20:05,478 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:20:05,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 822 states and 1082 transitions. [2025-03-04 16:20:05,481 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 750 [2025-03-04 16:20:05,481 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:05,481 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:05,481 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:05,483 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~fast_clk_edge~0 := 0;~slow_clk_edge~0 := 0;~q_buf_0~0 := 0;~q_free~0 := 0;~q_read_ev~0 := 0;~q_write_ev~0 := 0;~q_req_up~0 := 0;~q_ev~0 := 0;~p_num_write~0 := 0;~p_last_write~0 := 0;~p_dw_st~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 0;~c_num_read~0 := 0;~c_last_read~0 := 0;~c_dr_st~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 0;~a_t~0 := 0;~t~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~fast_clk_edge~0 := 2;~slow_clk_edge~0 := 2;~q_free~0 := 1;~q_write_ev~0 := 2;~q_read_ev~0 := ~q_write_ev~0;~p_num_write~0 := 0;~p_dw_pc~0 := 0;~p_dw_i~0 := 1;~c_num_read~0 := 0;~c_dr_pc~0 := 0;~c_dr_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret13#1, start_simulation_#t~ret14#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~4#1, start_simulation_~tmp___0~3#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~4#1;havoc start_simulation_~tmp___0~3#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume !(1 == ~q_req_up~0);" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~p_dw_i~0;~p_dw_st~0 := 0;" "assume 1 == ~c_dr_i~0;~c_dr_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~q_read_ev~0);" "assume !(0 == ~q_write_ev~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~1#1;assume { :begin_inline_is_do_write_p_triggered } true;havoc is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;havoc is_do_write_p_triggered_~__retres1~0#1;" "assume !(1 == ~p_dw_pc~0);" "assume !(2 == ~p_dw_pc~0);" "is_do_write_p_triggered_~__retres1~0#1 := 0;" "is_do_write_p_triggered_#res#1 := is_do_write_p_triggered_~__retres1~0#1;" "activate_threads_#t~ret7#1 := is_do_write_p_triggered_#res#1;havoc is_do_write_p_triggered_~__retres1~0#1;assume { :end_inline_is_do_write_p_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_do_read_c_triggered } true;havoc is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;havoc is_do_read_c_triggered_~__retres1~1#1;" "assume !(1 == ~c_dr_pc~0);" "assume !(2 == ~c_dr_pc~0);" "is_do_read_c_triggered_~__retres1~1#1 := 0;" "is_do_read_c_triggered_#res#1 := is_do_read_c_triggered_~__retres1~1#1;" "activate_threads_#t~ret8#1 := is_do_read_c_triggered_#res#1;havoc is_do_read_c_triggered_~__retres1~1#1;assume { :end_inline_is_do_read_c_triggered } true;activate_threads_~tmp___0~1#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1;" "assume !(0 != activate_threads_~tmp___0~1#1);" "havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~1#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~q_read_ev~0);" "assume !(1 == ~q_write_ev~0);" "assume { :end_inline_reset_delta_events } true;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret9#1, eval_#t~nondet10#1, eval_#t~nondet11#1, eval_~tmp~2#1, eval_~tmp___0~2#1, eval_~tmp___1~0#1;havoc eval_~tmp~2#1;havoc eval_~tmp___0~2#1;havoc eval_~tmp___1~0#1;" [2025-03-04 16:20:05,483 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1;" "assume 0 == ~p_dw_st~0;exists_runnable_thread_~__retres1~2#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1;" "eval_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp___1~0#1 := eval_#t~ret9#1;havoc eval_#t~ret9#1;" "assume 0 != eval_~tmp___1~0#1;" "assume 0 == ~p_dw_st~0;havoc eval_#t~nondet10#1;eval_~tmp~2#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1;" "assume !(0 != eval_~tmp~2#1);" "assume 0 == ~c_dr_st~0;havoc eval_#t~nondet11#1;eval_~tmp___0~2#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1;" "assume !(0 != eval_~tmp___0~2#1);" [2025-03-04 16:20:05,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,484 INFO L85 PathProgramCache]: Analyzing trace with hash 1305611587, now seen corresponding path program 2 times [2025-03-04 16:20:05,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1513872858] [2025-03-04 16:20:05,484 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:05,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,489 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:05,490 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:05,490 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:05,491 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,491 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,493 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:05,494 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:05,494 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,494 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,498 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,499 INFO L85 PathProgramCache]: Analyzing trace with hash 1968266873, now seen corresponding path program 1 times [2025-03-04 16:20:05,499 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,499 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [724115389] [2025-03-04 16:20:05,499 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,503 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:20:05,504 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:20:05,504 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,504 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,504 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,504 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 10 statements into 1 equivalence classes. [2025-03-04 16:20:05,505 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 10 of 10 statements. [2025-03-04 16:20:05,505 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,505 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,510 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:05,510 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:05,511 INFO L85 PathProgramCache]: Analyzing trace with hash 615334203, now seen corresponding path program 1 times [2025-03-04 16:20:05,511 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:05,511 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1094316830] [2025-03-04 16:20:05,511 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:05,511 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:05,517 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:05,518 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:05,518 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,519 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:05,520 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:05,521 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:05,521 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:05,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:05,527 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:06,090 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:06,094 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:06,094 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:06,094 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:06,094 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:06,101 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 30 statements into 1 equivalence classes. [2025-03-04 16:20:06,104 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 30 of 30 statements. [2025-03-04 16:20:06,104 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:06,104 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:06,182 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:20:06 BoogieIcfgContainer [2025-03-04 16:20:06,182 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:20:06,183 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:20:06,183 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:20:06,183 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:20:06,183 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:20:03" (3/4) ... [2025-03-04 16:20:06,185 INFO L143 WitnessPrinter]: Generating witness for non-termination counterexample [2025-03-04 16:20:06,241 INFO L149 WitnessManager]: Wrote witness to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/witness.graphml [2025-03-04 16:20:06,241 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:20:06,242 INFO L158 Benchmark]: Toolchain (without parser) took 3307.88ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 106.1MB in the beginning and 241.1MB in the end (delta: -135.1MB). Peak memory consumption was 31.8MB. Max. memory is 16.1GB. [2025-03-04 16:20:06,242 INFO L158 Benchmark]: CDTParser took 0.19ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:20:06,242 INFO L158 Benchmark]: CACSL2BoogieTranslator took 223.59ms. Allocated memory is still 142.6MB. Free memory was 106.1MB in the beginning and 92.6MB in the end (delta: 13.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:20:06,242 INFO L158 Benchmark]: Boogie Procedure Inliner took 38.79ms. Allocated memory is still 142.6MB. Free memory was 92.6MB in the beginning and 89.6MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:20:06,242 INFO L158 Benchmark]: Boogie Preprocessor took 47.28ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 88.7MB in the end (delta: 981.3kB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:20:06,242 INFO L158 Benchmark]: IcfgBuilder took 442.58ms. Allocated memory is still 142.6MB. Free memory was 88.7MB in the beginning and 62.6MB in the end (delta: 26.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. [2025-03-04 16:20:06,243 INFO L158 Benchmark]: BuchiAutomizer took 2492.29ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 62.6MB in the beginning and 248.3MB in the end (delta: -185.7MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:20:06,243 INFO L158 Benchmark]: Witness Printer took 58.49ms. Allocated memory is still 310.4MB. Free memory was 248.3MB in the beginning and 241.1MB in the end (delta: 7.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:20:06,244 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19ms. Allocated memory is still 201.3MB. Free memory is still 126.7MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 223.59ms. Allocated memory is still 142.6MB. Free memory was 106.1MB in the beginning and 92.6MB in the end (delta: 13.4MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 38.79ms. Allocated memory is still 142.6MB. Free memory was 92.6MB in the beginning and 89.6MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 47.28ms. Allocated memory is still 142.6MB. Free memory was 89.6MB in the beginning and 88.7MB in the end (delta: 981.3kB). There was no memory consumed. Max. memory is 16.1GB. * IcfgBuilder took 442.58ms. Allocated memory is still 142.6MB. Free memory was 88.7MB in the beginning and 62.6MB in the end (delta: 26.1MB). Peak memory consumption was 25.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 2492.29ms. Allocated memory was 142.6MB in the beginning and 310.4MB in the end (delta: 167.8MB). Free memory was 62.6MB in the beginning and 248.3MB in the end (delta: -185.7MB). There was no memory consumed. Max. memory is 16.1GB. * Witness Printer took 58.49ms. Allocated memory is still 310.4MB. Free memory was 248.3MB in the beginning and 241.1MB in the end (delta: 7.2MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 9 terminating modules (9 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.9 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 822 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 2.4s and 10 iterations. TraceHistogramMax:1. Analysis of lassos took 1.6s. Construction of modules took 0.2s. Büchi inclusion checks took 0.4s. Highest rank in rank-based complementation 0. Minimization of det autom 9. Minimization of nondet autom 0. Automata minimization 0.1s AutomataMinimizationTime, 9 MinimizatonAttempts, 240 StatesRemovedByMinimization, 5 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1521 SdHoareTripleChecker+Valid, 0.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1521 mSDsluCounter, 3395 SdHoareTripleChecker+Invalid, 0.2s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 1753 mSDsCounter, 73 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 241 IncrementalHoareTripleChecker+Invalid, 314 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 73 mSolverCounterUnsat, 1642 mSDtfsCounter, 241 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI3 SFLT0 conc1 concLT0 SILN0 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 410]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 410]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L24] int fast_clk_edge ; [L25] int slow_clk_edge ; [L26] int q_buf_0 ; [L27] int q_free ; [L28] int q_read_ev ; [L29] int q_write_ev ; [L30] int q_req_up ; [L31] int q_ev ; [L52] int p_num_write ; [L53] int p_last_write ; [L54] int p_dw_st ; [L55] int p_dw_pc ; [L56] int p_dw_i ; [L57] int c_num_read ; [L58] int c_last_read ; [L59] int c_dr_st ; [L60] int c_dr_pc ; [L61] int c_dr_i ; [L194] static int a_t ; [L344] static int t = 0; VAL [a_t=0, c_dr_i=0, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=0, p_dw_i=0, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=0, q_read_ev=0, q_req_up=0, q_write_ev=0, slow_clk_edge=0, t=0] [L555] int __retres1 ; [L559] CALL init_model() [L539] fast_clk_edge = 2 [L540] slow_clk_edge = 2 [L541] q_free = 1 [L542] q_write_ev = 2 [L543] q_read_ev = q_write_ev [L544] p_num_write = 0 [L545] p_dw_pc = 0 [L546] p_dw_i = 1 [L547] c_num_read = 0 [L548] c_dr_pc = 0 [L549] c_dr_i = 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L559] RET init_model() [L560] CALL start_simulation() [L477] int kernel_st ; [L478] int tmp ; [L479] int tmp___0 ; [L483] kernel_st = 0 [L484] CALL update_channels() [L258] COND FALSE !((int )q_req_up == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L484] RET update_channels() [L485] CALL init_threads() [L273] COND TRUE (int )p_dw_i == 1 [L274] p_dw_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L278] COND TRUE (int )c_dr_i == 1 [L279] c_dr_st = 0 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L485] RET init_threads() [L486] CALL fire_delta_events() [L311] COND FALSE !((int )q_read_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L316] COND FALSE !((int )q_write_ev == 0) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L486] RET fire_delta_events() [L487] CALL activate_threads() [L380] int tmp ; [L381] int tmp___0 ; [L385] CALL, EXPR is_do_write_p_triggered() [L63] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L66] COND FALSE !((int )p_dw_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L76] COND FALSE !((int )p_dw_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L86] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L88] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L385] RET, EXPR is_do_write_p_triggered() [L385] tmp = is_do_write_p_triggered() [L387] COND FALSE !(\read(tmp)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] CALL, EXPR is_do_read_c_triggered() [L92] int __retres1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L95] COND FALSE !((int )c_dr_pc == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L105] COND FALSE !((int )c_dr_pc == 2) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L115] __retres1 = 0 VAL [__retres1=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L117] return (__retres1); VAL [\result=0, a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L393] RET, EXPR is_do_read_c_triggered() [L393] tmp___0 = is_do_read_c_triggered() [L395] COND FALSE !(\read(tmp___0)) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L487] RET activate_threads() [L488] CALL reset_delta_events() [L329] COND FALSE !((int )q_read_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L334] COND FALSE !((int )q_write_ev == 1) VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L488] RET reset_delta_events() [L491] COND TRUE 1 VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] [L494] kernel_st = 1 [L495] CALL eval() [L405] int tmp ; [L406] int tmp___0 ; [L407] int tmp___1 ; VAL [a_t=0, c_dr_i=1, c_dr_pc=0, c_dr_st=0, c_last_read=0, c_num_read=0, fast_clk_edge=2, p_dw_i=1, p_dw_pc=0, p_dw_st=0, p_last_write=0, p_num_write=0, q_buf_0=0, q_ev=0, q_free=1, q_read_ev=2, q_req_up=0, q_write_ev=2, slow_clk_edge=2, t=0] Loop: [L410] COND TRUE 1 [L413] CALL, EXPR exists_runnable_thread() [L288] int __retres1 ; [L291] COND TRUE (int )p_dw_st == 0 [L292] __retres1 = 1 [L304] return (__retres1); [L413] RET, EXPR exists_runnable_thread() [L413] tmp___1 = exists_runnable_thread() [L415] COND TRUE \read(tmp___1) [L420] COND TRUE (int )p_dw_st == 0 [L422] tmp = __VERIFIER_nondet_int() [L424] COND FALSE !(\read(tmp)) [L435] COND TRUE (int )c_dr_st == 0 [L437] tmp___0 = __VERIFIER_nondet_int() [L439] COND FALSE !(\read(tmp___0)) End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2025-03-04 16:20:06,262 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)