./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/pipeline.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/pipeline.cil-2.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:20:03,883 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:20:03,940 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:20:03,943 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:20:03,943 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:20:03,944 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:20:03,963 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:20:03,964 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:20:03,964 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:20:03,965 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:20:03,965 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:20:03,966 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:20:03,966 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:20:03,966 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:20:03,967 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:20:03,967 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:20:03,968 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:20:03,968 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:20:03,968 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:20:03,968 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c42f0f019aa30bac52b753d657fd0a7a27ad0fcef5ea61d179259276789b8861 [2025-03-04 16:20:04,176 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:20:04,181 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:20:04,183 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:20:04,184 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:20:04,184 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:20:04,185 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/pipeline.cil-2.c [2025-03-04 16:20:05,317 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/31af2be5d/27e594a4899d4a81b0610a4f0f4c97c0/FLAG774be7a53 [2025-03-04 16:20:05,572 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:20:05,573 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/pipeline.cil-2.c [2025-03-04 16:20:05,589 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/31af2be5d/27e594a4899d4a81b0610a4f0f4c97c0/FLAG774be7a53 [2025-03-04 16:20:05,603 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/31af2be5d/27e594a4899d4a81b0610a4f0f4c97c0 [2025-03-04 16:20:05,605 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:20:05,606 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:20:05,607 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:20:05,608 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:20:05,611 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:20:05,612 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,614 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@6712e31f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05, skipping insertion in model container [2025-03-04 16:20:05,614 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,639 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:20:05,800 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:20:05,812 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:20:05,865 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:20:05,882 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:20:05,883 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05 WrapperNode [2025-03-04 16:20:05,883 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:20:05,884 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:20:05,884 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:20:05,884 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:20:05,888 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,896 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,929 INFO L138 Inliner]: procedures = 20, calls = 18, calls flagged for inlining = 13, calls inlined = 25, statements flattened = 1031 [2025-03-04 16:20:05,930 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:20:05,930 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:20:05,930 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:20:05,930 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:20:05,937 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,937 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,940 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,960 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:20:05,960 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,960 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,968 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,970 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,972 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,973 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,975 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:20:05,976 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:20:05,976 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:20:05,976 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:20:05,976 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (1/1) ... [2025-03-04 16:20:05,983 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:05,997 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:06,009 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:06,012 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:20:06,027 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:20:06,027 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:20:06,027 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:20:06,027 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:20:06,095 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:20:06,096 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:20:06,833 INFO L? ?]: Removed 76 outVars from TransFormulas that were not future-live. [2025-03-04 16:20:06,833 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:20:06,848 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:20:06,849 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:20:06,849 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:20:06 BoogieIcfgContainer [2025-03-04 16:20:06,849 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:20:06,850 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:20:06,850 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:20:06,854 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:20:06,855 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:06,855 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:20:05" (1/3) ... [2025-03-04 16:20:06,855 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bed1dd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:20:06, skipping insertion in model container [2025-03-04 16:20:06,857 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:06,857 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:20:05" (2/3) ... [2025-03-04 16:20:06,857 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3bed1dd7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:20:06, skipping insertion in model container [2025-03-04 16:20:06,857 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:20:06,857 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:20:06" (3/3) ... [2025-03-04 16:20:06,858 INFO L363 chiAutomizerObserver]: Analyzing ICFG pipeline.cil-2.c [2025-03-04 16:20:06,905 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:20:06,906 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:20:06,906 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:20:06,906 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:20:06,906 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:20:06,907 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:20:06,907 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:20:06,907 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:20:06,914 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:06,942 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2025-03-04 16:20:06,944 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:06,944 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:06,951 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:06,951 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:06,951 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:20:06,952 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:06,965 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 361 [2025-03-04 16:20:06,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:06,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:06,967 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:06,967 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:06,973 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-03-04 16:20:06,976 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume !true;" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:06,980 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:06,981 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 1 times [2025-03-04 16:20:06,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:06,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1549601156] [2025-03-04 16:20:06,987 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:06,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,043 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,075 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,079 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,079 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,079 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:07,088 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,114 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,114 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,140 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:07,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,143 INFO L85 PathProgramCache]: Analyzing trace with hash 520539416, now seen corresponding path program 1 times [2025-03-04 16:20:07,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [707610313] [2025-03-04 16:20:07,143 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:07,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 39 statements into 1 equivalence classes. [2025-03-04 16:20:07,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 39 of 39 statements. [2025-03-04 16:20:07,153 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,153 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:07,194 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:07,195 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:07,195 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [707610313] [2025-03-04 16:20:07,196 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [707610313] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:07,196 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:07,196 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:20:07,196 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1754164328] [2025-03-04 16:20:07,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:07,199 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:07,200 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:07,217 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 16:20:07,218 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 16:20:07,221 INFO L87 Difference]: Start difference. First operand has 423 states, 422 states have (on average 1.7962085308056872) internal successors, (758), 422 states have internal predecessors, (758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 19.5) internal successors, (39), 2 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:07,244 INFO L93 Difference]: Finished difference Result 417 states and 745 transitions. [2025-03-04 16:20:07,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 745 transitions. [2025-03-04 16:20:07,250 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2025-03-04 16:20:07,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 416 states and 744 transitions. [2025-03-04 16:20:07,258 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 416 [2025-03-04 16:20:07,259 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 416 [2025-03-04 16:20:07,260 INFO L73 IsDeterministic]: Start isDeterministic. Operand 416 states and 744 transitions. [2025-03-04 16:20:07,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:07,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-03-04 16:20:07,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 416 states and 744 transitions. [2025-03-04 16:20:07,292 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 416 to 416. [2025-03-04 16:20:07,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 416 states have (on average 1.7884615384615385) internal successors, (744), 415 states have internal predecessors, (744), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 744 transitions. [2025-03-04 16:20:07,298 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-03-04 16:20:07,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 16:20:07,303 INFO L432 stractBuchiCegarLoop]: Abstraction has 416 states and 744 transitions. [2025-03-04 16:20:07,303 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:20:07,303 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 744 transitions. [2025-03-04 16:20:07,308 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 358 [2025-03-04 16:20:07,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:07,308 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:07,310 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,311 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,311 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-03-04 16:20:07,311 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:07,313 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,313 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 2 times [2025-03-04 16:20:07,313 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,313 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [198085149] [2025-03-04 16:20:07,314 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:07,314 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,343 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,361 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,361 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:07,361 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,361 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:07,365 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,373 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,376 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,376 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,388 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:07,389 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,389 INFO L85 PathProgramCache]: Analyzing trace with hash 16513805, now seen corresponding path program 1 times [2025-03-04 16:20:07,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [539257097] [2025-03-04 16:20:07,389 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:07,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,395 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:07,401 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:07,406 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,407 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:07,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:07,463 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:07,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [539257097] [2025-03-04 16:20:07,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [539257097] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:07,463 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:07,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:07,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1598681652] [2025-03-04 16:20:07,464 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:07,464 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:07,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:07,464 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:07,464 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:07,465 INFO L87 Difference]: Start difference. First operand 416 states and 744 transitions. cyclomatic complexity: 330 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,550 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:07,550 INFO L93 Difference]: Finished difference Result 506 states and 918 transitions. [2025-03-04 16:20:07,550 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 506 states and 918 transitions. [2025-03-04 16:20:07,553 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 433 [2025-03-04 16:20:07,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 506 states to 506 states and 918 transitions. [2025-03-04 16:20:07,559 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 506 [2025-03-04 16:20:07,560 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 506 [2025-03-04 16:20:07,561 INFO L73 IsDeterministic]: Start isDeterministic. Operand 506 states and 918 transitions. [2025-03-04 16:20:07,562 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:07,563 INFO L218 hiAutomatonCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-03-04 16:20:07,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 506 states and 918 transitions. [2025-03-04 16:20:07,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 506 to 506. [2025-03-04 16:20:07,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 506 states, 506 states have (on average 1.8142292490118577) internal successors, (918), 505 states have internal predecessors, (918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 918 transitions. [2025-03-04 16:20:07,578 INFO L240 hiAutomatonCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-03-04 16:20:07,578 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:07,579 INFO L432 stractBuchiCegarLoop]: Abstraction has 506 states and 918 transitions. [2025-03-04 16:20:07,579 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:20:07,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 506 states and 918 transitions. [2025-03-04 16:20:07,581 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 433 [2025-03-04 16:20:07,581 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:07,581 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:07,582 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,582 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,582 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-03-04 16:20:07,582 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume 0 == ~main_in1_ev~0;~main_in1_ev~0 := 1;" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume 1 == ~main_in1_ev~0;~main_in1_ev~0 := 2;" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:07,583 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,583 INFO L85 PathProgramCache]: Analyzing trace with hash -658770066, now seen corresponding path program 1 times [2025-03-04 16:20:07,583 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,583 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355244403] [2025-03-04 16:20:07,583 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:07,583 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,588 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,593 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,593 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,593 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:07,669 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:07,669 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:07,670 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355244403] [2025-03-04 16:20:07,670 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355244403] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:07,670 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:07,670 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:07,670 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1120574360] [2025-03-04 16:20:07,670 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:07,670 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:07,670 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,671 INFO L85 PathProgramCache]: Analyzing trace with hash 1813465164, now seen corresponding path program 1 times [2025-03-04 16:20:07,671 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,671 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389240758] [2025-03-04 16:20:07,671 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:07,671 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,676 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:07,687 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:07,688 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,688 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:07,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:07,717 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:07,717 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389240758] [2025-03-04 16:20:07,718 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389240758] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:07,718 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:07,718 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:07,718 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1539270322] [2025-03-04 16:20:07,718 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:07,718 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:07,718 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:07,719 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:07,719 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:07,719 INFO L87 Difference]: Start difference. First operand 506 states and 918 transitions. cyclomatic complexity: 414 Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,792 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:07,793 INFO L93 Difference]: Finished difference Result 918 states and 1644 transitions. [2025-03-04 16:20:07,793 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 918 states and 1644 transitions. [2025-03-04 16:20:07,799 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 791 [2025-03-04 16:20:07,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 918 states to 918 states and 1644 transitions. [2025-03-04 16:20:07,804 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 918 [2025-03-04 16:20:07,805 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 918 [2025-03-04 16:20:07,805 INFO L73 IsDeterministic]: Start isDeterministic. Operand 918 states and 1644 transitions. [2025-03-04 16:20:07,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:07,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-03-04 16:20:07,808 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 918 states and 1644 transitions. [2025-03-04 16:20:07,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 918 to 918. [2025-03-04 16:20:07,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 918 states, 918 states have (on average 1.7908496732026145) internal successors, (1644), 917 states have internal predecessors, (1644), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:07,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 918 states to 918 states and 1644 transitions. [2025-03-04 16:20:07,827 INFO L240 hiAutomatonCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-03-04 16:20:07,828 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:07,828 INFO L432 stractBuchiCegarLoop]: Abstraction has 918 states and 1644 transitions. [2025-03-04 16:20:07,829 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:20:07,829 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 918 states and 1644 transitions. [2025-03-04 16:20:07,832 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 791 [2025-03-04 16:20:07,833 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:07,833 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:07,834 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,836 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:07,836 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" [2025-03-04 16:20:07,836 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:07,837 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,837 INFO L85 PathProgramCache]: Analyzing trace with hash 1362474382, now seen corresponding path program 3 times [2025-03-04 16:20:07,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1425993272] [2025-03-04 16:20:07,837 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:07,837 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,862 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,868 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,870 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:07,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,870 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:07,873 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:07,880 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:07,880 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,880 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:07,889 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:07,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:07,890 INFO L85 PathProgramCache]: Analyzing trace with hash 47533612, now seen corresponding path program 1 times [2025-03-04 16:20:07,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:07,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567624271] [2025-03-04 16:20:07,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:07,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:07,894 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:07,897 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:07,897 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:07,898 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:07,923 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:07,923 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:07,923 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567624271] [2025-03-04 16:20:07,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567624271] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:07,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:07,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:07,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1818699888] [2025-03-04 16:20:07,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:07,923 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:07,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:07,924 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:07,924 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:07,924 INFO L87 Difference]: Start difference. First operand 918 states and 1644 transitions. cyclomatic complexity: 728 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:08,080 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:08,080 INFO L93 Difference]: Finished difference Result 1140 states and 1974 transitions. [2025-03-04 16:20:08,080 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1140 states and 1974 transitions. [2025-03-04 16:20:08,086 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 976 [2025-03-04 16:20:08,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1140 states to 1140 states and 1974 transitions. [2025-03-04 16:20:08,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1140 [2025-03-04 16:20:08,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1140 [2025-03-04 16:20:08,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1140 states and 1974 transitions. [2025-03-04 16:20:08,097 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:08,097 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-03-04 16:20:08,098 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1140 states and 1974 transitions. [2025-03-04 16:20:08,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1140 to 1140. [2025-03-04 16:20:08,115 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1140 states, 1140 states have (on average 1.731578947368421) internal successors, (1974), 1139 states have internal predecessors, (1974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:08,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1140 states to 1140 states and 1974 transitions. [2025-03-04 16:20:08,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-03-04 16:20:08,118 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:08,119 INFO L432 stractBuchiCegarLoop]: Abstraction has 1140 states and 1974 transitions. [2025-03-04 16:20:08,119 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:20:08,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1140 states and 1974 transitions. [2025-03-04 16:20:08,124 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 976 [2025-03-04 16:20:08,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:08,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:08,125 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:08,125 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:08,125 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" [2025-03-04 16:20:08,125 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:08,126 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:08,126 INFO L85 PathProgramCache]: Analyzing trace with hash 968443117, now seen corresponding path program 1 times [2025-03-04 16:20:08,126 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:08,126 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [469319009] [2025-03-04 16:20:08,127 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:08,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:08,132 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:08,136 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:08,136 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:08,136 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:08,198 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:08,198 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:08,198 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [469319009] [2025-03-04 16:20:08,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [469319009] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:08,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:08,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:08,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1563957676] [2025-03-04 16:20:08,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:08,198 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:08,198 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:08,198 INFO L85 PathProgramCache]: Analyzing trace with hash 47532651, now seen corresponding path program 1 times [2025-03-04 16:20:08,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:08,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1966436727] [2025-03-04 16:20:08,199 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:08,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:08,202 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:08,203 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:08,203 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:08,203 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:08,204 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:08,205 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:08,206 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:08,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:08,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:08,209 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:08,765 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:20:08,766 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:20:08,766 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:20:08,766 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:20:08,766 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-04 16:20:08,766 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:08,766 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:20:08,766 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:20:08,767 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration5_Loop [2025-03-04 16:20:08,767 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:20:08,767 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:20:08,779 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,819 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,871 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:08,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,167 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:20:09,167 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-03-04 16:20:09,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,168 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,172 INFO L229 MonitoredProcess]: Starting monitored process 2 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,173 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2025-03-04 16:20:09,174 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:20:09,174 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:09,192 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-04 16:20:09,193 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet4#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet4#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-04 16:20:09,199 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2025-03-04 16:20:09,199 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,199 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,203 INFO L229 MonitoredProcess]: Starting monitored process 3 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,205 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2025-03-04 16:20:09,206 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:20:09,206 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:09,217 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-04 16:20:09,217 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp___1~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp___1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-04 16:20:09,223 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2025-03-04 16:20:09,223 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,224 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,226 INFO L229 MonitoredProcess]: Starting monitored process 4 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,227 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2025-03-04 16:20:09,228 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:20:09,228 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:09,244 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2025-03-04 16:20:09,245 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,245 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,246 INFO L229 MonitoredProcess]: Starting monitored process 5 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,247 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2025-03-04 16:20:09,248 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-03-04 16:20:09,248 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:09,260 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-03-04 16:20:09,268 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2025-03-04 16:20:09,268 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:20:09,268 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:20:09,268 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:20:09,268 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:20:09,268 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 16:20:09,268 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,268 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:20:09,268 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:20:09,268 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration5_Loop [2025-03-04 16:20:09,268 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:20:09,268 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:20:09,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,274 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,276 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,283 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,285 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,287 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,297 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,302 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,312 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,318 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,326 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,335 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,344 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,346 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,351 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,361 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,363 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,369 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,374 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:09,646 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:20:09,649 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 16:20:09,651 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,651 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,653 INFO L229 MonitoredProcess]: Starting monitored process 6 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,655 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2025-03-04 16:20:09,656 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:20:09,667 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:20:09,668 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:20:09,668 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:20:09,668 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:20:09,668 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:20:09,674 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:20:09,674 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:20:09,676 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:20:09,682 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2025-03-04 16:20:09,683 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,683 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,688 INFO L229 MonitoredProcess]: Starting monitored process 7 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,689 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2025-03-04 16:20:09,690 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:20:09,700 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:20:09,700 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:20:09,700 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:20:09,700 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:20:09,700 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:20:09,700 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:20:09,701 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:20:09,702 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:20:09,707 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Forceful destruction successful, exit code 0 [2025-03-04 16:20:09,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,708 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,709 INFO L229 MonitoredProcess]: Starting monitored process 8 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,710 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2025-03-04 16:20:09,711 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:20:09,720 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:20:09,720 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:20:09,720 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:20:09,720 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:20:09,720 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:20:09,721 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:20:09,721 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:20:09,723 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 16:20:09,725 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-03-04 16:20:09,727 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-03-04 16:20:09,728 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:09,728 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:09,730 INFO L229 MonitoredProcess]: Starting monitored process 9 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:09,732 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2025-03-04 16:20:09,733 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 16:20:09,733 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-03-04 16:20:09,733 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 16:20:09,733 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~main_dbl_ev~0) = -1*~main_dbl_ev~0 + 1 Supporting invariants [] [2025-03-04 16:20:09,740 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2025-03-04 16:20:09,742 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-03-04 16:20:09,767 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:09,784 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:09,805 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:09,805 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:09,806 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:09,807 INFO L256 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 16:20:09,809 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:20:09,872 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:09,884 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:09,884 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:09,884 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:09,884 INFO L256 TraceCheckSpWp]: Trace formula consists of 116 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 16:20:09,885 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:20:09,973 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:09,978 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-03-04 16:20:09,979 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 1140 states and 1974 transitions. cyclomatic complexity: 836 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:10,161 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 1140 states and 1974 transitions. cyclomatic complexity: 836. Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 4148 states and 7215 transitions. Complement of second has 5 states. [2025-03-04 16:20:10,162 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 16:20:10,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:10,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1400 transitions. [2025-03-04 16:20:10,167 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 44 letters. [2025-03-04 16:20:10,168 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:10,169 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 84 letters. Loop has 44 letters. [2025-03-04 16:20:10,169 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:10,169 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 88 letters. [2025-03-04 16:20:10,173 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:10,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4148 states and 7215 transitions. [2025-03-04 16:20:10,202 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2928 [2025-03-04 16:20:10,226 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4148 states to 4148 states and 7215 transitions. [2025-03-04 16:20:10,226 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3098 [2025-03-04 16:20:10,229 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3135 [2025-03-04 16:20:10,230 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4148 states and 7215 transitions. [2025-03-04 16:20:10,230 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:10,230 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4148 states and 7215 transitions. [2025-03-04 16:20:10,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4148 states and 7215 transitions. [2025-03-04 16:20:10,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4148 to 3133. [2025-03-04 16:20:10,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3133 states, 3133 states have (on average 1.7405043089690393) internal successors, (5453), 3132 states have internal predecessors, (5453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:10,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3133 states to 3133 states and 5453 transitions. [2025-03-04 16:20:10,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3133 states and 5453 transitions. [2025-03-04 16:20:10,300 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:10,301 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:10,301 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:10,301 INFO L87 Difference]: Start difference. First operand 3133 states and 5453 transitions. Second operand has 4 states, 4 states have (on average 10.0) internal successors, (40), 4 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:10,582 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2025-03-04 16:20:10,609 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:10,610 INFO L93 Difference]: Finished difference Result 5016 states and 8751 transitions. [2025-03-04 16:20:10,610 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5016 states and 8751 transitions. [2025-03-04 16:20:10,631 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 2990 [2025-03-04 16:20:10,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5016 states to 5016 states and 8751 transitions. [2025-03-04 16:20:10,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3383 [2025-03-04 16:20:10,654 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3383 [2025-03-04 16:20:10,654 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5016 states and 8751 transitions. [2025-03-04 16:20:10,654 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:10,654 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5016 states and 8751 transitions. [2025-03-04 16:20:10,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5016 states and 8751 transitions. [2025-03-04 16:20:10,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5016 to 3684. [2025-03-04 16:20:10,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3684 states, 3684 states have (on average 1.752442996742671) internal successors, (6456), 3683 states have internal predecessors, (6456), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:10,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3684 states to 3684 states and 6456 transitions. [2025-03-04 16:20:10,718 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3684 states and 6456 transitions. [2025-03-04 16:20:10,718 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:10,719 INFO L432 stractBuchiCegarLoop]: Abstraction has 3684 states and 6456 transitions. [2025-03-04 16:20:10,719 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:20:10,719 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3684 states and 6456 transitions. [2025-03-04 16:20:10,731 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2284 [2025-03-04 16:20:10,732 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:10,732 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:10,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:10,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:10,733 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" [2025-03-04 16:20:10,733 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" [2025-03-04 16:20:10,733 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:10,733 INFO L85 PathProgramCache]: Analyzing trace with hash -1973214483, now seen corresponding path program 1 times [2025-03-04 16:20:10,733 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:10,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1296106105] [2025-03-04 16:20:10,733 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:10,734 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:10,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:10,740 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:10,741 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:10,741 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:10,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:10,768 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:10,768 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1296106105] [2025-03-04 16:20:10,768 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1296106105] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:10,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:10,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:10,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1990557057] [2025-03-04 16:20:10,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:10,769 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:10,769 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:10,769 INFO L85 PathProgramCache]: Analyzing trace with hash -949539702, now seen corresponding path program 1 times [2025-03-04 16:20:10,769 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:10,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [108483373] [2025-03-04 16:20:10,769 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:10,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:10,773 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:10,775 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:10,775 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:10,775 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:10,775 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:10,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:10,779 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:10,779 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:10,779 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:10,782 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:11,194 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:20:11,194 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:20:11,194 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:20:11,194 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:20:11,194 INFO L128 ssoRankerPreferences]: Use exernal solver: true [2025-03-04 16:20:11,194 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,194 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:20:11,194 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:20:11,194 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration6_Loop [2025-03-04 16:20:11,195 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:20:11,195 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:20:11,196 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,198 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,202 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,204 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,211 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,214 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,217 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,221 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,225 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,230 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,233 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,237 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,240 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,251 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,253 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,255 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,259 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,264 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,267 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,268 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,272 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,282 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,284 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,286 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,552 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:20:11,553 INFO L365 LassoAnalysis]: Checking for nontermination... [2025-03-04 16:20:11,553 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,553 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,559 INFO L229 MonitoredProcess]: Starting monitored process 10 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,560 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2025-03-04 16:20:11,561 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:20:11,561 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:11,572 INFO L398 LassoAnalysis]: Proved nontermination for one component. [2025-03-04 16:20:11,572 INFO L401 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2025-03-04 16:20:11,578 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2025-03-04 16:20:11,578 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,578 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,580 INFO L229 MonitoredProcess]: Starting monitored process 11 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,581 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2025-03-04 16:20:11,582 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2025-03-04 16:20:11,582 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:11,600 INFO L540 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2025-03-04 16:20:11,600 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,600 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,603 INFO L229 MonitoredProcess]: Starting monitored process 12 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,605 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2025-03-04 16:20:11,606 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2025-03-04 16:20:11,606 INFO L160 nArgumentSynthesizer]: Using integer mode. [2025-03-04 16:20:11,618 INFO L405 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2025-03-04 16:20:11,624 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2025-03-04 16:20:11,625 INFO L204 LassoAnalysis]: Preferences: [2025-03-04 16:20:11,625 INFO L125 ssoRankerPreferences]: Compute integeral hull: false [2025-03-04 16:20:11,625 INFO L126 ssoRankerPreferences]: Enable LassoPartitioneer: true [2025-03-04 16:20:11,625 INFO L127 ssoRankerPreferences]: Term annotations enabled: false [2025-03-04 16:20:11,625 INFO L128 ssoRankerPreferences]: Use exernal solver: false [2025-03-04 16:20:11,625 INFO L129 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,625 INFO L130 ssoRankerPreferences]: Dump SMT script to file: false [2025-03-04 16:20:11,625 INFO L131 ssoRankerPreferences]: Path of dumped script: [2025-03-04 16:20:11,625 INFO L132 ssoRankerPreferences]: Filename of dumped script: pipeline.cil-2.c_Iteration6_Loop [2025-03-04 16:20:11,625 INFO L133 ssoRankerPreferences]: MapElimAlgo: Frank [2025-03-04 16:20:11,625 INFO L241 LassoAnalysis]: Starting lasso preprocessing... [2025-03-04 16:20:11,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,633 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,635 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,652 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,682 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2025-03-04 16:20:11,940 INFO L259 LassoAnalysis]: Preprocessing complete. [2025-03-04 16:20:11,940 INFO L451 LassoAnalysis]: Using template 'affine'. [2025-03-04 16:20:11,941 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,941 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,942 INFO L229 MonitoredProcess]: Starting monitored process 13 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,944 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2025-03-04 16:20:11,945 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:20:11,954 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:20:11,954 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:20:11,954 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:20:11,954 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:20:11,954 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:20:11,955 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:20:11,955 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:20:11,956 INFO L488 LassoAnalysis]: Proving termination failed for this template and these settings. [2025-03-04 16:20:11,961 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2025-03-04 16:20:11,962 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,962 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,963 INFO L229 MonitoredProcess]: Starting monitored process 14 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,964 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2025-03-04 16:20:11,965 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2025-03-04 16:20:11,974 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2025-03-04 16:20:11,974 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2025-03-04 16:20:11,974 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2025-03-04 16:20:11,974 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2025-03-04 16:20:11,974 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2025-03-04 16:20:11,975 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2025-03-04 16:20:11,975 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2025-03-04 16:20:11,977 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2025-03-04 16:20:11,978 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2025-03-04 16:20:11,978 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2025-03-04 16:20:11,979 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:20:11,979 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:20:11,981 INFO L229 MonitoredProcess]: Starting monitored process 15 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:20:11,982 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2025-03-04 16:20:11,983 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2025-03-04 16:20:11,983 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2025-03-04 16:20:11,983 INFO L474 LassoAnalysis]: Proved termination. [2025-03-04 16:20:11,983 INFO L476 LassoAnalysis]: Termination argument consisting of: Ranking function f(~main_pres_ev~0) = -1*~main_pres_ev~0 + 1 Supporting invariants [] [2025-03-04 16:20:11,989 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2025-03-04 16:20:11,990 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2025-03-04 16:20:11,998 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:12,012 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 40 statements into 1 equivalence classes. [2025-03-04 16:20:12,028 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 40 of 40 statements. [2025-03-04 16:20:12,028 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:12,028 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:12,029 INFO L256 TraceCheckSpWp]: Trace formula consists of 232 conjuncts, 2 conjuncts are in the unsatisfiable core [2025-03-04 16:20:12,030 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:20:12,070 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:12,077 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:12,077 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:12,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:12,077 INFO L256 TraceCheckSpWp]: Trace formula consists of 113 conjuncts, 4 conjuncts are in the unsatisfiable core [2025-03-04 16:20:12,078 INFO L279 TraceCheckSpWp]: Computing forward predicates... [2025-03-04 16:20:12,146 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:12,147 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2025-03-04 16:20:12,147 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 3684 states and 6456 transitions. cyclomatic complexity: 2778 Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:12,232 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 3684 states and 6456 transitions. cyclomatic complexity: 2778. Second operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 7220 states and 12660 transitions. Complement of second has 5 states. [2025-03-04 16:20:12,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2025-03-04 16:20:12,233 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 16.8) internal successors, (84), 5 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:12,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1400 transitions. [2025-03-04 16:20:12,234 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 44 letters. [2025-03-04 16:20:12,234 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:12,235 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 84 letters. Loop has 44 letters. [2025-03-04 16:20:12,235 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:12,235 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1400 transitions. Stem has 40 letters. Loop has 88 letters. [2025-03-04 16:20:12,235 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2025-03-04 16:20:12,235 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7220 states and 12660 transitions. [2025-03-04 16:20:12,265 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 4568 [2025-03-04 16:20:12,297 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7220 states to 7220 states and 12660 transitions. [2025-03-04 16:20:12,297 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4780 [2025-03-04 16:20:12,301 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4832 [2025-03-04 16:20:12,301 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7220 states and 12660 transitions. [2025-03-04 16:20:12,301 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:12,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7220 states and 12660 transitions. [2025-03-04 16:20:12,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7220 states and 12660 transitions. [2025-03-04 16:20:12,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7220 to 6024. [2025-03-04 16:20:12,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6024 states, 6024 states have (on average 1.754980079681275) internal successors, (10572), 6023 states have internal predecessors, (10572), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:12,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6024 states to 6024 states and 10572 transitions. [2025-03-04 16:20:12,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6024 states and 10572 transitions. [2025-03-04 16:20:12,395 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:12,396 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:12,396 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:12,396 INFO L87 Difference]: Start difference. First operand 6024 states and 10572 transitions. Second operand has 3 states, 3 states have (on average 13.333333333333334) internal successors, (40), 3 states have internal predecessors, (40), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:12,499 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2025-03-04 16:20:12,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:12,590 INFO L93 Difference]: Finished difference Result 10082 states and 17344 transitions. [2025-03-04 16:20:12,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10082 states and 17344 transitions. [2025-03-04 16:20:12,627 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5799 [2025-03-04 16:20:12,655 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10082 states to 10082 states and 17344 transitions. [2025-03-04 16:20:12,655 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6058 [2025-03-04 16:20:12,660 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6058 [2025-03-04 16:20:12,661 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10082 states and 17344 transitions. [2025-03-04 16:20:12,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:12,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10082 states and 17344 transitions. [2025-03-04 16:20:12,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10082 states and 17344 transitions. [2025-03-04 16:20:12,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10082 to 10032. [2025-03-04 16:20:12,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10032 states, 10032 states have (on average 1.7188995215311005) internal successors, (17244), 10031 states have internal predecessors, (17244), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:12,788 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10032 states to 10032 states and 17244 transitions. [2025-03-04 16:20:12,788 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10032 states and 17244 transitions. [2025-03-04 16:20:12,789 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:12,789 INFO L432 stractBuchiCegarLoop]: Abstraction has 10032 states and 17244 transitions. [2025-03-04 16:20:12,789 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:20:12,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10032 states and 17244 transitions. [2025-03-04 16:20:12,816 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 5769 [2025-03-04 16:20:12,816 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:12,816 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:12,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:12,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:12,817 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume true;" [2025-03-04 16:20:12,817 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-03-04 16:20:12,818 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:12,818 INFO L85 PathProgramCache]: Analyzing trace with hash -712966469, now seen corresponding path program 1 times [2025-03-04 16:20:12,818 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:12,818 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2023206393] [2025-03-04 16:20:12,818 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:12,818 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:12,821 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:12,824 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:12,824 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:12,824 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:12,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:12,870 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:12,871 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2023206393] [2025-03-04 16:20:12,871 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2023206393] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:12,871 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:12,871 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:12,871 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [198117354] [2025-03-04 16:20:12,871 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:12,872 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:12,872 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:12,872 INFO L85 PathProgramCache]: Analyzing trace with hash 1512973912, now seen corresponding path program 1 times [2025-03-04 16:20:12,872 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:12,872 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1716026218] [2025-03-04 16:20:12,872 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:12,872 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:12,875 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:12,878 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:12,878 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:12,878 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:12,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:12,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:12,901 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1716026218] [2025-03-04 16:20:12,901 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1716026218] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:12,901 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:12,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:12,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [894833481] [2025-03-04 16:20:12,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:12,901 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:12,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:12,901 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:12,901 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:12,901 INFO L87 Difference]: Start difference. First operand 10032 states and 17244 transitions. cyclomatic complexity: 7222 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:13,170 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:13,170 INFO L93 Difference]: Finished difference Result 15331 states and 25903 transitions. [2025-03-04 16:20:13,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15331 states and 25903 transitions. [2025-03-04 16:20:13,236 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 8921 [2025-03-04 16:20:13,285 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15331 states to 15331 states and 25903 transitions. [2025-03-04 16:20:13,285 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9389 [2025-03-04 16:20:13,293 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9389 [2025-03-04 16:20:13,294 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15331 states and 25903 transitions. [2025-03-04 16:20:13,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:13,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15331 states and 25903 transitions. [2025-03-04 16:20:13,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15331 states and 25903 transitions. [2025-03-04 16:20:13,426 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15331 to 12848. [2025-03-04 16:20:13,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 12848 states, 12848 states have (on average 1.6961394769613947) internal successors, (21792), 12847 states have internal predecessors, (21792), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:13,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12848 states to 12848 states and 21792 transitions. [2025-03-04 16:20:13,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 12848 states and 21792 transitions. [2025-03-04 16:20:13,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:13,477 INFO L432 stractBuchiCegarLoop]: Abstraction has 12848 states and 21792 transitions. [2025-03-04 16:20:13,477 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:20:13,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 12848 states and 21792 transitions. [2025-03-04 16:20:13,506 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7359 [2025-03-04 16:20:13,506 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:13,506 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:13,507 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:13,507 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:13,507 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume true;" [2025-03-04 16:20:13,507 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume 0 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 1;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_neg_edge~0;~main_clk_neg_edge~0 := 2;" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-03-04 16:20:13,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:13,513 INFO L85 PathProgramCache]: Analyzing trace with hash -2066276166, now seen corresponding path program 1 times [2025-03-04 16:20:13,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:13,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1649434966] [2025-03-04 16:20:13,513 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:13,513 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:13,516 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:13,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:13,519 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:13,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:13,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:13,571 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:13,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1649434966] [2025-03-04 16:20:13,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1649434966] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:13,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:13,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:13,572 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454875280] [2025-03-04 16:20:13,572 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:13,572 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:13,572 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:13,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1512973912, now seen corresponding path program 2 times [2025-03-04 16:20:13,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:13,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [886473864] [2025-03-04 16:20:13,573 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:13,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:13,576 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:13,578 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:13,578 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:13,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:13,591 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:13,592 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:13,592 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [886473864] [2025-03-04 16:20:13,592 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [886473864] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:13,592 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:13,592 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:13,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927598498] [2025-03-04 16:20:13,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:13,593 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:13,593 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:13,594 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:13,594 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:13,594 INFO L87 Difference]: Start difference. First operand 12848 states and 21792 transitions. cyclomatic complexity: 8954 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:13,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:13,727 INFO L93 Difference]: Finished difference Result 13065 states and 21940 transitions. [2025-03-04 16:20:13,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13065 states and 21940 transitions. [2025-03-04 16:20:13,817 INFO L131 ngComponentsAnalysis]: Automaton has 10 accepting balls. 7558 [2025-03-04 16:20:13,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13065 states to 13065 states and 21940 transitions. [2025-03-04 16:20:13,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7920 [2025-03-04 16:20:13,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7920 [2025-03-04 16:20:13,856 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13065 states and 21940 transitions. [2025-03-04 16:20:13,856 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:13,856 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13065 states and 21940 transitions. [2025-03-04 16:20:13,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13065 states and 21940 transitions. [2025-03-04 16:20:13,951 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13065 to 11962. [2025-03-04 16:20:13,966 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11962 states, 11962 states have (on average 1.6833305467313158) internal successors, (20136), 11961 states have internal predecessors, (20136), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:13,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11962 states to 11962 states and 20136 transitions. [2025-03-04 16:20:13,988 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11962 states and 20136 transitions. [2025-03-04 16:20:13,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:13,989 INFO L432 stractBuchiCegarLoop]: Abstraction has 11962 states and 20136 transitions. [2025-03-04 16:20:13,989 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:20:13,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11962 states and 20136 transitions. [2025-03-04 16:20:14,010 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6852 [2025-03-04 16:20:14,010 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:14,010 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:14,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:14,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:14,011 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:14,011 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-03-04 16:20:14,011 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:14,012 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 1 times [2025-03-04 16:20:14,012 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:14,012 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [497906956] [2025-03-04 16:20:14,012 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:14,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:14,015 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:14,017 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:14,017 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:14,017 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:14,017 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:14,019 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:14,021 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:14,021 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:14,021 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:14,025 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:14,025 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:14,025 INFO L85 PathProgramCache]: Analyzing trace with hash 672742392, now seen corresponding path program 1 times [2025-03-04 16:20:14,025 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:14,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [205635218] [2025-03-04 16:20:14,025 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:14,026 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:14,028 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:14,029 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:14,029 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:14,029 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:14,052 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:14,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:14,053 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [205635218] [2025-03-04 16:20:14,053 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [205635218] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:14,053 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:14,053 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:14,053 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [20732734] [2025-03-04 16:20:14,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:14,053 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:14,053 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:14,054 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:14,054 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:14,054 INFO L87 Difference]: Start difference. First operand 11962 states and 20136 transitions. cyclomatic complexity: 8184 Second operand has 3 states, 3 states have (on average 14.666666666666666) internal successors, (44), 3 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:14,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:14,122 INFO L93 Difference]: Finished difference Result 16565 states and 27763 transitions. [2025-03-04 16:20:14,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16565 states and 27763 transitions. [2025-03-04 16:20:14,167 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9392 [2025-03-04 16:20:14,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16565 states to 16565 states and 27763 transitions. [2025-03-04 16:20:14,206 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9989 [2025-03-04 16:20:14,214 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9989 [2025-03-04 16:20:14,215 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16565 states and 27763 transitions. [2025-03-04 16:20:14,215 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:14,215 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16565 states and 27763 transitions. [2025-03-04 16:20:14,225 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16565 states and 27763 transitions. [2025-03-04 16:20:14,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16565 to 16499. [2025-03-04 16:20:14,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16499 states, 16499 states have (on average 1.678707800472756) internal successors, (27697), 16498 states have internal predecessors, (27697), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:14,458 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16499 states to 16499 states and 27697 transitions. [2025-03-04 16:20:14,458 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16499 states and 27697 transitions. [2025-03-04 16:20:14,459 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:14,459 INFO L432 stractBuchiCegarLoop]: Abstraction has 16499 states and 27697 transitions. [2025-03-04 16:20:14,459 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:20:14,459 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16499 states and 27697 transitions. [2025-03-04 16:20:14,493 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 9356 [2025-03-04 16:20:14,493 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:14,493 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:14,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:14,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:14,494 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume 1 == ~N_generate_i~0;~N_generate_st~0 := 0;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:14,494 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-03-04 16:20:14,494 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:14,494 INFO L85 PathProgramCache]: Analyzing trace with hash -1063766375, now seen corresponding path program 1 times [2025-03-04 16:20:14,495 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:14,495 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468420994] [2025-03-04 16:20:14,495 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:14,495 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:14,498 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:14,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:14,500 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:14,500 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:14,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:14,536 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:14,536 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1468420994] [2025-03-04 16:20:14,536 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1468420994] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:14,536 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:14,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:14,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1377031366] [2025-03-04 16:20:14,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:14,536 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:14,536 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:14,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1520730431, now seen corresponding path program 1 times [2025-03-04 16:20:14,536 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:14,536 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029934822] [2025-03-04 16:20:14,536 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:14,536 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:14,539 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 47 statements into 1 equivalence classes. [2025-03-04 16:20:14,540 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 47 of 47 statements. [2025-03-04 16:20:14,540 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:14,540 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:14,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:14,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:14,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029934822] [2025-03-04 16:20:14,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029934822] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:14,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:14,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:14,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1256658663] [2025-03-04 16:20:14,553 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:14,554 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:14,554 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:14,554 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:14,554 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:14,554 INFO L87 Difference]: Start difference. First operand 16499 states and 27697 transitions. cyclomatic complexity: 11212 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:14,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:14,700 INFO L93 Difference]: Finished difference Result 18549 states and 30570 transitions. [2025-03-04 16:20:14,700 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18549 states and 30570 transitions. [2025-03-04 16:20:14,757 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10836 [2025-03-04 16:20:14,804 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18549 states to 18549 states and 30570 transitions. [2025-03-04 16:20:14,805 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11003 [2025-03-04 16:20:14,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11003 [2025-03-04 16:20:14,814 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18549 states and 30570 transitions. [2025-03-04 16:20:14,814 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:14,814 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18549 states and 30570 transitions. [2025-03-04 16:20:14,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18549 states and 30570 transitions. [2025-03-04 16:20:15,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18549 to 18549. [2025-03-04 16:20:15,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18549 states, 18549 states have (on average 1.648067281255054) internal successors, (30570), 18548 states have internal predecessors, (30570), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:15,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18549 states to 18549 states and 30570 transitions. [2025-03-04 16:20:15,093 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18549 states and 30570 transitions. [2025-03-04 16:20:15,095 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:15,096 INFO L432 stractBuchiCegarLoop]: Abstraction has 18549 states and 30570 transitions. [2025-03-04 16:20:15,096 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:20:15,096 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18549 states and 30570 transitions. [2025-03-04 16:20:15,145 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 10836 [2025-03-04 16:20:15,145 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:15,145 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:15,146 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:15,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:15,146 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:15,146 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume true;" [2025-03-04 16:20:15,147 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:15,147 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 2 times [2025-03-04 16:20:15,147 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:15,147 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [851595670] [2025-03-04 16:20:15,147 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:15,147 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:15,151 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:15,154 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:15,154 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:15,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:15,154 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:15,156 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:15,159 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:15,159 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:15,160 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:15,166 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:15,167 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:15,167 INFO L85 PathProgramCache]: Analyzing trace with hash -619825120, now seen corresponding path program 1 times [2025-03-04 16:20:15,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:15,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1050332856] [2025-03-04 16:20:15,167 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:15,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:15,171 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 45 statements into 1 equivalence classes. [2025-03-04 16:20:15,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 45 of 45 statements. [2025-03-04 16:20:15,174 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:15,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:15,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:15,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:15,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1050332856] [2025-03-04 16:20:15,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1050332856] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:15,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:15,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:15,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [902483324] [2025-03-04 16:20:15,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:15,198 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:15,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:15,198 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:15,198 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:15,198 INFO L87 Difference]: Start difference. First operand 18549 states and 30570 transitions. cyclomatic complexity: 12041 Second operand has 3 states, 3 states have (on average 15.0) internal successors, (45), 3 states have internal predecessors, (45), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:15,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:15,310 INFO L93 Difference]: Finished difference Result 25209 states and 41413 transitions. [2025-03-04 16:20:15,310 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25209 states and 41413 transitions. [2025-03-04 16:20:15,407 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 14688 [2025-03-04 16:20:15,476 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25209 states to 25209 states and 41413 transitions. [2025-03-04 16:20:15,477 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14958 [2025-03-04 16:20:15,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14958 [2025-03-04 16:20:15,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25209 states and 41413 transitions. [2025-03-04 16:20:15,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:15,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25209 states and 41413 transitions. [2025-03-04 16:20:15,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25209 states and 41413 transitions. [2025-03-04 16:20:15,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25209 to 25086. [2025-03-04 16:20:15,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25086 states, 25086 states have (on average 1.6459379733716017) internal successors, (41290), 25085 states have internal predecessors, (41290), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:16,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25086 states to 25086 states and 41290 transitions. [2025-03-04 16:20:16,009 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25086 states and 41290 transitions. [2025-03-04 16:20:16,009 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:16,010 INFO L432 stractBuchiCegarLoop]: Abstraction has 25086 states and 41290 transitions. [2025-03-04 16:20:16,010 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:20:16,010 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25086 states and 41290 transitions. [2025-03-04 16:20:16,061 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 14616 [2025-03-04 16:20:16,062 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:16,062 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:16,062 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:16,063 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:16,063 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume 1 == ~S1_addsub_i~0;~S1_addsub_st~0 := 0;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:16,063 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume true;" [2025-03-04 16:20:16,063 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:16,063 INFO L85 PathProgramCache]: Analyzing trace with hash -724282565, now seen corresponding path program 1 times [2025-03-04 16:20:16,064 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:16,064 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1774847494] [2025-03-04 16:20:16,064 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:16,064 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:16,067 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:16,069 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:16,069 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:16,069 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:16,093 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:16,093 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:16,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1774847494] [2025-03-04 16:20:16,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1774847494] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:16,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:16,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:16,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2034949528] [2025-03-04 16:20:16,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:16,094 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:16,094 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:16,094 INFO L85 PathProgramCache]: Analyzing trace with hash 510818328, now seen corresponding path program 1 times [2025-03-04 16:20:16,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:16,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225077602] [2025-03-04 16:20:16,094 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:16,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:16,099 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-03-04 16:20:16,101 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-03-04 16:20:16,101 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:16,101 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:16,111 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:16,112 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:16,112 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225077602] [2025-03-04 16:20:16,112 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225077602] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:16,112 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:16,112 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:16,112 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [997814222] [2025-03-04 16:20:16,112 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:16,112 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:16,113 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:16,113 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:16,113 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:16,113 INFO L87 Difference]: Start difference. First operand 25086 states and 41290 transitions. cyclomatic complexity: 16226 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:16,198 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:16,199 INFO L93 Difference]: Finished difference Result 20947 states and 33958 transitions. [2025-03-04 16:20:16,199 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 20947 states and 33958 transitions. [2025-03-04 16:20:16,264 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12249 [2025-03-04 16:20:16,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 20947 states to 20947 states and 33958 transitions. [2025-03-04 16:20:16,306 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 12429 [2025-03-04 16:20:16,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 12429 [2025-03-04 16:20:16,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 20947 states and 33958 transitions. [2025-03-04 16:20:16,317 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:16,317 INFO L218 hiAutomatonCegarLoop]: Abstraction has 20947 states and 33958 transitions. [2025-03-04 16:20:16,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20947 states and 33958 transitions. [2025-03-04 16:20:16,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20947 to 20947. [2025-03-04 16:20:16,640 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 20947 states, 20947 states have (on average 1.6211390652599418) internal successors, (33958), 20946 states have internal predecessors, (33958), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:16,666 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20947 states to 20947 states and 33958 transitions. [2025-03-04 16:20:16,666 INFO L240 hiAutomatonCegarLoop]: Abstraction has 20947 states and 33958 transitions. [2025-03-04 16:20:16,667 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:16,667 INFO L432 stractBuchiCegarLoop]: Abstraction has 20947 states and 33958 transitions. [2025-03-04 16:20:16,667 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:20:16,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 20947 states and 33958 transitions. [2025-03-04 16:20:16,710 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 12249 [2025-03-04 16:20:16,710 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:16,710 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:16,711 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:16,711 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:16,711 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:16,711 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume 0 == ~S2_presdbl_st~0;" "assume true;" [2025-03-04 16:20:16,711 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:16,712 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 3 times [2025-03-04 16:20:16,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:16,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1585814128] [2025-03-04 16:20:16,712 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:16,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:16,716 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:16,718 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:16,719 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:16,719 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:16,719 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:16,720 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:16,724 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:16,724 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:16,724 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:16,729 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:16,730 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:16,730 INFO L85 PathProgramCache]: Analyzing trace with hash -2034712390, now seen corresponding path program 1 times [2025-03-04 16:20:16,730 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:16,731 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2054523830] [2025-03-04 16:20:16,731 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:16,731 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:16,734 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 46 statements into 1 equivalence classes. [2025-03-04 16:20:16,739 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 46 of 46 statements. [2025-03-04 16:20:16,739 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:16,739 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:16,750 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:16,750 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:16,750 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2054523830] [2025-03-04 16:20:16,750 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2054523830] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:16,750 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:16,750 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:16,750 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1022010014] [2025-03-04 16:20:16,750 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:16,750 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:16,750 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:16,750 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:16,750 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:16,750 INFO L87 Difference]: Start difference. First operand 20947 states and 33958 transitions. cyclomatic complexity: 13031 Second operand has 3 states, 3 states have (on average 15.333333333333334) internal successors, (46), 3 states have internal predecessors, (46), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:16,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:16,983 INFO L93 Difference]: Finished difference Result 28633 states and 46180 transitions. [2025-03-04 16:20:16,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28633 states and 46180 transitions. [2025-03-04 16:20:17,107 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 16718 [2025-03-04 16:20:17,163 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28633 states to 28633 states and 46180 transitions. [2025-03-04 16:20:17,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16999 [2025-03-04 16:20:17,174 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16999 [2025-03-04 16:20:17,174 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28633 states and 46180 transitions. [2025-03-04 16:20:17,175 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:17,175 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28633 states and 46180 transitions. [2025-03-04 16:20:17,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28633 states and 46180 transitions. [2025-03-04 16:20:17,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28633 to 28428. [2025-03-04 16:20:17,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28428 states, 28428 states have (on average 1.617243562684677) internal successors, (45975), 28427 states have internal predecessors, (45975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:17,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28428 states to 28428 states and 45975 transitions. [2025-03-04 16:20:17,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28428 states and 45975 transitions. [2025-03-04 16:20:17,542 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:17,542 INFO L432 stractBuchiCegarLoop]: Abstraction has 28428 states and 45975 transitions. [2025-03-04 16:20:17,542 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:20:17,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28428 states and 45975 transitions. [2025-03-04 16:20:17,602 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 16598 [2025-03-04 16:20:17,603 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:17,603 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:17,603 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:17,603 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:17,604 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume 1 == ~S2_presdbl_i~0;~S2_presdbl_st~0 := 0;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:17,604 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume 0 == ~S2_presdbl_st~0;" "assume true;" [2025-03-04 16:20:17,604 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:17,604 INFO L85 PathProgramCache]: Analyzing trace with hash -1406068135, now seen corresponding path program 1 times [2025-03-04 16:20:17,605 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:17,605 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1913275081] [2025-03-04 16:20:17,605 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:17,605 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:17,608 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:17,610 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:17,610 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:17,610 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:17,629 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:17,630 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:17,630 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1913275081] [2025-03-04 16:20:17,630 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1913275081] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:17,630 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:17,630 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:17,630 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1969594086] [2025-03-04 16:20:17,630 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:17,631 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:17,631 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:17,631 INFO L85 PathProgramCache]: Analyzing trace with hash -1133152957, now seen corresponding path program 1 times [2025-03-04 16:20:17,631 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:17,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [822500435] [2025-03-04 16:20:17,631 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:17,632 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:17,634 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 49 statements into 1 equivalence classes. [2025-03-04 16:20:17,635 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 49 of 49 statements. [2025-03-04 16:20:17,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:17,636 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:17,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:17,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:17,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [822500435] [2025-03-04 16:20:17,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [822500435] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:17,645 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:17,645 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:17,645 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57323009] [2025-03-04 16:20:17,645 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:17,646 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:17,646 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:17,646 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:17,646 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:17,646 INFO L87 Difference]: Start difference. First operand 28428 states and 45975 transitions. cyclomatic complexity: 17569 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:17,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:17,729 INFO L93 Difference]: Finished difference Result 24444 states and 38985 transitions. [2025-03-04 16:20:17,729 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 24444 states and 38985 transitions. [2025-03-04 16:20:17,901 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14322 [2025-03-04 16:20:17,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 24444 states to 24444 states and 38985 transitions. [2025-03-04 16:20:17,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14514 [2025-03-04 16:20:17,966 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14514 [2025-03-04 16:20:17,967 INFO L73 IsDeterministic]: Start isDeterministic. Operand 24444 states and 38985 transitions. [2025-03-04 16:20:17,967 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:17,967 INFO L218 hiAutomatonCegarLoop]: Abstraction has 24444 states and 38985 transitions. [2025-03-04 16:20:17,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24444 states and 38985 transitions. [2025-03-04 16:20:18,156 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24444 to 24444. [2025-03-04 16:20:18,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24444 states, 24444 states have (on average 1.594869906725577) internal successors, (38985), 24443 states have internal predecessors, (38985), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:18,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24444 states to 24444 states and 38985 transitions. [2025-03-04 16:20:18,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24444 states and 38985 transitions. [2025-03-04 16:20:18,217 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:18,218 INFO L432 stractBuchiCegarLoop]: Abstraction has 24444 states and 38985 transitions. [2025-03-04 16:20:18,218 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:20:18,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24444 states and 38985 transitions. [2025-03-04 16:20:18,277 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 14322 [2025-03-04 16:20:18,277 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:18,277 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:18,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:18,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:18,278 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:18,278 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" "assume true;" [2025-03-04 16:20:18,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:18,278 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 4 times [2025-03-04 16:20:18,278 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:18,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1169123137] [2025-03-04 16:20:18,279 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:20:18,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:18,288 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 41 statements into 2 equivalence classes. [2025-03-04 16:20:18,291 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:18,291 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:20:18,291 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:18,291 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:18,292 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:18,295 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:18,295 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:18,295 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:18,300 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:18,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:18,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1348422434, now seen corresponding path program 1 times [2025-03-04 16:20:18,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:18,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137528534] [2025-03-04 16:20:18,300 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:18,301 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:18,304 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 47 statements into 1 equivalence classes. [2025-03-04 16:20:18,305 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 47 of 47 statements. [2025-03-04 16:20:18,305 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:18,305 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:18,318 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:18,318 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:18,318 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137528534] [2025-03-04 16:20:18,318 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137528534] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:18,318 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:18,318 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:18,319 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792184401] [2025-03-04 16:20:18,319 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:18,319 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:18,319 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:18,319 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:18,319 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:18,319 INFO L87 Difference]: Start difference. First operand 24444 states and 38985 transitions. cyclomatic complexity: 14561 Second operand has 3 states, 3 states have (on average 15.666666666666666) internal successors, (47), 3 states have internal predecessors, (47), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:18,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:18,444 INFO L93 Difference]: Finished difference Result 34172 states and 53962 transitions. [2025-03-04 16:20:18,444 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34172 states and 53962 transitions. [2025-03-04 16:20:18,693 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 20017 [2025-03-04 16:20:18,752 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34172 states to 34172 states and 53962 transitions. [2025-03-04 16:20:18,752 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 20309 [2025-03-04 16:20:18,765 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 20309 [2025-03-04 16:20:18,765 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34172 states and 53962 transitions. [2025-03-04 16:20:18,766 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:18,766 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34172 states and 53962 transitions. [2025-03-04 16:20:18,783 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34172 states and 53962 transitions. [2025-03-04 16:20:18,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34172 to 33844. [2025-03-04 16:20:19,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 33844 states, 33844 states have (on average 1.5847417562935824) internal successors, (53634), 33843 states have internal predecessors, (53634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:19,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33844 states to 33844 states and 53634 transitions. [2025-03-04 16:20:19,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 33844 states and 53634 transitions. [2025-03-04 16:20:19,059 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:19,059 INFO L432 stractBuchiCegarLoop]: Abstraction has 33844 states and 53634 transitions. [2025-03-04 16:20:19,059 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:20:19,060 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 33844 states and 53634 transitions. [2025-03-04 16:20:19,130 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 19825 [2025-03-04 16:20:19,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:19,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:19,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:19,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:19,131 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume 1 == ~S3_zero_i~0;~S3_zero_st~0 := 0;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:19,131 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume 0 == ~S3_zero_st~0;" "assume true;" [2025-03-04 16:20:19,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:19,131 INFO L85 PathProgramCache]: Analyzing trace with hash -458229893, now seen corresponding path program 1 times [2025-03-04 16:20:19,131 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:19,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [29638644] [2025-03-04 16:20:19,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:19,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:19,135 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:19,137 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:19,137 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:19,137 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:19,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:19,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:19,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [29638644] [2025-03-04 16:20:19,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [29638644] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:19,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:19,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:19,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1726776188] [2025-03-04 16:20:19,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:19,159 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:19,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:19,159 INFO L85 PathProgramCache]: Analyzing trace with hash -768006215, now seen corresponding path program 1 times [2025-03-04 16:20:19,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:19,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1025652806] [2025-03-04 16:20:19,159 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:19,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:19,163 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 50 statements into 1 equivalence classes. [2025-03-04 16:20:19,164 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 50 of 50 statements. [2025-03-04 16:20:19,164 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:19,164 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:19,173 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:19,174 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:19,174 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1025652806] [2025-03-04 16:20:19,174 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1025652806] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:19,174 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:19,174 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:19,174 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1745475999] [2025-03-04 16:20:19,174 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:19,174 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:19,174 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:19,174 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:19,175 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:19,175 INFO L87 Difference]: Start difference. First operand 33844 states and 53634 transitions. cyclomatic complexity: 19812 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:19,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:19,424 INFO L93 Difference]: Finished difference Result 30015 states and 46986 transitions. [2025-03-04 16:20:19,424 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30015 states and 46986 transitions. [2025-03-04 16:20:19,503 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17640 [2025-03-04 16:20:19,555 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30015 states to 30015 states and 46986 transitions. [2025-03-04 16:20:19,555 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17843 [2025-03-04 16:20:19,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17843 [2025-03-04 16:20:19,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30015 states and 46986 transitions. [2025-03-04 16:20:19,566 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:19,566 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30015 states and 46986 transitions. [2025-03-04 16:20:19,579 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30015 states and 46986 transitions. [2025-03-04 16:20:19,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30015 to 30015. [2025-03-04 16:20:19,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30015 states, 30015 states have (on average 1.565417291354323) internal successors, (46986), 30014 states have internal predecessors, (46986), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:19,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30015 states to 30015 states and 46986 transitions. [2025-03-04 16:20:19,909 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30015 states and 46986 transitions. [2025-03-04 16:20:19,909 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:19,909 INFO L432 stractBuchiCegarLoop]: Abstraction has 30015 states and 46986 transitions. [2025-03-04 16:20:19,909 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:20:19,909 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30015 states and 46986 transitions. [2025-03-04 16:20:19,969 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 17640 [2025-03-04 16:20:19,969 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:19,969 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:19,970 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:19,970 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:19,970 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:19,971 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" "assume true;" [2025-03-04 16:20:19,971 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:19,971 INFO L85 PathProgramCache]: Analyzing trace with hash -712966438, now seen corresponding path program 5 times [2025-03-04 16:20:19,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:19,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2103872363] [2025-03-04 16:20:19,971 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:20:19,971 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:19,976 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:19,978 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:19,978 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:19,978 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:19,978 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:19,980 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:19,982 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:19,982 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:19,982 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:19,985 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:19,985 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:19,986 INFO L85 PathProgramCache]: Analyzing trace with hash -1148580484, now seen corresponding path program 1 times [2025-03-04 16:20:19,986 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:19,986 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1538739107] [2025-03-04 16:20:19,986 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:19,986 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:19,988 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 48 statements into 1 equivalence classes. [2025-03-04 16:20:19,989 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 48 of 48 statements. [2025-03-04 16:20:19,990 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:19,990 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:19,999 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:20,000 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:20,000 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1538739107] [2025-03-04 16:20:20,000 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1538739107] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:20,000 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:20,000 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:20,000 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [578317235] [2025-03-04 16:20:20,001 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:20,001 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:20,001 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:20,001 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:20,001 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:20,001 INFO L87 Difference]: Start difference. First operand 30015 states and 46986 transitions. cyclomatic complexity: 16991 Second operand has 3 states, 3 states have (on average 16.0) internal successors, (48), 3 states have internal predecessors, (48), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:20,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:20,113 INFO L93 Difference]: Finished difference Result 42077 states and 64602 transitions. [2025-03-04 16:20:20,113 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42077 states and 64602 transitions. [2025-03-04 16:20:20,367 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 23943 [2025-03-04 16:20:20,461 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42077 states to 42077 states and 64602 transitions. [2025-03-04 16:20:20,461 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25056 [2025-03-04 16:20:20,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25056 [2025-03-04 16:20:20,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42077 states and 64602 transitions. [2025-03-04 16:20:20,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:20,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42077 states and 64602 transitions. [2025-03-04 16:20:20,505 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42077 states and 64602 transitions. [2025-03-04 16:20:20,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42077 to 41585. [2025-03-04 16:20:21,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41585 states, 41585 states have (on average 1.5416616568474208) internal successors, (64110), 41584 states have internal predecessors, (64110), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:21,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41585 states to 41585 states and 64110 transitions. [2025-03-04 16:20:21,050 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41585 states and 64110 transitions. [2025-03-04 16:20:21,050 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:21,050 INFO L432 stractBuchiCegarLoop]: Abstraction has 41585 states and 64110 transitions. [2025-03-04 16:20:21,050 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:20:21,050 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41585 states and 64110 transitions. [2025-03-04 16:20:21,130 INFO L131 ngComponentsAnalysis]: Automaton has 13 accepting balls. 23655 [2025-03-04 16:20:21,130 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:21,130 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:21,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:21,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:21,131 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume 1 == ~D_print_i~0;~D_print_st~0 := 0;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:21,131 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume 0 == ~D_print_st~0;" "assume true;" [2025-03-04 16:20:21,131 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:21,131 INFO L85 PathProgramCache]: Analyzing trace with hash -1674580455, now seen corresponding path program 1 times [2025-03-04 16:20:21,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:21,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370600838] [2025-03-04 16:20:21,132 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:21,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:21,135 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 41 statements into 1 equivalence classes. [2025-03-04 16:20:21,137 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 41 of 41 statements. [2025-03-04 16:20:21,137 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:21,137 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:21,168 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:21,168 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:21,168 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370600838] [2025-03-04 16:20:21,169 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370600838] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:21,169 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:21,169 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:21,169 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1042603455] [2025-03-04 16:20:21,169 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:21,169 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:21,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:21,169 INFO L85 PathProgramCache]: Analyzing trace with hash 716843652, now seen corresponding path program 1 times [2025-03-04 16:20:21,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:21,170 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1651000942] [2025-03-04 16:20:21,170 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:21,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:21,172 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 51 statements into 1 equivalence classes. [2025-03-04 16:20:21,174 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 51 of 51 statements. [2025-03-04 16:20:21,174 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:21,174 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:21,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:21,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:21,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1651000942] [2025-03-04 16:20:21,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1651000942] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:21,185 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:21,185 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:21,185 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597575429] [2025-03-04 16:20:21,185 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:21,185 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:21,186 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:21,186 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:21,186 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:21,186 INFO L87 Difference]: Start difference. First operand 41585 states and 64110 transitions. cyclomatic complexity: 22547 Second operand has 4 states, 4 states have (on average 10.25) internal successors, (41), 4 states have internal predecessors, (41), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:21,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:21,300 INFO L93 Difference]: Finished difference Result 37911 states and 57804 transitions. [2025-03-04 16:20:21,300 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37911 states and 57804 transitions. [2025-03-04 16:20:21,406 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21561 [2025-03-04 16:20:21,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37911 states to 37911 states and 57804 transitions. [2025-03-04 16:20:21,630 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22584 [2025-03-04 16:20:21,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22584 [2025-03-04 16:20:21,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37911 states and 57804 transitions. [2025-03-04 16:20:21,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:21,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37911 states and 57804 transitions. [2025-03-04 16:20:21,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37911 states and 57804 transitions. [2025-03-04 16:20:21,876 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37911 to 37911. [2025-03-04 16:20:21,906 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37911 states, 37911 states have (on average 1.5247289704835008) internal successors, (57804), 37910 states have internal predecessors, (57804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:22,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37911 states to 37911 states and 57804 transitions. [2025-03-04 16:20:22,105 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37911 states and 57804 transitions. [2025-03-04 16:20:22,105 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:22,106 INFO L432 stractBuchiCegarLoop]: Abstraction has 37911 states and 57804 transitions. [2025-03-04 16:20:22,106 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 16:20:22,106 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37911 states and 57804 transitions. [2025-03-04 16:20:22,173 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21561 [2025-03-04 16:20:22,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:22,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:22,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:22,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:22,175 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:20:22,175 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-03-04 16:20:22,175 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:22,175 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 1 times [2025-03-04 16:20:22,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:22,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1661027803] [2025-03-04 16:20:22,175 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:22,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:22,181 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:22,184 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:22,184 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:22,184 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:22,184 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:22,185 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:22,187 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:22,187 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:22,187 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:22,192 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:22,192 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:22,192 INFO L85 PathProgramCache]: Analyzing trace with hash -244030365, now seen corresponding path program 1 times [2025-03-04 16:20:22,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:22,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [405873927] [2025-03-04 16:20:22,192 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:22,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:22,195 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-04 16:20:22,196 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-04 16:20:22,196 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:22,196 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:22,207 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:22,207 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:22,207 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [405873927] [2025-03-04 16:20:22,207 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [405873927] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:22,207 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:22,207 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:22,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1094575817] [2025-03-04 16:20:22,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:22,208 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:22,208 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:22,208 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:22,208 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:22,208 INFO L87 Difference]: Start difference. First operand 37911 states and 57804 transitions. cyclomatic complexity: 19913 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:22,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:22,317 INFO L93 Difference]: Finished difference Result 37911 states and 57602 transitions. [2025-03-04 16:20:22,317 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37911 states and 57602 transitions. [2025-03-04 16:20:22,435 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21561 [2025-03-04 16:20:22,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37911 states to 37911 states and 57602 transitions. [2025-03-04 16:20:22,516 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22584 [2025-03-04 16:20:22,532 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22584 [2025-03-04 16:20:22,532 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37911 states and 57602 transitions. [2025-03-04 16:20:22,532 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:22,532 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37911 states and 57602 transitions. [2025-03-04 16:20:22,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37911 states and 57602 transitions. [2025-03-04 16:20:22,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37911 to 37911. [2025-03-04 16:20:23,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37911 states, 37911 states have (on average 1.5194007016433224) internal successors, (57602), 37910 states have internal predecessors, (57602), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:23,082 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37911 states to 37911 states and 57602 transitions. [2025-03-04 16:20:23,082 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37911 states and 57602 transitions. [2025-03-04 16:20:23,082 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:23,082 INFO L432 stractBuchiCegarLoop]: Abstraction has 37911 states and 57602 transitions. [2025-03-04 16:20:23,082 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 16:20:23,082 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37911 states and 57602 transitions. [2025-03-04 16:20:23,179 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 21561 [2025-03-04 16:20:23,180 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:23,180 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:23,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:23,181 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:23,181 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:20:23,181 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-03-04 16:20:23,181 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:23,181 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 2 times [2025-03-04 16:20:23,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:23,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [804128306] [2025-03-04 16:20:23,181 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:23,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:23,185 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:23,188 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:23,188 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:23,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:23,188 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:23,189 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:23,192 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:23,192 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:23,192 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:23,198 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:23,200 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:23,200 INFO L85 PathProgramCache]: Analyzing trace with hash 10706180, now seen corresponding path program 1 times [2025-03-04 16:20:23,200 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:23,200 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2130049357] [2025-03-04 16:20:23,200 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:23,200 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:23,204 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 54 statements into 1 equivalence classes. [2025-03-04 16:20:23,205 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 54 of 54 statements. [2025-03-04 16:20:23,206 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:23,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:23,220 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:23,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:23,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2130049357] [2025-03-04 16:20:23,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2130049357] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:23,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:23,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:23,221 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1416532486] [2025-03-04 16:20:23,221 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:23,221 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:23,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:23,222 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:23,222 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:23,222 INFO L87 Difference]: Start difference. First operand 37911 states and 57602 transitions. cyclomatic complexity: 19711 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:23,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:23,343 INFO L93 Difference]: Finished difference Result 37896 states and 56102 transitions. [2025-03-04 16:20:23,343 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37896 states and 56102 transitions. [2025-03-04 16:20:23,475 INFO L131 ngComponentsAnalysis]: Automaton has 156 accepting balls. 20997 [2025-03-04 16:20:23,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37896 states to 37896 states and 56102 transitions. [2025-03-04 16:20:23,565 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22575 [2025-03-04 16:20:23,581 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22575 [2025-03-04 16:20:23,581 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37896 states and 56102 transitions. [2025-03-04 16:20:23,581 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:23,581 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37896 states and 56102 transitions. [2025-03-04 16:20:23,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37896 states and 56102 transitions. [2025-03-04 16:20:24,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37896 to 34561. [2025-03-04 16:20:24,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 34561 states, 34561 states have (on average 1.486415323630682) internal successors, (51372), 34560 states have internal predecessors, (51372), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:24,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34561 states to 34561 states and 51372 transitions. [2025-03-04 16:20:24,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 34561 states and 51372 transitions. [2025-03-04 16:20:24,097 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:24,097 INFO L432 stractBuchiCegarLoop]: Abstraction has 34561 states and 51372 transitions. [2025-03-04 16:20:24,097 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 16:20:24,097 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 34561 states and 51372 transitions. [2025-03-04 16:20:24,165 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 19557 [2025-03-04 16:20:24,165 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:24,165 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:24,165 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:24,165 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:24,166 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" [2025-03-04 16:20:24,166 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume 0 == ~S1_addsub_st~0;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" [2025-03-04 16:20:24,166 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:24,166 INFO L85 PathProgramCache]: Analyzing trace with hash -627122419, now seen corresponding path program 3 times [2025-03-04 16:20:24,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:24,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1530104321] [2025-03-04 16:20:24,166 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:24,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:24,170 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:24,172 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:24,172 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:24,172 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:24,172 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:24,174 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 42 statements into 1 equivalence classes. [2025-03-04 16:20:24,175 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 42 of 42 statements. [2025-03-04 16:20:24,175 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:24,175 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:24,178 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:24,179 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:24,179 INFO L85 PathProgramCache]: Analyzing trace with hash -287373672, now seen corresponding path program 1 times [2025-03-04 16:20:24,179 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:24,179 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2136477324] [2025-03-04 16:20:24,179 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:24,179 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:24,185 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-04 16:20:24,186 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-04 16:20:24,186 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:24,186 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:24,193 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:24,193 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:24,193 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2136477324] [2025-03-04 16:20:24,193 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2136477324] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:24,193 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:24,193 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:24,193 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948744070] [2025-03-04 16:20:24,193 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:24,193 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:24,193 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:24,194 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:24,194 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:24,194 INFO L87 Difference]: Start difference. First operand 34561 states and 51372 transitions. cyclomatic complexity: 16831 Second operand has 3 states, 3 states have (on average 18.666666666666668) internal successors, (56), 3 states have internal predecessors, (56), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:24,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:24,319 INFO L93 Difference]: Finished difference Result 22250 states and 32307 transitions. [2025-03-04 16:20:24,319 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22250 states and 32307 transitions. [2025-03-04 16:20:24,381 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 12261 [2025-03-04 16:20:24,427 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22250 states to 22250 states and 32307 transitions. [2025-03-04 16:20:24,427 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13270 [2025-03-04 16:20:24,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13270 [2025-03-04 16:20:24,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22250 states and 32307 transitions. [2025-03-04 16:20:24,434 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:24,434 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22250 states and 32307 transitions. [2025-03-04 16:20:24,445 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22250 states and 32307 transitions. [2025-03-04 16:20:24,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22250 to 21925. [2025-03-04 16:20:24,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21925 states, 21925 states have (on average 1.4509464082098062) internal successors, (31812), 21924 states have internal predecessors, (31812), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:24,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21925 states to 21925 states and 31812 transitions. [2025-03-04 16:20:24,812 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21925 states and 31812 transitions. [2025-03-04 16:20:24,812 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:24,813 INFO L432 stractBuchiCegarLoop]: Abstraction has 21925 states and 31812 transitions. [2025-03-04 16:20:24,813 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-04 16:20:24,813 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21925 states and 31812 transitions. [2025-03-04 16:20:24,852 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 12261 [2025-03-04 16:20:24,852 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:24,852 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:24,853 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:24,853 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:24,853 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" [2025-03-04 16:20:24,853 INFO L754 eck$LassoCheckResult]: Loop: "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume 0 == ~N_generate_st~0;" "assume 0 == ~N_generate_st~0;havoc eval_#t~nondet4#1;eval_~tmp~0#1 := eval_#t~nondet4#1;havoc eval_#t~nondet4#1;" "assume 0 != eval_~tmp~0#1;~N_generate_st~0 := 1;assume { :begin_inline_N_generate } true;havoc N_generate_~a~0#1, N_generate_~b~0#1;havoc N_generate_~a~0#1;havoc N_generate_~b~0#1;~main_in1_val_t~0 := N_generate_~a~0#1;~main_in1_req_up~0 := 1;~main_in2_val_t~0 := N_generate_~b~0#1;~main_in2_req_up~0 := 1;" "havoc N_generate_~a~0#1, N_generate_~b~0#1;assume { :end_inline_N_generate } true;" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume ~main_clk_val~0 != ~main_clk_val_t~0;~main_clk_val~0 := ~main_clk_val_t~0;~main_clk_ev~0 := 0;" "assume 1 == ~main_clk_val~0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 2;" "~main_clk_req_up~0 := 0;" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume 0 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 1;" "assume !(0 == ~main_clk_neg_edge~0);" "assume 1 == ~main_clk_pos_edge~0;~N_generate_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S1_addsub_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S2_presdbl_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~S3_zero_st~0 := 0;" "assume 1 == ~main_clk_pos_edge~0;~D_print_st~0 := 0;" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume 1 == ~main_clk_pos_edge~0;~main_clk_pos_edge~0 := 2;" "assume !(1 == ~main_clk_neg_edge~0);" "assume 0 == ~N_generate_st~0;" "assume true;" [2025-03-04 16:20:24,854 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:24,854 INFO L85 PathProgramCache]: Analyzing trace with hash -2062638999, now seen corresponding path program 1 times [2025-03-04 16:20:24,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:24,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [891191440] [2025-03-04 16:20:24,854 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:24,855 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:24,859 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 44 statements into 1 equivalence classes. [2025-03-04 16:20:24,861 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 44 of 44 statements. [2025-03-04 16:20:24,861 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:24,861 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:24,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:24,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:24,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [891191440] [2025-03-04 16:20:24,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [891191440] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:24,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:24,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:24,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [884839691] [2025-03-04 16:20:24,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:24,886 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:24,887 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:24,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1087832447, now seen corresponding path program 1 times [2025-03-04 16:20:24,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:24,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1653375394] [2025-03-04 16:20:24,887 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:24,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:24,891 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 56 statements into 1 equivalence classes. [2025-03-04 16:20:24,892 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 56 of 56 statements. [2025-03-04 16:20:24,892 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:24,892 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:24,900 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:24,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:24,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1653375394] [2025-03-04 16:20:24,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1653375394] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:24,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:24,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:24,900 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1714175876] [2025-03-04 16:20:24,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:24,901 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:24,901 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:24,902 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:24,902 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:24,902 INFO L87 Difference]: Start difference. First operand 21925 states and 31812 transitions. cyclomatic complexity: 9902 Second operand has 4 states, 4 states have (on average 11.0) internal successors, (44), 4 states have internal predecessors, (44), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:24,953 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:24,953 INFO L93 Difference]: Finished difference Result 8622 states and 12403 transitions. [2025-03-04 16:20:24,953 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8622 states and 12403 transitions. [2025-03-04 16:20:24,973 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-03-04 16:20:24,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8622 states to 8622 states and 12403 transitions. [2025-03-04 16:20:24,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5722 [2025-03-04 16:20:24,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5722 [2025-03-04 16:20:24,991 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8622 states and 12403 transitions. [2025-03-04 16:20:24,991 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:24,991 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8622 states and 12403 transitions. [2025-03-04 16:20:24,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8622 states and 12403 transitions. [2025-03-04 16:20:25,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8622 to 8616. [2025-03-04 16:20:25,043 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8616 states, 8616 states have (on average 1.4388347260909935) internal successors, (12397), 8615 states have internal predecessors, (12397), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:25,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8616 states to 8616 states and 12397 transitions. [2025-03-04 16:20:25,053 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12397 transitions. [2025-03-04 16:20:25,054 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:25,054 INFO L432 stractBuchiCegarLoop]: Abstraction has 8616 states and 12397 transitions. [2025-03-04 16:20:25,054 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-04 16:20:25,054 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8616 states and 12397 transitions. [2025-03-04 16:20:25,072 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-03-04 16:20:25,072 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:25,072 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:25,074 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,074 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,074 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,077 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume 0 == ~main_clk_ev~0;~main_clk_ev~0 := 1;" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,078 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,079 INFO L85 PathProgramCache]: Analyzing trace with hash 1245953054, now seen corresponding path program 1 times [2025-03-04 16:20:25,079 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,079 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1522162060] [2025-03-04 16:20:25,079 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:25,079 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,083 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:25,085 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:25,086 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:25,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1522162060] [2025-03-04 16:20:25,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1522162060] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,115 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:25,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2065240783] [2025-03-04 16:20:25,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,116 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:25,116 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,116 INFO L85 PathProgramCache]: Analyzing trace with hash 1482777633, now seen corresponding path program 1 times [2025-03-04 16:20:25,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,117 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852084350] [2025-03-04 16:20:25,117 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:25,117 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,124 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 178 statements into 1 equivalence classes. [2025-03-04 16:20:25,125 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-03-04 16:20:25,125 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:25,125 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,144 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,144 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,146 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852084350] [2025-03-04 16:20:25,146 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852084350] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,146 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,146 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:25,146 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [749329857] [2025-03-04 16:20:25,147 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,149 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:25,150 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:25,150 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:25,150 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:25,150 INFO L87 Difference]: Start difference. First operand 8616 states and 12397 transitions. cyclomatic complexity: 3787 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:25,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:25,242 INFO L93 Difference]: Finished difference Result 9482 states and 13607 transitions. [2025-03-04 16:20:25,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9482 states and 13607 transitions. [2025-03-04 16:20:25,267 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 6032 [2025-03-04 16:20:25,283 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9482 states to 9482 states and 13607 transitions. [2025-03-04 16:20:25,284 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6282 [2025-03-04 16:20:25,287 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6282 [2025-03-04 16:20:25,287 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9482 states and 13607 transitions. [2025-03-04 16:20:25,287 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:25,287 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9482 states and 13607 transitions. [2025-03-04 16:20:25,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9482 states and 13607 transitions. [2025-03-04 16:20:25,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9482 to 8616. [2025-03-04 16:20:25,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8616 states, 8616 states have (on average 1.432799442896936) internal successors, (12345), 8615 states have internal predecessors, (12345), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:25,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8616 states to 8616 states and 12345 transitions. [2025-03-04 16:20:25,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8616 states and 12345 transitions. [2025-03-04 16:20:25,353 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:25,353 INFO L432 stractBuchiCegarLoop]: Abstraction has 8616 states and 12345 transitions. [2025-03-04 16:20:25,353 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-04 16:20:25,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8616 states and 12345 transitions. [2025-03-04 16:20:25,369 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5568 [2025-03-04 16:20:25,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:25,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:25,370 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,370 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,370 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume 0 == ~main_dbl_ev~0;~main_dbl_ev~0 := 1;" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,371 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,371 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,371 INFO L85 PathProgramCache]: Analyzing trace with hash -1350089443, now seen corresponding path program 1 times [2025-03-04 16:20:25,371 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,371 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [67938240] [2025-03-04 16:20:25,371 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:25,372 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,377 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:25,379 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:25,379 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:25,379 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,410 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [67938240] [2025-03-04 16:20:25,410 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [67938240] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:25,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1020446189] [2025-03-04 16:20:25,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,411 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:25,411 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,411 INFO L85 PathProgramCache]: Analyzing trace with hash -1525146528, now seen corresponding path program 1 times [2025-03-04 16:20:25,412 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,412 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [864359191] [2025-03-04 16:20:25,412 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:25,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,418 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 178 statements into 1 equivalence classes. [2025-03-04 16:20:25,419 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-03-04 16:20:25,419 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:25,419 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,441 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,441 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,441 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [864359191] [2025-03-04 16:20:25,441 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [864359191] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,441 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,441 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:25,442 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1687434253] [2025-03-04 16:20:25,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,443 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:25,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:25,443 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:25,443 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:25,443 INFO L87 Difference]: Start difference. First operand 8616 states and 12345 transitions. cyclomatic complexity: 3735 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:25,558 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:25,558 INFO L93 Difference]: Finished difference Result 12047 states and 17085 transitions. [2025-03-04 16:20:25,559 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 12047 states and 17085 transitions. [2025-03-04 16:20:25,719 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 7394 [2025-03-04 16:20:25,742 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 12047 states to 12047 states and 17085 transitions. [2025-03-04 16:20:25,743 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7640 [2025-03-04 16:20:25,747 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7640 [2025-03-04 16:20:25,748 INFO L73 IsDeterministic]: Start isDeterministic. Operand 12047 states and 17085 transitions. [2025-03-04 16:20:25,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2025-03-04 16:20:25,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 12047 states and 17085 transitions. [2025-03-04 16:20:25,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12047 states and 17085 transitions. [2025-03-04 16:20:25,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12047 to 8947. [2025-03-04 16:20:25,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8947 states, 8947 states have (on average 1.4225997541075222) internal successors, (12728), 8946 states have internal predecessors, (12728), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:25,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8947 states to 8947 states and 12728 transitions. [2025-03-04 16:20:25,830 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8947 states and 12728 transitions. [2025-03-04 16:20:25,831 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:20:25,831 INFO L432 stractBuchiCegarLoop]: Abstraction has 8947 states and 12728 transitions. [2025-03-04 16:20:25,831 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-04 16:20:25,831 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8947 states and 12728 transitions. [2025-03-04 16:20:25,847 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5914 [2025-03-04 16:20:25,847 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:25,848 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:25,849 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,849 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:25,849 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume 1 == ~main_dbl_ev~0;~main_dbl_ev~0 := 2;" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,849 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:25,850 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,850 INFO L85 PathProgramCache]: Analyzing trace with hash -1319069636, now seen corresponding path program 1 times [2025-03-04 16:20:25,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,852 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [619025487] [2025-03-04 16:20:25,852 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:25,852 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,856 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:25,858 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:25,858 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:25,858 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,885 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [619025487] [2025-03-04 16:20:25,885 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [619025487] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,885 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,885 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:20:25,885 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [122534537] [2025-03-04 16:20:25,885 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,886 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:20:25,886 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:25,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1525146528, now seen corresponding path program 2 times [2025-03-04 16:20:25,886 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:25,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1353099926] [2025-03-04 16:20:25,887 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:25,887 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:25,892 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 178 statements into 1 equivalence classes. [2025-03-04 16:20:25,893 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-03-04 16:20:25,893 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:25,893 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:25,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:25,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:25,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1353099926] [2025-03-04 16:20:25,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1353099926] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:25,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:25,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:25,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [462729878] [2025-03-04 16:20:25,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:25,910 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:25,912 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:25,912 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:20:25,912 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:20:25,912 INFO L87 Difference]: Start difference. First operand 8947 states and 12728 transitions. cyclomatic complexity: 3787 Second operand has 4 states, 4 states have (on average 22.25) internal successors, (89), 4 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:26,064 INFO L93 Difference]: Finished difference Result 9972 states and 14052 transitions. [2025-03-04 16:20:26,064 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9972 states and 14052 transitions. [2025-03-04 16:20:26,093 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 6556 [2025-03-04 16:20:26,108 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9972 states to 6834 states and 9656 transitions. [2025-03-04 16:20:26,108 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6834 [2025-03-04 16:20:26,111 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6834 [2025-03-04 16:20:26,112 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6834 states and 9656 transitions. [2025-03-04 16:20:26,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:26,117 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6834 states and 9656 transitions. [2025-03-04 16:20:26,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6834 states and 9656 transitions. [2025-03-04 16:20:26,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6834 to 3711. [2025-03-04 16:20:26,147 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3711 states, 3711 states have (on average 1.4195634599838318) internal successors, (5268), 3710 states have internal predecessors, (5268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3711 states to 3711 states and 5268 transitions. [2025-03-04 16:20:26,151 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3711 states and 5268 transitions. [2025-03-04 16:20:26,151 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:20:26,152 INFO L432 stractBuchiCegarLoop]: Abstraction has 3711 states and 5268 transitions. [2025-03-04 16:20:26,152 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-04 16:20:26,152 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3711 states and 5268 transitions. [2025-03-04 16:20:26,156 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3540 [2025-03-04 16:20:26,156 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:26,156 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:26,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,157 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,158 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,159 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,159 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 1 times [2025-03-04 16:20:26,159 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,159 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1615868544] [2025-03-04 16:20:26,159 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:26,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,165 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,167 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,167 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,167 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,168 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:26,170 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,173 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,173 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,173 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,180 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:26,181 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,181 INFO L85 PathProgramCache]: Analyzing trace with hash -1525146528, now seen corresponding path program 3 times [2025-03-04 16:20:26,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [983807415] [2025-03-04 16:20:26,181 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:26,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,187 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 178 statements into 1 equivalence classes. [2025-03-04 16:20:26,188 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 178 of 178 statements. [2025-03-04 16:20:26,188 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:26,188 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:26,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:26,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:26,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [983807415] [2025-03-04 16:20:26,206 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [983807415] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:26,206 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:26,206 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:26,206 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [786015586] [2025-03-04 16:20:26,206 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:26,207 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:26,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:26,207 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:26,207 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:26,207 INFO L87 Difference]: Start difference. First operand 3711 states and 5268 transitions. cyclomatic complexity: 1559 Second operand has 3 states, 3 states have (on average 59.333333333333336) internal successors, (178), 3 states have internal predecessors, (178), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:26,226 INFO L93 Difference]: Finished difference Result 3711 states and 5256 transitions. [2025-03-04 16:20:26,226 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3711 states and 5256 transitions. [2025-03-04 16:20:26,234 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3540 [2025-03-04 16:20:26,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3711 states to 3711 states and 5256 transitions. [2025-03-04 16:20:26,243 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3711 [2025-03-04 16:20:26,244 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3711 [2025-03-04 16:20:26,244 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3711 states and 5256 transitions. [2025-03-04 16:20:26,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:26,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3711 states and 5256 transitions. [2025-03-04 16:20:26,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3711 states and 5256 transitions. [2025-03-04 16:20:26,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3711 to 3711. [2025-03-04 16:20:26,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3711 states, 3711 states have (on average 1.4163298302344383) internal successors, (5256), 3710 states have internal predecessors, (5256), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3711 states to 3711 states and 5256 transitions. [2025-03-04 16:20:26,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3711 states and 5256 transitions. [2025-03-04 16:20:26,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:26,277 INFO L432 stractBuchiCegarLoop]: Abstraction has 3711 states and 5256 transitions. [2025-03-04 16:20:26,277 INFO L338 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2025-03-04 16:20:26,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3711 states and 5256 transitions. [2025-03-04 16:20:26,283 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 3540 [2025-03-04 16:20:26,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:26,284 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:26,285 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,285 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,285 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,285 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume 0 == ~main_in2_ev~0;~main_in2_ev~0 := 1;" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume 1 == ~main_in2_ev~0;~main_in2_ev~0 := 2;" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,286 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,286 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 2 times [2025-03-04 16:20:26,286 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,286 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [158620697] [2025-03-04 16:20:26,286 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:26,286 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,291 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,294 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,295 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:26,295 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,295 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:26,297 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,300 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,301 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,301 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,313 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:26,315 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,315 INFO L85 PathProgramCache]: Analyzing trace with hash -1786134912, now seen corresponding path program 1 times [2025-03-04 16:20:26,315 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1724865731] [2025-03-04 16:20:26,315 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:26,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,321 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:26,323 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:26,323 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,323 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:26,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:26,380 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:26,380 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1724865731] [2025-03-04 16:20:26,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1724865731] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:26,380 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:26,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:26,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [266333058] [2025-03-04 16:20:26,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:26,380 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:26,381 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:26,381 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:26,381 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:26,381 INFO L87 Difference]: Start difference. First operand 3711 states and 5256 transitions. cyclomatic complexity: 1547 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:26,442 INFO L93 Difference]: Finished difference Result 7417 states and 10393 transitions. [2025-03-04 16:20:26,442 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7417 states and 10393 transitions. [2025-03-04 16:20:26,464 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7080 [2025-03-04 16:20:26,477 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7417 states to 7417 states and 10393 transitions. [2025-03-04 16:20:26,478 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7417 [2025-03-04 16:20:26,480 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7417 [2025-03-04 16:20:26,480 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7417 states and 10393 transitions. [2025-03-04 16:20:26,487 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:26,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7417 states and 10393 transitions. [2025-03-04 16:20:26,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7417 states and 10393 transitions. [2025-03-04 16:20:26,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7417 to 7417. [2025-03-04 16:20:26,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7417 states, 7417 states have (on average 1.4012403936901712) internal successors, (10393), 7416 states have internal predecessors, (10393), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7417 states to 7417 states and 10393 transitions. [2025-03-04 16:20:26,542 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7417 states and 10393 transitions. [2025-03-04 16:20:26,543 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:26,543 INFO L432 stractBuchiCegarLoop]: Abstraction has 7417 states and 10393 transitions. [2025-03-04 16:20:26,543 INFO L338 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2025-03-04 16:20:26,543 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7417 states and 10393 transitions. [2025-03-04 16:20:26,555 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7080 [2025-03-04 16:20:26,555 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:26,555 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:26,556 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,556 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:26,556 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,556 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume 0 == ~main_sum_ev~0;~main_sum_ev~0 := 1;" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume 1 == ~main_sum_ev~0;~main_sum_ev~0 := 2;" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:26,557 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,557 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 3 times [2025-03-04 16:20:26,557 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,557 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [119173310] [2025-03-04 16:20:26,557 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:20:26,557 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,562 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,566 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,566 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:20:26,566 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,566 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:26,568 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:26,570 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:26,570 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,570 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:26,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:26,578 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:26,578 INFO L85 PathProgramCache]: Analyzing trace with hash 404569728, now seen corresponding path program 1 times [2025-03-04 16:20:26,578 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:26,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221616315] [2025-03-04 16:20:26,579 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:26,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:26,584 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:26,586 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:26,586 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:26,586 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:26,615 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:26,615 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:26,615 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221616315] [2025-03-04 16:20:26,615 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221616315] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:26,615 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:26,615 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:26,616 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339589915] [2025-03-04 16:20:26,616 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:26,616 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:26,616 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:26,617 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:26,617 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:26,617 INFO L87 Difference]: Start difference. First operand 7417 states and 10393 transitions. cyclomatic complexity: 2978 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:26,722 INFO L93 Difference]: Finished difference Result 14823 states and 20545 transitions. [2025-03-04 16:20:26,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14823 states and 20545 transitions. [2025-03-04 16:20:26,786 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14160 [2025-03-04 16:20:26,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14823 states to 14823 states and 20545 transitions. [2025-03-04 16:20:26,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14823 [2025-03-04 16:20:26,837 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14823 [2025-03-04 16:20:26,837 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14823 states and 20545 transitions. [2025-03-04 16:20:26,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:26,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14823 states and 20545 transitions. [2025-03-04 16:20:26,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14823 states and 20545 transitions. [2025-03-04 16:20:26,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14823 to 14823. [2025-03-04 16:20:26,977 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14823 states, 14823 states have (on average 1.3860217229980436) internal successors, (20545), 14822 states have internal predecessors, (20545), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:26,998 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14823 states to 14823 states and 20545 transitions. [2025-03-04 16:20:26,999 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14823 states and 20545 transitions. [2025-03-04 16:20:26,999 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:26,999 INFO L432 stractBuchiCegarLoop]: Abstraction has 14823 states and 20545 transitions. [2025-03-04 16:20:26,999 INFO L338 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2025-03-04 16:20:26,999 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14823 states and 20545 transitions. [2025-03-04 16:20:27,042 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 14160 [2025-03-04 16:20:27,043 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:27,043 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:27,044 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:27,044 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:27,045 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:27,045 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume 0 == ~main_diff_ev~0;~main_diff_ev~0 := 1;" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume 1 == ~main_diff_ev~0;~main_diff_ev~0 := 2;" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:27,045 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:27,045 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 4 times [2025-03-04 16:20:27,045 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:27,045 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915375473] [2025-03-04 16:20:27,045 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:20:27,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:27,050 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 89 statements into 2 equivalence classes. [2025-03-04 16:20:27,053 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:27,054 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:20:27,054 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:27,054 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:27,055 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:27,058 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:27,058 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:27,058 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:27,067 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:27,067 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:27,068 INFO L85 PathProgramCache]: Analyzing trace with hash 890879616, now seen corresponding path program 1 times [2025-03-04 16:20:27,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:27,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [54645644] [2025-03-04 16:20:27,068 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:27,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:27,074 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:27,077 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:27,077 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:27,077 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:27,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:27,110 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:27,110 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [54645644] [2025-03-04 16:20:27,110 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [54645644] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:27,110 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:27,110 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:27,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1784529382] [2025-03-04 16:20:27,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:27,111 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:27,111 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:27,111 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:27,111 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:27,111 INFO L87 Difference]: Start difference. First operand 14823 states and 20545 transitions. cyclomatic complexity: 5724 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:27,216 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:27,216 INFO L93 Difference]: Finished difference Result 29623 states and 40605 transitions. [2025-03-04 16:20:27,216 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 29623 states and 40605 transitions. [2025-03-04 16:20:27,336 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28320 [2025-03-04 16:20:27,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 29623 states to 29623 states and 40605 transitions. [2025-03-04 16:20:27,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 29623 [2025-03-04 16:20:27,432 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 29623 [2025-03-04 16:20:27,432 INFO L73 IsDeterministic]: Start isDeterministic. Operand 29623 states and 40605 transitions. [2025-03-04 16:20:27,455 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:27,455 INFO L218 hiAutomatonCegarLoop]: Abstraction has 29623 states and 40605 transitions. [2025-03-04 16:20:27,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29623 states and 40605 transitions. [2025-03-04 16:20:27,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29623 to 29623. [2025-03-04 16:20:27,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 29623 states, 29623 states have (on average 1.370725449819397) internal successors, (40605), 29622 states have internal predecessors, (40605), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:27,759 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29623 states to 29623 states and 40605 transitions. [2025-03-04 16:20:27,759 INFO L240 hiAutomatonCegarLoop]: Abstraction has 29623 states and 40605 transitions. [2025-03-04 16:20:27,759 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:27,760 INFO L432 stractBuchiCegarLoop]: Abstraction has 29623 states and 40605 transitions. [2025-03-04 16:20:27,760 INFO L338 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2025-03-04 16:20:27,760 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 29623 states and 40605 transitions. [2025-03-04 16:20:27,854 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 28320 [2025-03-04 16:20:27,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:27,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:27,857 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:27,857 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:27,857 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:27,857 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume 0 == ~main_pres_ev~0;~main_pres_ev~0 := 1;" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume 1 == ~main_pres_ev~0;~main_pres_ev~0 := 2;" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:27,858 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:27,858 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 5 times [2025-03-04 16:20:27,858 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:27,858 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315400811] [2025-03-04 16:20:27,858 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:20:27,858 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:27,863 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:27,866 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:27,866 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:27,866 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:27,866 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:27,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:27,870 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:27,870 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:27,870 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:27,880 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:27,880 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:27,880 INFO L85 PathProgramCache]: Analyzing trace with hash 1183661696, now seen corresponding path program 1 times [2025-03-04 16:20:27,880 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:27,881 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [885081290] [2025-03-04 16:20:27,881 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:27,881 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:27,888 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:27,890 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:27,890 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:27,890 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:27,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:27,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:27,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [885081290] [2025-03-04 16:20:27,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [885081290] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:27,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:27,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:27,918 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [693185105] [2025-03-04 16:20:27,918 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:27,918 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:27,918 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:27,919 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:27,919 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:27,919 INFO L87 Difference]: Start difference. First operand 29623 states and 40605 transitions. cyclomatic complexity: 10984 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:28,098 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:28,098 INFO L93 Difference]: Finished difference Result 59199 states and 80237 transitions. [2025-03-04 16:20:28,098 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 59199 states and 80237 transitions. [2025-03-04 16:20:28,375 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640 [2025-03-04 16:20:28,528 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 59199 states to 59199 states and 80237 transitions. [2025-03-04 16:20:28,528 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 59199 [2025-03-04 16:20:28,567 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 59199 [2025-03-04 16:20:28,568 INFO L73 IsDeterministic]: Start isDeterministic. Operand 59199 states and 80237 transitions. [2025-03-04 16:20:28,625 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:28,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-03-04 16:20:28,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59199 states and 80237 transitions. [2025-03-04 16:20:29,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59199 to 59199. [2025-03-04 16:20:29,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 59199 states, 59199 states have (on average 1.3553776246220375) internal successors, (80237), 59198 states have internal predecessors, (80237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:29,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59199 states to 59199 states and 80237 transitions. [2025-03-04 16:20:29,236 INFO L240 hiAutomatonCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-03-04 16:20:29,237 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:29,237 INFO L432 stractBuchiCegarLoop]: Abstraction has 59199 states and 80237 transitions. [2025-03-04 16:20:29,237 INFO L338 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2025-03-04 16:20:29,237 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 59199 states and 80237 transitions. [2025-03-04 16:20:29,427 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 56640 [2025-03-04 16:20:29,427 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:29,427 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:29,431 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:29,431 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:29,432 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:29,432 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume 0 == ~main_zero_ev~0;~main_zero_ev~0 := 1;" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume 1 == ~main_zero_ev~0;~main_zero_ev~0 := 2;" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:29,432 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:29,432 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 6 times [2025-03-04 16:20:29,432 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:29,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029506811] [2025-03-04 16:20:29,432 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:20:29,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:29,439 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:29,441 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:29,441 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:20:29,441 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:29,441 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:29,443 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:29,445 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:29,445 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:29,445 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:29,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:29,457 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:29,457 INFO L85 PathProgramCache]: Analyzing trace with hash 1322455679, now seen corresponding path program 1 times [2025-03-04 16:20:29,458 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:29,458 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [817230336] [2025-03-04 16:20:29,458 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:29,458 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:29,465 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:29,468 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:29,468 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:29,468 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:29,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:29,498 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:29,498 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [817230336] [2025-03-04 16:20:29,498 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [817230336] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:29,498 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:29,498 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:29,498 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [563848153] [2025-03-04 16:20:29,498 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:29,499 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:29,499 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:29,499 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:29,499 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:29,499 INFO L87 Difference]: Start difference. First operand 59199 states and 80237 transitions. cyclomatic complexity: 21040 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:29,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:29,799 INFO L93 Difference]: Finished difference Result 118207 states and 158749 transitions. [2025-03-04 16:20:29,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 118207 states and 158749 transitions. [2025-03-04 16:20:30,327 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 113280 [2025-03-04 16:20:30,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 118207 states to 118207 states and 158749 transitions. [2025-03-04 16:20:30,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 118207 [2025-03-04 16:20:30,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 118207 [2025-03-04 16:20:30,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 118207 states and 158749 transitions. [2025-03-04 16:20:30,824 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:30,825 INFO L218 hiAutomatonCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-03-04 16:20:30,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118207 states and 158749 transitions. [2025-03-04 16:20:31,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118207 to 118207. [2025-03-04 16:20:31,666 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 118207 states, 118207 states have (on average 1.342974612332603) internal successors, (158749), 118206 states have internal predecessors, (158749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:31,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118207 states to 118207 states and 158749 transitions. [2025-03-04 16:20:31,860 INFO L240 hiAutomatonCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-03-04 16:20:31,860 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:31,860 INFO L432 stractBuchiCegarLoop]: Abstraction has 118207 states and 158749 transitions. [2025-03-04 16:20:31,860 INFO L338 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2025-03-04 16:20:31,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 118207 states and 158749 transitions. [2025-03-04 16:20:32,286 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 113280 [2025-03-04 16:20:32,286 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:32,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:32,299 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:32,299 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:32,300 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:32,300 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume 1 == ~main_clk_ev~0;~main_clk_ev~0 := 2;" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:32,300 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:32,300 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 7 times [2025-03-04 16:20:32,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:32,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648487475] [2025-03-04 16:20:32,300 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:20:32,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:32,307 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:32,309 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:32,310 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:32,310 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:32,310 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:32,312 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:32,314 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:32,314 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:32,314 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:32,324 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:32,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:32,325 INFO L85 PathProgramCache]: Analyzing trace with hash 1578078847, now seen corresponding path program 1 times [2025-03-04 16:20:32,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:32,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1163608093] [2025-03-04 16:20:32,325 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:32,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:32,332 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:32,335 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:32,335 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:32,335 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:32,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:32,364 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:32,364 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1163608093] [2025-03-04 16:20:32,364 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1163608093] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:32,364 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:32,364 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:20:32,364 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1106413928] [2025-03-04 16:20:32,364 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:32,365 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:32,365 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:32,365 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:20:32,365 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:20:32,365 INFO L87 Difference]: Start difference. First operand 118207 states and 158749 transitions. cyclomatic complexity: 40544 Second operand has 3 states, 3 states have (on average 60.666666666666664) internal successors, (182), 3 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:32,866 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:32,866 INFO L93 Difference]: Finished difference Result 209343 states and 282429 transitions. [2025-03-04 16:20:32,866 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 209343 states and 282429 transitions. [2025-03-04 16:20:33,865 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204416 [2025-03-04 16:20:34,478 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 209343 states to 209343 states and 282429 transitions. [2025-03-04 16:20:34,479 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 209343 [2025-03-04 16:20:34,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 209343 [2025-03-04 16:20:34,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 209343 states and 282429 transitions. [2025-03-04 16:20:34,780 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:34,781 INFO L218 hiAutomatonCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-03-04 16:20:34,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209343 states and 282429 transitions. [2025-03-04 16:20:36,521 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209343 to 209343. [2025-03-04 16:20:36,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209343 states, 209343 states have (on average 1.3491208208538141) internal successors, (282429), 209342 states have internal predecessors, (282429), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:37,060 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209343 states to 209343 states and 282429 transitions. [2025-03-04 16:20:37,061 INFO L240 hiAutomatonCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-03-04 16:20:37,061 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:20:37,061 INFO L432 stractBuchiCegarLoop]: Abstraction has 209343 states and 282429 transitions. [2025-03-04 16:20:37,061 INFO L338 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2025-03-04 16:20:37,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209343 states and 282429 transitions. [2025-03-04 16:20:37,817 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 204416 [2025-03-04 16:20:37,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:20:37,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:20:37,838 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:37,838 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:20:37,838 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(17, 2);call #Ultimate.allocInit(12, 3);~main_in1_val~0 := 0;~main_in1_val_t~0 := 0;~main_in1_ev~0 := 0;~main_in1_req_up~0 := 0;~main_in2_val~0 := 0;~main_in2_val_t~0 := 0;~main_in2_ev~0 := 0;~main_in2_req_up~0 := 0;~main_diff_val~0 := 0;~main_diff_val_t~0 := 0;~main_diff_ev~0 := 0;~main_diff_req_up~0 := 0;~main_sum_val~0 := 0;~main_sum_val_t~0 := 0;~main_sum_ev~0 := 0;~main_sum_req_up~0 := 0;~main_pres_val~0 := 0;~main_pres_val_t~0 := 0;~main_pres_ev~0 := 0;~main_pres_req_up~0 := 0;~main_dbl_val~0 := 0;~main_dbl_val_t~0 := 0;~main_dbl_ev~0 := 0;~main_dbl_req_up~0 := 0;~main_zero_val~0 := 0;~main_zero_val_t~0 := 0;~main_zero_ev~0 := 0;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_val_t~0 := 0;~main_clk_ev~0 := 0;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 0;~main_clk_neg_edge~0 := 0;~N_generate_st~0 := 0;~N_generate_i~0 := 0;~S1_addsub_st~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_st~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_st~0 := 0;~S3_zero_i~0 := 0;~D_z~0 := 0;~D_print_st~0 := 0;~D_print_i~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~count~0#1, main_~__retres2~0#1;havoc main_~count~0#1;havoc main_~__retres2~0#1;~main_in1_ev~0 := 2;~main_in1_req_up~0 := 0;~main_in2_ev~0 := 2;~main_in2_req_up~0 := 0;~main_diff_ev~0 := 2;~main_diff_req_up~0 := 0;~main_sum_ev~0 := 2;~main_sum_req_up~0 := 0;~main_pres_ev~0 := 2;~main_pres_req_up~0 := 0;~main_dbl_ev~0 := 2;~main_dbl_req_up~0 := 0;~main_zero_ev~0 := 2;~main_zero_req_up~0 := 0;~main_clk_val~0 := 0;~main_clk_ev~0 := 2;~main_clk_req_up~0 := 0;~main_clk_pos_edge~0 := 2;~main_clk_neg_edge~0 := 2;main_~count~0#1 := 0;~N_generate_i~0 := 0;~S1_addsub_i~0 := 0;~S2_presdbl_i~0 := 0;~S3_zero_i~0 := 0;~D_print_i~0 := 0;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:37,838 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "~main_clk_val_t~0 := 1;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;main_~count~0#1 := 1 + main_~count~0#1;" "assume !(5 == main_~count~0#1);" "~main_clk_val_t~0 := 0;~main_clk_req_up~0 := 1;assume { :begin_inline_start_simulation } true;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~kernel_st~0#1;start_simulation_~kernel_st~0#1 := 0;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume 1 == ~main_clk_req_up~0;" "assume !(~main_clk_val~0 != ~main_clk_val_t~0);" "~main_clk_req_up~0 := 0;" "assume !(1 == ~N_generate_i~0);~N_generate_st~0 := 2;" "assume !(1 == ~S1_addsub_i~0);~S1_addsub_st~0 := 2;" "assume !(1 == ~S2_presdbl_i~0);~S2_presdbl_st~0 := 2;" "assume !(1 == ~S3_zero_i~0);~S3_zero_st~0 := 2;" "assume !(1 == ~D_print_i~0);~D_print_st~0 := 2;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;havoc eval_~tmp~0#1;havoc eval_~tmp___0~0#1;havoc eval_~tmp___1~0#1;havoc eval_~tmp___2~0#1;havoc eval_~tmp___3~0#1;" "assume true;" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc eval_#t~nondet4#1, eval_#t~nondet5#1, eval_#t~nondet6#1, eval_#t~nondet7#1, eval_#t~nondet8#1, eval_~tmp~0#1, eval_~tmp___0~0#1, eval_~tmp___1~0#1, eval_~tmp___2~0#1, eval_~tmp___3~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;" "assume !(1 == ~main_in1_req_up~0);" "assume !(1 == ~main_in2_req_up~0);" "assume !(1 == ~main_sum_req_up~0);" "assume !(1 == ~main_diff_req_up~0);" "assume !(1 == ~main_pres_req_up~0);" "assume !(1 == ~main_dbl_req_up~0);" "assume !(1 == ~main_zero_req_up~0);" "assume !(1 == ~main_clk_req_up~0);" "start_simulation_~kernel_st~0#1 := 3;" "assume !(0 == ~main_in1_ev~0);" "assume !(0 == ~main_in2_ev~0);" "assume !(0 == ~main_sum_ev~0);" "assume !(0 == ~main_diff_ev~0);" "assume !(0 == ~main_pres_ev~0);" "assume !(0 == ~main_dbl_ev~0);" "assume !(0 == ~main_zero_ev~0);" "assume !(0 == ~main_clk_ev~0);" "assume !(0 == ~main_clk_pos_edge~0);" "assume !(0 == ~main_clk_neg_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_in1_ev~0);" "assume !(1 == ~main_in2_ev~0);" "assume !(1 == ~main_sum_ev~0);" "assume !(1 == ~main_diff_ev~0);" "assume !(1 == ~main_pres_ev~0);" "assume !(1 == ~main_dbl_ev~0);" "assume !(1 == ~main_zero_ev~0);" "assume !(1 == ~main_clk_ev~0);" "assume !(1 == ~main_clk_pos_edge~0);" "assume !(1 == ~main_clk_neg_edge~0);" "assume !(0 == ~N_generate_st~0);" "assume !(0 == ~S1_addsub_st~0);" "assume !(0 == ~S2_presdbl_st~0);" "assume !(0 == ~S3_zero_st~0);" "assume !(0 == ~D_print_st~0);" "havoc start_simulation_~kernel_st~0#1;assume { :end_inline_start_simulation } true;" [2025-03-04 16:20:37,839 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:37,839 INFO L85 PathProgramCache]: Analyzing trace with hash 1178946301, now seen corresponding path program 8 times [2025-03-04 16:20:37,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:37,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [590979345] [2025-03-04 16:20:37,839 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:20:37,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:37,844 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:37,846 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:37,847 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:20:37,847 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:37,847 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:20:37,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 89 statements into 1 equivalence classes. [2025-03-04 16:20:37,851 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 89 of 89 statements. [2025-03-04 16:20:37,851 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:37,851 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:20:37,860 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:20:37,862 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:20:37,862 INFO L85 PathProgramCache]: Analyzing trace with hash 1701820031, now seen corresponding path program 1 times [2025-03-04 16:20:37,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:20:37,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076035749] [2025-03-04 16:20:37,862 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:20:37,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:20:37,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 182 statements into 1 equivalence classes. [2025-03-04 16:20:37,872 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 182 of 182 statements. [2025-03-04 16:20:37,872 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:20:37,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:20:37,953 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:20:37,954 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:20:37,954 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076035749] [2025-03-04 16:20:37,954 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076035749] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:20:37,954 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:20:37,954 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2025-03-04 16:20:37,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [304461860] [2025-03-04 16:20:37,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:20:37,955 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:20:37,955 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:20:37,955 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2025-03-04 16:20:37,955 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2025-03-04 16:20:37,955 INFO L87 Difference]: Start difference. First operand 209343 states and 282429 transitions. cyclomatic complexity: 73088 Second operand has 5 states, 5 states have (on average 36.4) internal successors, (182), 5 states have internal predecessors, (182), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:20:38,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:20:38,513 INFO L93 Difference]: Finished difference Result 216511 states and 293485 transitions. [2025-03-04 16:20:38,513 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216511 states and 293485 transitions. [2025-03-04 16:20:39,442 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 211584 [2025-03-04 16:20:40,063 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216511 states to 216511 states and 293485 transitions. [2025-03-04 16:20:40,063 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216511 [2025-03-04 16:20:40,219 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216511 [2025-03-04 16:20:40,219 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216511 states and 293485 transitions. [2025-03-04 16:20:40,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:20:40,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216511 states and 293485 transitions. [2025-03-04 16:20:40,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216511 states and 293485 transitions.