./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/ldv-sets/test_mutex_double_lock.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/ldv-sets/test_mutex_double_lock.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 869ef2ac3e655b6efbdfa5c05d637a0f622008da83d6042d15962fe695aee939 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:00:38,086 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:00:38,143 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:00:38,149 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:00:38,150 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:00:38,151 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:00:38,173 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:00:38,173 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:00:38,174 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:00:38,174 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:00:38,174 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:00:38,175 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:00:38,175 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:00:38,175 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:00:38,176 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:00:38,176 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:00:38,176 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:00:38,177 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:00:38,178 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:00:38,178 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:00:38,178 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:00:38,178 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:00:38,178 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:00:38,179 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 869ef2ac3e655b6efbdfa5c05d637a0f622008da83d6042d15962fe695aee939 [2025-03-04 16:00:38,406 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:00:38,411 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:00:38,413 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:00:38,413 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:00:38,414 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:00:38,415 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/ldv-sets/test_mutex_double_lock.i [2025-03-04 16:00:39,556 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00bfc7e28/9553c9fa52654965a28f6221b1412180/FLAG466616f7a [2025-03-04 16:00:39,842 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:00:39,844 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/ldv-sets/test_mutex_double_lock.i [2025-03-04 16:00:39,857 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00bfc7e28/9553c9fa52654965a28f6221b1412180/FLAG466616f7a [2025-03-04 16:00:40,129 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/00bfc7e28/9553c9fa52654965a28f6221b1412180 [2025-03-04 16:00:40,131 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:00:40,132 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:00:40,132 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:00:40,132 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:00:40,135 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:00:40,136 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,137 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4922ca42 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40, skipping insertion in model container [2025-03-04 16:00:40,137 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,166 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:00:40,432 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:00:40,442 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:00:40,475 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:00:40,496 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:00:40,496 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40 WrapperNode [2025-03-04 16:00:40,496 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:00:40,497 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:00:40,497 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:00:40,497 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:00:40,501 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,516 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,542 INFO L138 Inliner]: procedures = 139, calls = 60, calls flagged for inlining = 29, calls inlined = 42, statements flattened = 419 [2025-03-04 16:00:40,543 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:00:40,543 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:00:40,543 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:00:40,543 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:00:40,548 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,549 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,554 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,581 INFO L175 MemorySlicer]: Split 51 memory accesses to 2 slices as follows [2, 49]. 96 percent of accesses are in the largest equivalence class. The 4 initializations are split as follows [2, 2]. The 14 writes are split as follows [0, 14]. [2025-03-04 16:00:40,584 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,584 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,596 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,598 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,599 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,600 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,606 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:00:40,607 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:00:40,607 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:00:40,607 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:00:40,608 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (1/1) ... [2025-03-04 16:00:40,612 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:00:40,622 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:00:40,632 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:00:40,635 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:00:40,649 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$#0 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~$Pointer$#1 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-04 16:00:40,650 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:00:40,651 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:00:40,765 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:00:40,766 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:00:41,176 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L663: havoc ldv_set_empty_#t~ret31#1; [2025-03-04 16:00:41,176 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L620: havoc ldv_list_empty_#t~mem10#1.base, ldv_list_empty_#t~mem10#1.offset; [2025-03-04 16:00:41,233 INFO L? ?]: Removed 244 outVars from TransFormulas that were not future-live. [2025-03-04 16:00:41,233 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:00:41,243 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:00:41,244 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:00:41,244 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:00:41 BoogieIcfgContainer [2025-03-04 16:00:41,244 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:00:41,245 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:00:41,245 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:00:41,249 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:00:41,250 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:00:41,250 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:00:40" (1/3) ... [2025-03-04 16:00:41,251 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9b90caf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:00:41, skipping insertion in model container [2025-03-04 16:00:41,251 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:00:41,251 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:00:40" (2/3) ... [2025-03-04 16:00:41,252 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@9b90caf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:00:41, skipping insertion in model container [2025-03-04 16:00:41,252 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:00:41,252 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:00:41" (3/3) ... [2025-03-04 16:00:41,253 INFO L363 chiAutomizerObserver]: Analyzing ICFG test_mutex_double_lock.i [2025-03-04 16:00:41,288 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:00:41,289 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:00:41,289 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:00:41,289 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:00:41,289 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:00:41,289 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:00:41,289 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:00:41,289 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:00:41,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 83 states, 82 states have (on average 1.3902439024390243) internal successors, (114), 82 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:41,308 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22 [2025-03-04 16:00:41,308 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:41,310 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:41,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:41,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 16:00:41,314 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:00:41,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 83 states, 82 states have (on average 1.3902439024390243) internal successors, (114), 82 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:41,317 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 22 [2025-03-04 16:00:41,318 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:41,318 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:41,319 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:41,319 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 16:00:41,323 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(8, 3);~#mutexes~0.base, ~#mutexes~0.offset := 3, 0;call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, ~#mutexes~0.offset, 4);call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, 4 + ~#mutexes~0.offset, 4);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_foo } true;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset, foo_#t~ret36#1.base, foo_#t~ret36#1.offset, foo_~m1~0#1.base, foo_~m1~0#1.offset, foo_~m2~0#1.base, foo_~m2~0#1.offset;assume { :begin_inline_ldv_initialize } true;" "assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret35#1.base, foo_#t~ret35#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m1~0#1.base, foo_~m1~0#1.offset := foo_#t~ret35#1.base, foo_#t~ret35#1.offset;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret36#1.base, foo_#t~ret36#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m2~0#1.base, foo_~m2~0#1.offset := foo_#t~ret36#1.base, foo_#t~ret36#1.offset;havoc foo_#t~ret36#1.base, foo_#t~ret36#1.offset;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" [2025-03-04 16:00:41,323 INFO L754 eck$LassoCheckResult]: Loop: "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" "assume !(ldv_is_in_set_#t~mem28#1.base == ldv_is_in_set_~e#1.base && ldv_is_in_set_#t~mem28#1.offset == ldv_is_in_set_~e#1.offset);havoc ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset;call ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, 4 + ldv_is_in_set_~m~1#1.offset, 4);ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset := ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;havoc ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset := ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset - 4;havoc ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;havoc ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;" [2025-03-04 16:00:41,328 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:41,328 INFO L85 PathProgramCache]: Analyzing trace with hash -459900790, now seen corresponding path program 1 times [2025-03-04 16:00:41,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:41,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254277477] [2025-03-04 16:00:41,334 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:41,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:41,398 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:00:41,446 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:00:41,446 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:41,446 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:41,447 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:41,454 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 9 statements into 1 equivalence classes. [2025-03-04 16:00:41,472 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 9 of 9 statements. [2025-03-04 16:00:41,472 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:41,473 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:41,488 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:41,489 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:41,489 INFO L85 PathProgramCache]: Analyzing trace with hash 5184, now seen corresponding path program 1 times [2025-03-04 16:00:41,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:41,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395518943] [2025-03-04 16:00:41,490 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:41,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:41,496 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:41,500 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:41,501 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:41,501 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:41,501 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:41,502 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:41,507 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:41,509 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:41,509 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:41,511 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:41,513 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:41,513 INFO L85 PathProgramCache]: Analyzing trace with hash 416976521, now seen corresponding path program 1 times [2025-03-04 16:00:41,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:41,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [788461256] [2025-03-04 16:00:41,515 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:41,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:41,523 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 11 statements into 1 equivalence classes. [2025-03-04 16:00:41,534 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 11 of 11 statements. [2025-03-04 16:00:41,537 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:41,538 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:00:41,762 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:00:41,762 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:00:41,762 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [788461256] [2025-03-04 16:00:41,763 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [788461256] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:00:41,763 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:00:41,763 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:00:41,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468600098] [2025-03-04 16:00:41,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:00:41,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:00:41,910 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:00:41,910 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:00:41,912 INFO L87 Difference]: Start difference. First operand has 83 states, 82 states have (on average 1.3902439024390243) internal successors, (114), 82 states have internal predecessors, (114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 4 states, 4 states have (on average 2.75) internal successors, (11), 3 states have internal predecessors, (11), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:42,119 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:00:42,121 INFO L93 Difference]: Finished difference Result 120 states and 137 transitions. [2025-03-04 16:00:42,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 120 states and 137 transitions. [2025-03-04 16:00:42,124 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 24 [2025-03-04 16:00:42,131 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 120 states to 91 states and 108 transitions. [2025-03-04 16:00:42,132 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91 [2025-03-04 16:00:42,133 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91 [2025-03-04 16:00:42,133 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91 states and 108 transitions. [2025-03-04 16:00:42,134 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:00:42,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91 states and 108 transitions. [2025-03-04 16:00:42,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states and 108 transitions. [2025-03-04 16:00:42,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 82. [2025-03-04 16:00:42,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 82 states, 82 states have (on average 1.1951219512195121) internal successors, (98), 81 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:42,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 98 transitions. [2025-03-04 16:00:42,175 INFO L240 hiAutomatonCegarLoop]: Abstraction has 82 states and 98 transitions. [2025-03-04 16:00:42,177 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:00:42,181 INFO L432 stractBuchiCegarLoop]: Abstraction has 82 states and 98 transitions. [2025-03-04 16:00:42,181 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:00:42,182 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 82 states and 98 transitions. [2025-03-04 16:00:42,185 INFO L131 ngComponentsAnalysis]: Automaton has 7 accepting balls. 21 [2025-03-04 16:00:42,185 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:42,185 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:42,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:42,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 16:00:42,186 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(8, 3);~#mutexes~0.base, ~#mutexes~0.offset := 3, 0;call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, ~#mutexes~0.offset, 4);call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, 4 + ~#mutexes~0.offset, 4);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_foo } true;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset, foo_#t~ret36#1.base, foo_#t~ret36#1.offset, foo_~m1~0#1.base, foo_~m1~0#1.offset, foo_~m2~0#1.base, foo_~m2~0#1.offset;assume { :begin_inline_ldv_initialize } true;" "assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret35#1.base, foo_#t~ret35#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m1~0#1.base, foo_~m1~0#1.offset := foo_#t~ret35#1.base, foo_#t~ret35#1.offset;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret36#1.base, foo_#t~ret36#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m2~0#1.base, foo_~m2~0#1.offset := foo_#t~ret36#1.base, foo_#t~ret36#1.offset;havoc foo_#t~ret36#1.base, foo_#t~ret36#1.offset;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "ldv_set_add_#t~ret17#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume 0 == ldv_set_add_#t~ret17#1;havoc ldv_set_add_#t~ret17#1;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 12;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset := ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;havoc ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;call write~$Pointer$#1(ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, 4);assume { :begin_inline_ldv_list_add } true;ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset := ldv_set_add_~le~0#1.base, 4 + ldv_set_add_~le~0#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset := ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset;ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset := ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;call ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset := read~$Pointer$#1(ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, 4);assume { :begin_inline___ldv_list_add } true;__ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset := ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset := __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset;__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset := __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset;__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset := __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~next#1.base, 4 + __ldv_list_add_~next#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset, __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~new#1.base, 4 + __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, 4);" "havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;havoc __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;assume { :end_inline___ldv_list_add } true;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;" "havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;havoc ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;assume { :end_inline_ldv_list_add } true;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;" "havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :end_inline_ldv_set_add } true;" "havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;havoc mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :end_inline_mutex_lock } true;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" [2025-03-04 16:00:42,186 INFO L754 eck$LassoCheckResult]: Loop: "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" "assume !(ldv_is_in_set_#t~mem28#1.base == ldv_is_in_set_~e#1.base && ldv_is_in_set_#t~mem28#1.offset == ldv_is_in_set_~e#1.offset);havoc ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset;call ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, 4 + ldv_is_in_set_~m~1#1.offset, 4);ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset := ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;havoc ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset := ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset - 4;havoc ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;havoc ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;" [2025-03-04 16:00:42,187 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:42,187 INFO L85 PathProgramCache]: Analyzing trace with hash -1924964196, now seen corresponding path program 1 times [2025-03-04 16:00:42,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:42,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2114414119] [2025-03-04 16:00:42,187 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:42,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:42,218 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-04 16:00:42,302 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-04 16:00:42,303 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:42,303 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:42,303 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:42,314 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 23 statements into 1 equivalence classes. [2025-03-04 16:00:42,348 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 23 of 23 statements. [2025-03-04 16:00:42,348 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:42,348 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:42,356 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:42,358 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:42,358 INFO L85 PathProgramCache]: Analyzing trace with hash 4064, now seen corresponding path program 1 times [2025-03-04 16:00:42,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:42,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355559631] [2025-03-04 16:00:42,358 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:42,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:42,361 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:42,363 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:42,363 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:42,363 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:42,364 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:42,364 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:42,365 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:42,365 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:42,365 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:42,367 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:42,367 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:42,367 INFO L85 PathProgramCache]: Analyzing trace with hash 1240315323, now seen corresponding path program 1 times [2025-03-04 16:00:42,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:42,367 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1532087675] [2025-03-04 16:00:42,368 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:42,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:42,395 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 25 statements into 1 equivalence classes. [2025-03-04 16:00:42,423 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 25 of 25 statements. [2025-03-04 16:00:42,423 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:42,423 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:00:43,737 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:00:43,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:00:43,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1532087675] [2025-03-04 16:00:43,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1532087675] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:00:43,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:00:43,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-04 16:00:43,738 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1735242160] [2025-03-04 16:00:43,738 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:00:43,822 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:00:43,822 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2025-03-04 16:00:43,822 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2025-03-04 16:00:43,823 INFO L87 Difference]: Start difference. First operand 82 states and 98 transitions. cyclomatic complexity: 23 Second operand has 12 states, 11 states have (on average 2.272727272727273) internal successors, (25), 11 states have internal predecessors, (25), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:44,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:00:44,807 INFO L93 Difference]: Finished difference Result 107 states and 128 transitions. [2025-03-04 16:00:44,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107 states and 128 transitions. [2025-03-04 16:00:44,808 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 27 [2025-03-04 16:00:44,812 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107 states to 107 states and 128 transitions. [2025-03-04 16:00:44,813 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107 [2025-03-04 16:00:44,814 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107 [2025-03-04 16:00:44,815 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107 states and 128 transitions. [2025-03-04 16:00:44,815 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:00:44,815 INFO L218 hiAutomatonCegarLoop]: Abstraction has 107 states and 128 transitions. [2025-03-04 16:00:44,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states and 128 transitions. [2025-03-04 16:00:44,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 101. [2025-03-04 16:00:44,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 101 states, 101 states have (on average 1.198019801980198) internal successors, (121), 100 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:44,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 101 states to 101 states and 121 transitions. [2025-03-04 16:00:44,819 INFO L240 hiAutomatonCegarLoop]: Abstraction has 101 states and 121 transitions. [2025-03-04 16:00:44,819 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 16:00:44,820 INFO L432 stractBuchiCegarLoop]: Abstraction has 101 states and 121 transitions. [2025-03-04 16:00:44,820 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:00:44,820 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 101 states and 121 transitions. [2025-03-04 16:00:44,821 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 24 [2025-03-04 16:00:44,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:44,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:44,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:44,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 16:00:44,821 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(8, 3);~#mutexes~0.base, ~#mutexes~0.offset := 3, 0;call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, ~#mutexes~0.offset, 4);call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, 4 + ~#mutexes~0.offset, 4);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_foo } true;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset, foo_#t~ret36#1.base, foo_#t~ret36#1.offset, foo_~m1~0#1.base, foo_~m1~0#1.offset, foo_~m2~0#1.base, foo_~m2~0#1.offset;assume { :begin_inline_ldv_initialize } true;" "assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret35#1.base, foo_#t~ret35#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m1~0#1.base, foo_~m1~0#1.offset := foo_#t~ret35#1.base, foo_#t~ret35#1.offset;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret36#1.base, foo_#t~ret36#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m2~0#1.base, foo_~m2~0#1.offset := foo_#t~ret36#1.base, foo_#t~ret36#1.offset;havoc foo_#t~ret36#1.base, foo_#t~ret36#1.offset;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "ldv_set_add_#t~ret17#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume 0 == ldv_set_add_#t~ret17#1;havoc ldv_set_add_#t~ret17#1;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 12;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset := ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;havoc ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;call write~$Pointer$#1(ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, 4);assume { :begin_inline_ldv_list_add } true;ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset := ldv_set_add_~le~0#1.base, 4 + ldv_set_add_~le~0#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset := ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset;ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset := ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;call ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset := read~$Pointer$#1(ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, 4);assume { :begin_inline___ldv_list_add } true;__ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset := ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset := __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset;__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset := __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset;__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset := __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~next#1.base, 4 + __ldv_list_add_~next#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset, __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~new#1.base, 4 + __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, 4);" "havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;havoc __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;assume { :end_inline___ldv_list_add } true;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;" "havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;havoc ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;assume { :end_inline_ldv_list_add } true;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;" "havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :end_inline_ldv_set_add } true;" "havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;havoc mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :end_inline_mutex_lock } true;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" [2025-03-04 16:00:44,822 INFO L754 eck$LassoCheckResult]: Loop: "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" "assume !(ldv_is_in_set_#t~mem28#1.base == ldv_is_in_set_~e#1.base && ldv_is_in_set_#t~mem28#1.offset == ldv_is_in_set_~e#1.offset);havoc ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset;call ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, 4 + ldv_is_in_set_~m~1#1.offset, 4);ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset := ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;havoc ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset := ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset - 4;havoc ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;havoc ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;" [2025-03-04 16:00:44,822 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:44,822 INFO L85 PathProgramCache]: Analyzing trace with hash -2058065547, now seen corresponding path program 1 times [2025-03-04 16:00:44,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:44,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [653835882] [2025-03-04 16:00:44,822 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:44,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:44,839 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 27 statements into 1 equivalence classes. [2025-03-04 16:00:44,846 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 27 of 27 statements. [2025-03-04 16:00:44,847 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:44,847 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:00:45,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:00:45,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:00:45,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [653835882] [2025-03-04 16:00:45,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [653835882] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:00:45,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:00:45,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:00:45,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [184320498] [2025-03-04 16:00:45,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:00:45,089 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:00:45,090 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:45,090 INFO L85 PathProgramCache]: Analyzing trace with hash 3584, now seen corresponding path program 1 times [2025-03-04 16:00:45,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:45,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315502822] [2025-03-04 16:00:45,090 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:45,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:45,092 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:45,093 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:45,093 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:45,093 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:45,094 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:45,095 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:45,096 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:45,096 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:45,096 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:45,097 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:45,176 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:00:45,176 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:00:45,177 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:00:45,177 INFO L87 Difference]: Start difference. First operand 101 states and 121 transitions. cyclomatic complexity: 28 Second operand has 9 states, 9 states have (on average 3.0) internal successors, (27), 9 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:45,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:00:45,880 INFO L93 Difference]: Finished difference Result 139 states and 167 transitions. [2025-03-04 16:00:45,880 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 139 states and 167 transitions. [2025-03-04 16:00:45,881 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 35 [2025-03-04 16:00:45,882 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 139 states to 139 states and 167 transitions. [2025-03-04 16:00:45,882 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 139 [2025-03-04 16:00:45,882 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 139 [2025-03-04 16:00:45,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 139 states and 167 transitions. [2025-03-04 16:00:45,882 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:00:45,882 INFO L218 hiAutomatonCegarLoop]: Abstraction has 139 states and 167 transitions. [2025-03-04 16:00:45,883 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states and 167 transitions. [2025-03-04 16:00:45,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 110. [2025-03-04 16:00:45,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 110 states, 110 states have (on average 1.1818181818181819) internal successors, (130), 109 states have internal predecessors, (130), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:45,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 110 states to 110 states and 130 transitions. [2025-03-04 16:00:45,887 INFO L240 hiAutomatonCegarLoop]: Abstraction has 110 states and 130 transitions. [2025-03-04 16:00:45,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2025-03-04 16:00:45,890 INFO L432 stractBuchiCegarLoop]: Abstraction has 110 states and 130 transitions. [2025-03-04 16:00:45,890 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:00:45,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 110 states and 130 transitions. [2025-03-04 16:00:45,890 INFO L131 ngComponentsAnalysis]: Automaton has 9 accepting balls. 27 [2025-03-04 16:00:45,890 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:45,891 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:45,891 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:45,891 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1] [2025-03-04 16:00:45,891 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(8, 3);~#mutexes~0.base, ~#mutexes~0.offset := 3, 0;call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, ~#mutexes~0.offset, 4);call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, 4 + ~#mutexes~0.offset, 4);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_foo } true;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset, foo_#t~ret36#1.base, foo_#t~ret36#1.offset, foo_~m1~0#1.base, foo_~m1~0#1.offset, foo_~m2~0#1.base, foo_~m2~0#1.offset;assume { :begin_inline_ldv_initialize } true;" "assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret35#1.base, foo_#t~ret35#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m1~0#1.base, foo_~m1~0#1.offset := foo_#t~ret35#1.base, foo_#t~ret35#1.offset;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret36#1.base, foo_#t~ret36#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m2~0#1.base, foo_~m2~0#1.offset := foo_#t~ret36#1.base, foo_#t~ret36#1.offset;havoc foo_#t~ret36#1.base, foo_#t~ret36#1.offset;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "ldv_set_add_#t~ret17#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume 0 == ldv_set_add_#t~ret17#1;havoc ldv_set_add_#t~ret17#1;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 12;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset := ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;havoc ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset;call write~$Pointer$#1(ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, 4);assume { :begin_inline_ldv_list_add } true;ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset := ldv_set_add_~le~0#1.base, 4 + ldv_set_add_~le~0#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset := ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset;ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset := ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;call ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset := read~$Pointer$#1(ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, 4);assume { :begin_inline___ldv_list_add } true;__ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset := ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset, ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset := __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset;__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset := __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset;__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset := __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~next#1.base, 4 + __ldv_list_add_~next#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset, __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~new#1.base, 4 + __ldv_list_add_~new#1.offset, 4);call write~$Pointer$#1(__ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, 4);" "havoc __ldv_list_add_~new#1.base, __ldv_list_add_~new#1.offset, __ldv_list_add_~prev#1.base, __ldv_list_add_~prev#1.offset, __ldv_list_add_~next#1.base, __ldv_list_add_~next#1.offset;havoc __ldv_list_add_#in~new#1.base, __ldv_list_add_#in~new#1.offset, __ldv_list_add_#in~prev#1.base, __ldv_list_add_#in~prev#1.offset, __ldv_list_add_#in~next#1.base, __ldv_list_add_#in~next#1.offset;assume { :end_inline___ldv_list_add } true;havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset;" "havoc ldv_list_add_#t~mem6#1.base, ldv_list_add_#t~mem6#1.offset, ldv_list_add_~new#1.base, ldv_list_add_~new#1.offset, ldv_list_add_~head#1.base, ldv_list_add_~head#1.offset;havoc ldv_list_add_#in~new#1.base, ldv_list_add_#in~new#1.offset, ldv_list_add_#in~head#1.base, ldv_list_add_#in~head#1.offset;assume { :end_inline_ldv_list_add } true;havoc ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset;" "havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :end_inline_ldv_set_add } true;" "havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;havoc mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :end_inline_mutex_lock } true;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" "assume ldv_is_in_set_#t~mem28#1.base == ldv_is_in_set_~e#1.base && ldv_is_in_set_#t~mem28#1.offset == ldv_is_in_set_~e#1.offset;havoc ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset;ldv_is_in_set_#res#1 := 1;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" [2025-03-04 16:00:45,892 INFO L754 eck$LassoCheckResult]: Loop: "assume !(ldv_is_in_set_#t~mem28#1.base == ldv_is_in_set_~e#1.base && ldv_is_in_set_#t~mem28#1.offset == ldv_is_in_set_~e#1.offset);havoc ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset;call ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, 4 + ldv_is_in_set_~m~1#1.offset, 4);ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset := ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;havoc ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset;ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset := ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset - 4;havoc ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;havoc ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset;" "assume ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset;call ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset := read~$Pointer$#1(ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset, 4);" [2025-03-04 16:00:45,892 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:45,893 INFO L85 PathProgramCache]: Analyzing trace with hash -1939604745, now seen corresponding path program 1 times [2025-03-04 16:00:45,893 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:45,893 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [220687660] [2025-03-04 16:00:45,893 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:45,894 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:45,912 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 29 statements into 1 equivalence classes. [2025-03-04 16:00:45,919 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 29 of 29 statements. [2025-03-04 16:00:45,919 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:45,919 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:00:45,955 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:00:45,956 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:00:45,956 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [220687660] [2025-03-04 16:00:45,956 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [220687660] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:00:45,956 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:00:45,956 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:00:45,956 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [815945763] [2025-03-04 16:00:45,956 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:00:45,957 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:00:45,957 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:45,957 INFO L85 PathProgramCache]: Analyzing trace with hash 3554, now seen corresponding path program 2 times [2025-03-04 16:00:45,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:45,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1591363329] [2025-03-04 16:00:45,958 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:00:45,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:45,962 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:45,964 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:45,965 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:00:45,965 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:45,965 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:45,966 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:00:45,966 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:00:45,967 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:45,967 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:45,968 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:46,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:00:46,060 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:00:46,060 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:00:46,061 INFO L87 Difference]: Start difference. First operand 110 states and 130 transitions. cyclomatic complexity: 29 Second operand has 4 states, 4 states have (on average 7.25) internal successors, (29), 4 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:46,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:00:46,092 INFO L93 Difference]: Finished difference Result 87 states and 99 transitions. [2025-03-04 16:00:46,092 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 87 states and 99 transitions. [2025-03-04 16:00:46,093 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20 [2025-03-04 16:00:46,093 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 87 states to 76 states and 88 transitions. [2025-03-04 16:00:46,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76 [2025-03-04 16:00:46,093 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76 [2025-03-04 16:00:46,093 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76 states and 88 transitions. [2025-03-04 16:00:46,093 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:00:46,093 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76 states and 88 transitions. [2025-03-04 16:00:46,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states and 88 transitions. [2025-03-04 16:00:46,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 74. [2025-03-04 16:00:46,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74 states, 74 states have (on average 1.162162162162162) internal successors, (86), 73 states have internal predecessors, (86), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:46,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 86 transitions. [2025-03-04 16:00:46,096 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74 states and 86 transitions. [2025-03-04 16:00:46,098 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:00:46,098 INFO L432 stractBuchiCegarLoop]: Abstraction has 74 states and 86 transitions. [2025-03-04 16:00:46,098 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:00:46,098 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74 states and 86 transitions. [2025-03-04 16:00:46,099 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 20 [2025-03-04 16:00:46,099 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:00:46,099 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:00:46,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:00:46,099 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1] [2025-03-04 16:00:46,100 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(12, 2);call #Ultimate.allocInit(8, 3);~#mutexes~0.base, ~#mutexes~0.offset := 3, 0;call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, ~#mutexes~0.offset, 4);call write~init~$Pointer$#1(~#mutexes~0.base, ~#mutexes~0.offset, ~#mutexes~0.base, 4 + ~#mutexes~0.offset, 4);" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;assume { :begin_inline_foo } true;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset, foo_#t~ret36#1.base, foo_#t~ret36#1.offset, foo_~m1~0#1.base, foo_~m1~0#1.offset, foo_~m2~0#1.base, foo_~m2~0#1.offset;assume { :begin_inline_ldv_initialize } true;" "assume { :end_inline_ldv_initialize } true;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret35#1.base, foo_#t~ret35#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m1~0#1.base, foo_~m1~0#1.offset := foo_#t~ret35#1.base, foo_#t~ret35#1.offset;havoc foo_#t~ret35#1.base, foo_#t~ret35#1.offset;assume { :begin_inline_ldv_successful_malloc } true;ldv_successful_malloc_#in~size#1 := 8;havoc ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;ldv_successful_malloc_~size#1 := ldv_successful_malloc_#in~size#1;call ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset := #Ultimate.allocOnHeap(ldv_successful_malloc_~size#1 % 4294967296);ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset := ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset;assume { :begin_inline_assume_abort_if_not } true;assume_abort_if_not_#in~cond#1 := (if ldv_successful_malloc_~ptr~0#1.base != 0 || ldv_successful_malloc_~ptr~0#1.offset != 0 then 1 else 0);havoc assume_abort_if_not_~cond#1;assume_abort_if_not_~cond#1 := assume_abort_if_not_#in~cond#1;" "assume !(0 == assume_abort_if_not_~cond#1);" "havoc assume_abort_if_not_~cond#1;havoc assume_abort_if_not_#in~cond#1;assume { :end_inline_assume_abort_if_not } true;ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset := ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;" "foo_#t~ret36#1.base, foo_#t~ret36#1.offset := ldv_successful_malloc_#res#1.base, ldv_successful_malloc_#res#1.offset;havoc ldv_successful_malloc_#t~malloc5#1.base, ldv_successful_malloc_#t~malloc5#1.offset, ldv_successful_malloc_~size#1, ldv_successful_malloc_~ptr~0#1.base, ldv_successful_malloc_~ptr~0#1.offset;havoc ldv_successful_malloc_#in~size#1;assume { :end_inline_ldv_successful_malloc } true;foo_~m2~0#1.base, foo_~m2~0#1.offset := foo_#t~ret36#1.base, foo_#t~ret36#1.offset;havoc foo_#t~ret36#1.base, foo_#t~ret36#1.offset;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "ldv_set_add_#t~ret17#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 == ldv_set_add_#t~ret17#1);havoc ldv_set_add_#t~ret17#1;" "havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :end_inline_ldv_set_add } true;" "havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;havoc mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :end_inline_mutex_lock } true;assume { :begin_inline_mutex_lock } true;mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset := foo_~m1~0#1.base, foo_~m1~0#1.offset;havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;mutex_lock_~m#1.base, mutex_lock_~m#1.offset := mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_lock_#t~ret32#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 != mutex_lock_#t~ret32#1);havoc mutex_lock_#t~ret32#1;" "assume { :begin_inline_ldv_set_add } true;ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset := mutex_lock_~m#1.base, mutex_lock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset := ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset;ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset := ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "ldv_set_add_#t~ret17#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 == ldv_set_add_#t~ret17#1);havoc ldv_set_add_#t~ret17#1;" "havoc ldv_set_add_#t~ret17#1, ldv_set_add_#t~ret18#1.base, ldv_set_add_#t~ret18#1.offset, ldv_set_add_~le~0#1.base, ldv_set_add_~le~0#1.offset, ldv_set_add_~new#1.base, ldv_set_add_~new#1.offset, ldv_set_add_~s#1.base, ldv_set_add_~s#1.offset;havoc ldv_set_add_#in~new#1.base, ldv_set_add_#in~new#1.offset, ldv_set_add_#in~s#1.base, ldv_set_add_#in~s#1.offset;assume { :end_inline_ldv_set_add } true;" "havoc mutex_lock_#t~ret32#1, mutex_lock_~m#1.base, mutex_lock_~m#1.offset;havoc mutex_lock_#in~m#1.base, mutex_lock_#in~m#1.offset;assume { :end_inline_mutex_lock } true;assume { :begin_inline_mutex_unlock } true;mutex_unlock_#in~m#1.base, mutex_unlock_#in~m#1.offset := foo_~m2~0#1.base, foo_~m2~0#1.offset;havoc mutex_unlock_#t~ret33#1, mutex_unlock_~m#1.base, mutex_unlock_~m#1.offset;mutex_unlock_~m#1.base, mutex_unlock_~m#1.offset := mutex_unlock_#in~m#1.base, mutex_unlock_#in~m#1.offset;assume { :begin_inline_ldv_is_in_set } true;ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset := mutex_unlock_~m#1.base, mutex_unlock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset := ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset;ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset := ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;havoc ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;call ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset := read~$Pointer$#1(ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, 4);ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset := ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset;ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset := ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset - 4;havoc ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset;ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset := ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;havoc ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset;" "assume !(ldv_is_in_set_~m~1#1.base != ldv_is_in_set_~s#1.base || 4 + ldv_is_in_set_~m~1#1.offset != ldv_is_in_set_~s#1.offset);ldv_is_in_set_#res#1 := 0;" "mutex_unlock_#t~ret33#1 := ldv_is_in_set_#res#1;havoc ldv_is_in_set_#t~mem26#1.base, ldv_is_in_set_#t~mem26#1.offset, ldv_is_in_set_#t~ret27#1.base, ldv_is_in_set_#t~ret27#1.offset, ldv_is_in_set_~__mptr~3#1.base, ldv_is_in_set_~__mptr~3#1.offset, ldv_is_in_set_#t~mem28#1.base, ldv_is_in_set_#t~mem28#1.offset, ldv_is_in_set_#t~mem29#1.base, ldv_is_in_set_#t~mem29#1.offset, ldv_is_in_set_#t~ret30#1.base, ldv_is_in_set_#t~ret30#1.offset, ldv_is_in_set_~__mptr~4#1.base, ldv_is_in_set_~__mptr~4#1.offset, ldv_is_in_set_~e#1.base, ldv_is_in_set_~e#1.offset, ldv_is_in_set_~s#1.base, ldv_is_in_set_~s#1.offset, ldv_is_in_set_~m~1#1.base, ldv_is_in_set_~m~1#1.offset;havoc ldv_is_in_set_#in~e#1.base, ldv_is_in_set_#in~e#1.offset, ldv_is_in_set_#in~s#1.base, ldv_is_in_set_#in~s#1.offset;assume { :end_inline_ldv_is_in_set } true;" "assume !(0 == mutex_unlock_#t~ret33#1);havoc mutex_unlock_#t~ret33#1;" "assume { :begin_inline_ldv_set_del } true;ldv_set_del_#in~e#1.base, ldv_set_del_#in~e#1.offset, ldv_set_del_#in~s#1.base, ldv_set_del_#in~s#1.offset := mutex_unlock_~m#1.base, mutex_unlock_~m#1.offset, ~#mutexes~0.base, ~#mutexes~0.offset;havoc ldv_set_del_#t~mem19#1.base, ldv_set_del_#t~mem19#1.offset, ldv_set_del_#t~ret20#1.base, ldv_set_del_#t~ret20#1.offset, ldv_set_del_~__mptr~0#1.base, ldv_set_del_~__mptr~0#1.offset, ldv_set_del_#t~mem21#1.base, ldv_set_del_#t~mem21#1.offset, ldv_set_del_#t~ret22#1.base, ldv_set_del_#t~ret22#1.offset, ldv_set_del_~__mptr~1#1.base, ldv_set_del_~__mptr~1#1.offset, ldv_set_del_#t~mem23#1.base, ldv_set_del_#t~mem23#1.offset, ldv_set_del_#t~mem24#1.base, ldv_set_del_#t~mem24#1.offset, ldv_set_del_#t~ret25#1.base, ldv_set_del_#t~ret25#1.offset, ldv_set_del_~__mptr~2#1.base, ldv_set_del_~__mptr~2#1.offset, ldv_set_del_~e#1.base, ldv_set_del_~e#1.offset, ldv_set_del_~s#1.base, ldv_set_del_~s#1.offset, ldv_set_del_~m~0#1.base, ldv_set_del_~m~0#1.offset, ldv_set_del_~n~0#1.base, ldv_set_del_~n~0#1.offset;ldv_set_del_~e#1.base, ldv_set_del_~e#1.offset := ldv_set_del_#in~e#1.base, ldv_set_del_#in~e#1.offset;ldv_set_del_~s#1.base, ldv_set_del_~s#1.offset := ldv_set_del_#in~s#1.base, ldv_set_del_#in~s#1.offset;havoc ldv_set_del_~m~0#1.base, ldv_set_del_~m~0#1.offset;havoc ldv_set_del_~n~0#1.base, ldv_set_del_~n~0#1.offset;call ldv_set_del_#t~mem19#1.base, ldv_set_del_#t~mem19#1.offset := read~$Pointer$#1(ldv_set_del_~s#1.base, ldv_set_del_~s#1.offset, 4);ldv_set_del_~__mptr~0#1.base, ldv_set_del_~__mptr~0#1.offset := ldv_set_del_#t~mem19#1.base, ldv_set_del_#t~mem19#1.offset;havoc ldv_set_del_#t~mem19#1.base, ldv_set_del_#t~mem19#1.offset;ldv_set_del_#t~ret20#1.base, ldv_set_del_#t~ret20#1.offset := ldv_set_del_~__mptr~0#1.base, ldv_set_del_~__mptr~0#1.offset - 4;havoc ldv_set_del_~__mptr~0#1.base, ldv_set_del_~__mptr~0#1.offset;ldv_set_del_~m~0#1.base, ldv_set_del_~m~0#1.offset := ldv_set_del_#t~ret20#1.base, ldv_set_del_#t~ret20#1.offset;call ldv_set_del_#t~mem21#1.base, ldv_set_del_#t~mem21#1.offset := read~$Pointer$#1(ldv_set_del_~m~0#1.base, 4 + ldv_set_del_~m~0#1.offset, 4);ldv_set_del_~__mptr~1#1.base, ldv_set_del_~__mptr~1#1.offset := ldv_set_del_#t~mem21#1.base, ldv_set_del_#t~mem21#1.offset;havoc ldv_set_del_#t~mem21#1.base, ldv_set_del_#t~mem21#1.offset;ldv_set_del_#t~ret22#1.base, ldv_set_del_#t~ret22#1.offset := ldv_set_del_~__mptr~1#1.base, ldv_set_del_~__mptr~1#1.offset - 4;havoc ldv_set_del_~__mptr~1#1.base, ldv_set_del_~__mptr~1#1.offset;ldv_set_del_~n~0#1.base, ldv_set_del_~n~0#1.offset := ldv_set_del_#t~ret22#1.base, ldv_set_del_#t~ret22#1.offset;havoc ldv_set_del_#t~ret20#1.base, ldv_set_del_#t~ret20#1.offset;havoc ldv_set_del_#t~ret22#1.base, ldv_set_del_#t~ret22#1.offset;" [2025-03-04 16:00:46,103 INFO L754 eck$LassoCheckResult]: Loop: "assume ldv_set_del_~m~0#1.base != ldv_set_del_~s#1.base || 4 + ldv_set_del_~m~0#1.offset != ldv_set_del_~s#1.offset;call ldv_set_del_#t~mem23#1.base, ldv_set_del_#t~mem23#1.offset := read~$Pointer$#1(ldv_set_del_~m~0#1.base, ldv_set_del_~m~0#1.offset, 4);" "assume !(ldv_set_del_#t~mem23#1.base == ldv_set_del_~e#1.base && ldv_set_del_#t~mem23#1.offset == ldv_set_del_~e#1.offset);havoc ldv_set_del_#t~mem23#1.base, ldv_set_del_#t~mem23#1.offset;" "ldv_set_del_~m~0#1.base, ldv_set_del_~m~0#1.offset := ldv_set_del_~n~0#1.base, ldv_set_del_~n~0#1.offset;call ldv_set_del_#t~mem24#1.base, ldv_set_del_#t~mem24#1.offset := read~$Pointer$#1(ldv_set_del_~n~0#1.base, 4 + ldv_set_del_~n~0#1.offset, 4);ldv_set_del_~__mptr~2#1.base, ldv_set_del_~__mptr~2#1.offset := ldv_set_del_#t~mem24#1.base, ldv_set_del_#t~mem24#1.offset;havoc ldv_set_del_#t~mem24#1.base, ldv_set_del_#t~mem24#1.offset;ldv_set_del_#t~ret25#1.base, ldv_set_del_#t~ret25#1.offset := ldv_set_del_~__mptr~2#1.base, ldv_set_del_~__mptr~2#1.offset - 4;havoc ldv_set_del_~__mptr~2#1.base, ldv_set_del_~__mptr~2#1.offset;ldv_set_del_~n~0#1.base, ldv_set_del_~n~0#1.offset := ldv_set_del_#t~ret25#1.base, ldv_set_del_#t~ret25#1.offset;havoc ldv_set_del_#t~ret25#1.base, ldv_set_del_#t~ret25#1.offset;" [2025-03-04 16:00:46,104 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:46,104 INFO L85 PathProgramCache]: Analyzing trace with hash -1286188928, now seen corresponding path program 1 times [2025-03-04 16:00:46,104 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:46,104 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1467439385] [2025-03-04 16:00:46,104 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:46,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:46,116 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 31 statements into 1 equivalence classes. [2025-03-04 16:00:46,120 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 31 of 31 statements. [2025-03-04 16:00:46,120 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:46,120 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:00:46,143 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:00:46,143 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:00:46,143 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1467439385] [2025-03-04 16:00:46,144 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1467439385] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:00:46,144 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:00:46,144 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:00:46,144 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [728669154] [2025-03-04 16:00:46,144 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:00:46,144 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:00:46,144 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:00:46,144 INFO L85 PathProgramCache]: Analyzing trace with hash 75433, now seen corresponding path program 1 times [2025-03-04 16:00:46,144 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:00:46,144 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [904497968] [2025-03-04 16:00:46,145 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:00:46,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:00:46,148 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 16:00:46,149 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 16:00:46,149 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:46,149 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:46,149 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:00:46,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 3 statements into 1 equivalence classes. [2025-03-04 16:00:46,150 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 3 of 3 statements. [2025-03-04 16:00:46,150 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:00:46,150 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:00:46,153 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:00:46,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:00:46,238 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:00:46,238 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:00:46,238 INFO L87 Difference]: Start difference. First operand 74 states and 86 transitions. cyclomatic complexity: 18 Second operand has 4 states, 4 states have (on average 7.75) internal successors, (31), 4 states have internal predecessors, (31), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:00:46,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:00:46,245 INFO L93 Difference]: Finished difference Result 16 states and 15 transitions. [2025-03-04 16:00:46,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16 states and 15 transitions. [2025-03-04 16:00:46,246 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-04 16:00:46,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16 states to 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 0 [2025-03-04 16:00:46,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 0 [2025-03-04 16:00:46,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:00:46,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L240 hiAutomatonCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:00:46,247 INFO L432 stractBuchiCegarLoop]: Abstraction has 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:00:46,247 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 0 states and 0 transitions. [2025-03-04 16:00:46,247 INFO L131 ngComponentsAnalysis]: Automaton has 0 accepting balls. 0 [2025-03-04 16:00:46,248 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is true [2025-03-04 16:00:46,253 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 04.03 04:00:46 BoogieIcfgContainer [2025-03-04 16:00:46,253 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2025-03-04 16:00:46,254 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2025-03-04 16:00:46,254 INFO L270 PluginConnector]: Initializing Witness Printer... [2025-03-04 16:00:46,254 INFO L274 PluginConnector]: Witness Printer initialized [2025-03-04 16:00:46,254 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:00:41" (3/4) ... [2025-03-04 16:00:46,256 INFO L149 WitnessPrinter]: No result that supports witness generation found [2025-03-04 16:00:46,256 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2025-03-04 16:00:46,257 INFO L158 Benchmark]: Toolchain (without parser) took 6125.27ms. Allocated memory was 142.6MB in the beginning and 192.9MB in the end (delta: 50.3MB). Free memory was 110.5MB in the beginning and 64.6MB in the end (delta: 45.9MB). Peak memory consumption was 94.7MB. Max. memory is 16.1GB. [2025-03-04 16:00:46,257 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 124.3MB. There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:00:46,257 INFO L158 Benchmark]: CACSL2BoogieTranslator took 364.21ms. Allocated memory is still 142.6MB. Free memory was 110.5MB in the beginning and 91.3MB in the end (delta: 19.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2025-03-04 16:00:46,257 INFO L158 Benchmark]: Boogie Procedure Inliner took 45.50ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 88.3MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:00:46,258 INFO L158 Benchmark]: Boogie Preprocessor took 63.51ms. Allocated memory is still 142.6MB. Free memory was 88.3MB in the beginning and 81.5MB in the end (delta: 6.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. [2025-03-04 16:00:46,258 INFO L158 Benchmark]: IcfgBuilder took 637.21ms. Allocated memory is still 142.6MB. Free memory was 81.5MB in the beginning and 106.6MB in the end (delta: -25.0MB). Peak memory consumption was 49.2MB. Max. memory is 16.1GB. [2025-03-04 16:00:46,258 INFO L158 Benchmark]: BuchiAutomizer took 5008.51ms. Allocated memory was 142.6MB in the beginning and 192.9MB in the end (delta: 50.3MB). Free memory was 106.6MB in the beginning and 64.6MB in the end (delta: 42.0MB). Peak memory consumption was 87.4MB. Max. memory is 16.1GB. [2025-03-04 16:00:46,258 INFO L158 Benchmark]: Witness Printer took 2.69ms. Allocated memory is still 192.9MB. Free memory was 64.6MB in the beginning and 64.6MB in the end (delta: 23.5kB). There was no memory consumed. Max. memory is 16.1GB. [2025-03-04 16:00:46,259 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 201.3MB. Free memory is still 124.3MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 364.21ms. Allocated memory is still 142.6MB. Free memory was 110.5MB in the beginning and 91.3MB in the end (delta: 19.2MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 45.50ms. Allocated memory is still 142.6MB. Free memory was 91.3MB in the beginning and 88.3MB in the end (delta: 3.0MB). There was no memory consumed. Max. memory is 16.1GB. * Boogie Preprocessor took 63.51ms. Allocated memory is still 142.6MB. Free memory was 88.3MB in the beginning and 81.5MB in the end (delta: 6.7MB). Peak memory consumption was 8.4MB. Max. memory is 16.1GB. * IcfgBuilder took 637.21ms. Allocated memory is still 142.6MB. Free memory was 81.5MB in the beginning and 106.6MB in the end (delta: -25.0MB). Peak memory consumption was 49.2MB. Max. memory is 16.1GB. * BuchiAutomizer took 5008.51ms. Allocated memory was 142.6MB in the beginning and 192.9MB in the end (delta: 50.3MB). Free memory was 106.6MB in the beginning and 64.6MB in the end (delta: 42.0MB). Peak memory consumption was 87.4MB. Max. memory is 16.1GB. * Witness Printer took 2.69ms. Allocated memory is still 192.9MB. Free memory was 64.6MB in the beginning and 64.6MB in the end (delta: 23.5kB). There was no memory consumed. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 5 terminating modules (5 trivial, 0 deterministic, 0 nondeterministic). 5 modules have a trivial ranking function, the largest among these consists of 12 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.9s and 6 iterations. TraceHistogramMax:1. Analysis of lassos took 2.8s. Construction of modules took 1.4s. Büchi inclusion checks took 0.6s. Highest rank in rank-based complementation 0. Minimization of det autom 5. Minimization of nondet autom 0. Automata minimization 0.0s AutomataMinimizationTime, 4 MinimizatonAttempts, 46 StatesRemovedByMinimization, 4 NontrivialMinimizations. Non-live state removal took 0.0s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 283 SdHoareTripleChecker+Valid, 1.6s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 283 mSDsluCounter, 1095 SdHoareTripleChecker+Invalid, 1.4s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 835 mSDsCounter, 50 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 984 IncrementalHoareTripleChecker+Invalid, 1034 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 50 mSolverCounterUnsat, 260 mSDtfsCounter, 984 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont0 unkn0 SFLI0 SFLT0 conc2 concLT0 SILN0 SILU3 SILI0 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Termination proven Buchi Automizer proved that your program is terminating RESULT: Ultimate proved your program to be correct! [2025-03-04 16:00:46,272 INFO L552 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Result: TRUE