./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/systemc/transmitter.12.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/systemc/transmitter.12.cil.c -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:21:55,166 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:21:55,203 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:21:55,206 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:21:55,206 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:21:55,207 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:21:55,225 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:21:55,226 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:21:55,226 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:21:55,226 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:21:55,226 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:21:55,227 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:21:55,227 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:21:55,227 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:21:55,227 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:21:55,228 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:21:55,228 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:21:55,228 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:21:55,228 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 062c7418109a213aa13d25a99437d8241cca4f6492c123259890838dc94aff90 [2025-03-04 16:21:55,418 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:21:55,425 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:21:55,426 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:21:55,430 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:21:55,430 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:21:55,431 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/systemc/transmitter.12.cil.c [2025-03-04 16:21:56,571 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cbf67eb17/884bf184692642a793e7061e98050118/FLAG999023489 [2025-03-04 16:21:56,865 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:21:56,868 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/systemc/transmitter.12.cil.c [2025-03-04 16:21:56,883 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cbf67eb17/884bf184692642a793e7061e98050118/FLAG999023489 [2025-03-04 16:21:57,143 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cbf67eb17/884bf184692642a793e7061e98050118 [2025-03-04 16:21:57,145 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:21:57,146 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:21:57,146 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:21:57,146 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:21:57,149 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:21:57,149 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,150 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d5ee1f0 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57, skipping insertion in model container [2025-03-04 16:21:57,150 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,173 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:21:57,326 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:21:57,345 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:21:57,406 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:21:57,422 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:21:57,422 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57 WrapperNode [2025-03-04 16:21:57,423 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:21:57,423 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:21:57,424 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:21:57,424 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:21:57,428 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,438 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,505 INFO L138 Inliner]: procedures = 52, calls = 67, calls flagged for inlining = 62, calls inlined = 255, statements flattened = 3888 [2025-03-04 16:21:57,506 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:21:57,506 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:21:57,506 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:21:57,507 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:21:57,513 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,513 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,524 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,563 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2025-03-04 16:21:57,563 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,563 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,589 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,593 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,597 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,607 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,620 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:21:57,621 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:21:57,622 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:21:57,622 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:21:57,623 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (1/1) ... [2025-03-04 16:21:57,627 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:21:57,637 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:21:57,649 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:21:57,652 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:21:57,670 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:21:57,671 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:21:57,671 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:21:57,671 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:21:57,767 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:21:57,768 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:21:59,895 INFO L? ?]: Removed 830 outVars from TransFormulas that were not future-live. [2025-03-04 16:21:59,895 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:21:59,941 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:21:59,946 INFO L336 CfgBuilder]: Removed 0 assume(true) statements. [2025-03-04 16:21:59,946 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:21:59 BoogieIcfgContainer [2025-03-04 16:21:59,946 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:21:59,947 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:21:59,947 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:21:59,951 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:21:59,952 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:59,952 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:21:57" (1/3) ... [2025-03-04 16:21:59,953 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45f6e4a2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:21:59, skipping insertion in model container [2025-03-04 16:21:59,953 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:59,953 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:21:57" (2/3) ... [2025-03-04 16:21:59,954 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@45f6e4a2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:21:59, skipping insertion in model container [2025-03-04 16:21:59,954 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:21:59,954 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:21:59" (3/3) ... [2025-03-04 16:21:59,955 INFO L363 chiAutomizerObserver]: Analyzing ICFG transmitter.12.cil.c [2025-03-04 16:22:00,022 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:22:00,022 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:22:00,023 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:22:00,023 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:22:00,023 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:22:00,023 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:22:00,023 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:22:00,023 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:22:00,035 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1724 states, 1723 states have (on average 1.4840394660475915) internal successors, (2557), 1723 states have internal predecessors, (2557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:00,078 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1559 [2025-03-04 16:22:00,079 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:00,079 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:00,090 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,090 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,090 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:22:00,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1724 states, 1723 states have (on average 1.4840394660475915) internal successors, (2557), 1723 states have internal predecessors, (2557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:00,107 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1559 [2025-03-04 16:22:00,107 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:00,107 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:00,110 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,110 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,116 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:00,121 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume !true;" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:00,129 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:00,130 INFO L85 PathProgramCache]: Analyzing trace with hash 1348950054, now seen corresponding path program 1 times [2025-03-04 16:22:00,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:00,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [350649088] [2025-03-04 16:22:00,135 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:00,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:00,208 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:00,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:00,235 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:00,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:00,394 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:00,395 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:00,395 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [350649088] [2025-03-04 16:22:00,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [350649088] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:00,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:00,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:00,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634156919] [2025-03-04 16:22:00,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:00,400 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:00,401 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:00,401 INFO L85 PathProgramCache]: Analyzing trace with hash -1652520978, now seen corresponding path program 1 times [2025-03-04 16:22:00,401 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:00,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226286336] [2025-03-04 16:22:00,402 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:00,402 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:00,419 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 147 statements into 1 equivalence classes. [2025-03-04 16:22:00,420 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 147 of 147 statements. [2025-03-04 16:22:00,421 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:00,421 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:00,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:00,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:00,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226286336] [2025-03-04 16:22:00,471 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226286336] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:00,471 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:00,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:00,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [365968950] [2025-03-04 16:22:00,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:00,472 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:00,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:00,497 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 16:22:00,497 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 16:22:00,501 INFO L87 Difference]: Start difference. First operand has 1724 states, 1723 states have (on average 1.4840394660475915) internal successors, (2557), 1723 states have internal predecessors, (2557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 73.5) internal successors, (147), 2 states have internal predecessors, (147), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:00,555 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:00,555 INFO L93 Difference]: Finished difference Result 1721 states and 2537 transitions. [2025-03-04 16:22:00,556 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1721 states and 2537 transitions. [2025-03-04 16:22:00,565 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:00,581 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1721 states to 1715 states and 2531 transitions. [2025-03-04 16:22:00,582 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:00,584 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:00,585 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2531 transitions. [2025-03-04 16:22:00,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:00,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2531 transitions. [2025-03-04 16:22:00,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2531 transitions. [2025-03-04 16:22:00,651 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:00,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.475801749271137) internal successors, (2531), 1714 states have internal predecessors, (2531), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:00,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2531 transitions. [2025-03-04 16:22:00,660 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2531 transitions. [2025-03-04 16:22:00,661 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 16:22:00,664 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2531 transitions. [2025-03-04 16:22:00,664 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:22:00,664 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2531 transitions. [2025-03-04 16:22:00,671 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:00,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:00,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:00,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,675 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:00,676 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume !(1 == ~m_i~0);~m_st~0 := 2;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:00,676 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:00,677 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:00,677 INFO L85 PathProgramCache]: Analyzing trace with hash 1348950054, now seen corresponding path program 2 times [2025-03-04 16:22:00,678 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:00,678 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1680420812] [2025-03-04 16:22:00,678 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:22:00,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:00,710 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:00,721 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:00,721 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:22:00,722 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:00,792 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:00,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:00,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1680420812] [2025-03-04 16:22:00,793 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1680420812] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:00,793 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:00,793 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:00,793 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [88572790] [2025-03-04 16:22:00,793 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:00,793 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:00,794 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:00,794 INFO L85 PathProgramCache]: Analyzing trace with hash -1123275643, now seen corresponding path program 1 times [2025-03-04 16:22:00,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:00,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [333738603] [2025-03-04 16:22:00,794 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:00,794 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:00,813 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:00,829 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:00,832 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:00,832 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:00,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:00,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:00,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [333738603] [2025-03-04 16:22:00,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [333738603] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:00,902 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:00,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:00,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333445287] [2025-03-04 16:22:00,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:00,903 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:00,903 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:00,903 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:00,903 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:00,904 INFO L87 Difference]: Start difference. First operand 1715 states and 2531 transitions. cyclomatic complexity: 817 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:00,957 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:00,958 INFO L93 Difference]: Finished difference Result 1715 states and 2530 transitions. [2025-03-04 16:22:00,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2530 transitions. [2025-03-04 16:22:00,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:00,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2530 transitions. [2025-03-04 16:22:00,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:00,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:00,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2530 transitions. [2025-03-04 16:22:00,985 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:00,986 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2530 transitions. [2025-03-04 16:22:00,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2530 transitions. [2025-03-04 16:22:01,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:01,006 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4752186588921283) internal successors, (2530), 1714 states have internal predecessors, (2530), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2530 transitions. [2025-03-04 16:22:01,012 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2530 transitions. [2025-03-04 16:22:01,012 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:01,012 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2530 transitions. [2025-03-04 16:22:01,012 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:22:01,013 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2530 transitions. [2025-03-04 16:22:01,018 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,019 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:01,019 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:01,020 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,020 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,021 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume !(1 == ~t1_i~0);~t1_st~0 := 2;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:01,021 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:01,024 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,024 INFO L85 PathProgramCache]: Analyzing trace with hash 1179806279, now seen corresponding path program 1 times [2025-03-04 16:22:01,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658430280] [2025-03-04 16:22:01,024 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,039 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:01,044 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:01,044 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,044 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,095 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,096 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,096 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658430280] [2025-03-04 16:22:01,096 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658430280] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,096 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,096 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,096 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248080312] [2025-03-04 16:22:01,096 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,096 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:01,097 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,099 INFO L85 PathProgramCache]: Analyzing trace with hash -1352614075, now seen corresponding path program 1 times [2025-03-04 16:22:01,099 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,099 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1107377661] [2025-03-04 16:22:01,099 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,100 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,107 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:01,112 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:01,112 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,112 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,177 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,177 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1107377661] [2025-03-04 16:22:01,177 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1107377661] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,177 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1856968872] [2025-03-04 16:22:01,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,177 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:01,178 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:01,178 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:01,178 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:01,178 INFO L87 Difference]: Start difference. First operand 1715 states and 2530 transitions. cyclomatic complexity: 816 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:01,227 INFO L93 Difference]: Finished difference Result 1715 states and 2529 transitions. [2025-03-04 16:22:01,227 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2529 transitions. [2025-03-04 16:22:01,234 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2529 transitions. [2025-03-04 16:22:01,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:01,241 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:01,241 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2529 transitions. [2025-03-04 16:22:01,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:01,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2529 transitions. [2025-03-04 16:22:01,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2529 transitions. [2025-03-04 16:22:01,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:01,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4746355685131196) internal successors, (2529), 1714 states have internal predecessors, (2529), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,265 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2529 transitions. [2025-03-04 16:22:01,265 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2529 transitions. [2025-03-04 16:22:01,265 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:01,266 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2529 transitions. [2025-03-04 16:22:01,266 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:22:01,266 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2529 transitions. [2025-03-04 16:22:01,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,271 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:01,271 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:01,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,272 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume !(1 == ~t2_i~0);~t2_st~0 := 2;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:01,273 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:01,273 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,273 INFO L85 PathProgramCache]: Analyzing trace with hash -1180954618, now seen corresponding path program 1 times [2025-03-04 16:22:01,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1740687749] [2025-03-04 16:22:01,274 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,281 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:01,284 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:01,284 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,284 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1740687749] [2025-03-04 16:22:01,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1740687749] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [574721422] [2025-03-04 16:22:01,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,325 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:01,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,326 INFO L85 PathProgramCache]: Analyzing trace with hash -538848606, now seen corresponding path program 1 times [2025-03-04 16:22:01,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1802226082] [2025-03-04 16:22:01,326 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:01,344 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:01,344 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,344 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,396 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,396 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1802226082] [2025-03-04 16:22:01,396 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1802226082] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,396 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,396 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,396 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1756195525] [2025-03-04 16:22:01,396 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,396 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:01,397 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:01,397 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:01,397 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:01,398 INFO L87 Difference]: Start difference. First operand 1715 states and 2529 transitions. cyclomatic complexity: 815 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:01,423 INFO L93 Difference]: Finished difference Result 1715 states and 2528 transitions. [2025-03-04 16:22:01,423 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2528 transitions. [2025-03-04 16:22:01,431 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,437 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2528 transitions. [2025-03-04 16:22:01,437 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:01,438 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:01,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2528 transitions. [2025-03-04 16:22:01,441 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:01,441 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2528 transitions. [2025-03-04 16:22:01,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2528 transitions. [2025-03-04 16:22:01,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:01,460 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4740524781341109) internal successors, (2528), 1714 states have internal predecessors, (2528), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,464 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2528 transitions. [2025-03-04 16:22:01,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2528 transitions. [2025-03-04 16:22:01,465 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:01,466 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2528 transitions. [2025-03-04 16:22:01,466 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:22:01,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2528 transitions. [2025-03-04 16:22:01,472 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,472 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:01,472 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:01,474 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,474 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,474 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume !(1 == ~t3_i~0);~t3_st~0 := 2;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:01,474 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:01,474 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,475 INFO L85 PathProgramCache]: Analyzing trace with hash 1236743783, now seen corresponding path program 1 times [2025-03-04 16:22:01,475 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,475 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [800704731] [2025-03-04 16:22:01,475 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:01,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:01,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,553 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,553 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [800704731] [2025-03-04 16:22:01,553 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [800704731] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,553 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,553 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,553 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1579774120] [2025-03-04 16:22:01,554 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,554 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:01,554 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,554 INFO L85 PathProgramCache]: Analyzing trace with hash 468193803, now seen corresponding path program 1 times [2025-03-04 16:22:01,554 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126696442] [2025-03-04 16:22:01,555 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,555 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,565 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:01,574 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:01,574 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,574 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2126696442] [2025-03-04 16:22:01,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2126696442] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2127446988] [2025-03-04 16:22:01,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,627 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:01,627 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:01,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:01,628 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:01,628 INFO L87 Difference]: Start difference. First operand 1715 states and 2528 transitions. cyclomatic complexity: 814 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:01,655 INFO L93 Difference]: Finished difference Result 1715 states and 2527 transitions. [2025-03-04 16:22:01,655 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2527 transitions. [2025-03-04 16:22:01,664 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,670 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2527 transitions. [2025-03-04 16:22:01,670 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:01,671 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:01,672 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2527 transitions. [2025-03-04 16:22:01,674 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:01,674 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2527 transitions. [2025-03-04 16:22:01,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2527 transitions. [2025-03-04 16:22:01,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:01,691 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.473469387755102) internal successors, (2527), 1714 states have internal predecessors, (2527), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2527 transitions. [2025-03-04 16:22:01,696 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2527 transitions. [2025-03-04 16:22:01,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:01,697 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2527 transitions. [2025-03-04 16:22:01,698 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:22:01,698 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2527 transitions. [2025-03-04 16:22:01,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,702 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:01,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:01,704 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,704 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,704 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume !(1 == ~t4_i~0);~t4_st~0 := 2;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:01,704 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:01,705 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,705 INFO L85 PathProgramCache]: Analyzing trace with hash 1314734054, now seen corresponding path program 1 times [2025-03-04 16:22:01,705 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,706 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [72635947] [2025-03-04 16:22:01,706 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,706 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,718 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:01,720 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:01,721 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,721 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,747 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,748 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,748 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [72635947] [2025-03-04 16:22:01,748 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [72635947] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,748 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,748 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,748 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558382931] [2025-03-04 16:22:01,748 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,748 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:01,749 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,749 INFO L85 PathProgramCache]: Analyzing trace with hash -898254232, now seen corresponding path program 1 times [2025-03-04 16:22:01,750 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,751 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1794849859] [2025-03-04 16:22:01,751 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,751 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,758 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:01,764 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:01,765 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,765 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1794849859] [2025-03-04 16:22:01,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1794849859] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1183401009] [2025-03-04 16:22:01,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,804 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:01,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:01,805 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:01,805 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:01,805 INFO L87 Difference]: Start difference. First operand 1715 states and 2527 transitions. cyclomatic complexity: 813 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:01,856 INFO L93 Difference]: Finished difference Result 1715 states and 2526 transitions. [2025-03-04 16:22:01,856 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2526 transitions. [2025-03-04 16:22:01,862 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,869 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2526 transitions. [2025-03-04 16:22:01,869 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:01,870 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:01,870 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2526 transitions. [2025-03-04 16:22:01,872 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:01,872 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2526 transitions. [2025-03-04 16:22:01,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2526 transitions. [2025-03-04 16:22:01,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:01,891 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4728862973760932) internal successors, (2526), 1714 states have internal predecessors, (2526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:01,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2526 transitions. [2025-03-04 16:22:01,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2526 transitions. [2025-03-04 16:22:01,896 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:01,898 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2526 transitions. [2025-03-04 16:22:01,898 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:22:01,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2526 transitions. [2025-03-04 16:22:01,902 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:01,904 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:01,904 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:01,905 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,905 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:01,906 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume !(1 == ~t5_i~0);~t5_st~0 := 2;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:01,906 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:01,906 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,906 INFO L85 PathProgramCache]: Analyzing trace with hash -1038054777, now seen corresponding path program 1 times [2025-03-04 16:22:01,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1001858438] [2025-03-04 16:22:01,907 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,914 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:01,917 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:01,917 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,917 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:01,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:01,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:01,946 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1001858438] [2025-03-04 16:22:01,946 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1001858438] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:01,946 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:01,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:01,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1558517460] [2025-03-04 16:22:01,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:01,947 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:01,947 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:01,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1456399749, now seen corresponding path program 1 times [2025-03-04 16:22:01,947 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:01,947 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [496033602] [2025-03-04 16:22:01,947 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:01,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:01,956 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:01,960 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:01,961 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:01,961 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [496033602] [2025-03-04 16:22:02,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [496033602] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1238127879] [2025-03-04 16:22:02,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,004 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,005 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,005 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,005 INFO L87 Difference]: Start difference. First operand 1715 states and 2526 transitions. cyclomatic complexity: 812 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,030 INFO L93 Difference]: Finished difference Result 1715 states and 2525 transitions. [2025-03-04 16:22:02,030 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2525 transitions. [2025-03-04 16:22:02,036 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,043 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2525 transitions. [2025-03-04 16:22:02,043 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,044 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,044 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2525 transitions. [2025-03-04 16:22:02,046 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,046 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2525 transitions. [2025-03-04 16:22:02,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2525 transitions. [2025-03-04 16:22:02,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,067 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4723032069970845) internal successors, (2525), 1714 states have internal predecessors, (2525), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2525 transitions. [2025-03-04 16:22:02,071 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2525 transitions. [2025-03-04 16:22:02,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,072 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2525 transitions. [2025-03-04 16:22:02,073 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:22:02,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2525 transitions. [2025-03-04 16:22:02,077 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,077 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,077 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,079 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,079 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,079 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume !(1 == ~t6_i~0);~t6_st~0 := 2;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,079 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,080 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,080 INFO L85 PathProgramCache]: Analyzing trace with hash -144119866, now seen corresponding path program 1 times [2025-03-04 16:22:02,080 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,080 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [679444537] [2025-03-04 16:22:02,080 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,080 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,089 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,093 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,093 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,093 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,134 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,135 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,135 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [679444537] [2025-03-04 16:22:02,135 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [679444537] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,135 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,135 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,135 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128048356] [2025-03-04 16:22:02,135 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,135 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,135 INFO L85 PathProgramCache]: Analyzing trace with hash -898254232, now seen corresponding path program 2 times [2025-03-04 16:22:02,136 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,136 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [648216959] [2025-03-04 16:22:02,136 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:22:02,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,142 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:02,147 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,147 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:22:02,147 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [648216959] [2025-03-04 16:22:02,189 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [648216959] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,189 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,189 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,189 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21957291] [2025-03-04 16:22:02,189 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,189 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,189 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,189 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,189 INFO L87 Difference]: Start difference. First operand 1715 states and 2525 transitions. cyclomatic complexity: 811 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,223 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,223 INFO L93 Difference]: Finished difference Result 1715 states and 2524 transitions. [2025-03-04 16:22:02,223 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2524 transitions. [2025-03-04 16:22:02,230 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2524 transitions. [2025-03-04 16:22:02,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,238 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,238 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2524 transitions. [2025-03-04 16:22:02,240 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,240 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2524 transitions. [2025-03-04 16:22:02,242 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2524 transitions. [2025-03-04 16:22:02,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4717201166180758) internal successors, (2524), 1714 states have internal predecessors, (2524), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2524 transitions. [2025-03-04 16:22:02,268 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2524 transitions. [2025-03-04 16:22:02,268 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,270 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2524 transitions. [2025-03-04 16:22:02,270 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:22:02,270 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2524 transitions. [2025-03-04 16:22:02,275 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,275 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,275 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,278 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,278 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,278 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume !(1 == ~t8_i~0);~t8_st~0 := 2;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,278 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,278 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,279 INFO L85 PathProgramCache]: Analyzing trace with hash -1223661913, now seen corresponding path program 1 times [2025-03-04 16:22:02,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1965919129] [2025-03-04 16:22:02,279 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,290 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,294 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,294 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,294 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1965919129] [2025-03-04 16:22:02,324 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1965919129] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,324 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,324 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,324 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1462220028] [2025-03-04 16:22:02,324 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,324 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,325 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,325 INFO L85 PathProgramCache]: Analyzing trace with hash -1709745211, now seen corresponding path program 1 times [2025-03-04 16:22:02,325 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,325 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599588581] [2025-03-04 16:22:02,325 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,325 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,336 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:02,341 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,341 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,341 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599588581] [2025-03-04 16:22:02,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599588581] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,382 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [777531957] [2025-03-04 16:22:02,382 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,382 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,382 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,382 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,382 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,383 INFO L87 Difference]: Start difference. First operand 1715 states and 2524 transitions. cyclomatic complexity: 810 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,412 INFO L93 Difference]: Finished difference Result 1715 states and 2523 transitions. [2025-03-04 16:22:02,412 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2523 transitions. [2025-03-04 16:22:02,423 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,429 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2523 transitions. [2025-03-04 16:22:02,429 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,430 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,430 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2523 transitions. [2025-03-04 16:22:02,432 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,432 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2523 transitions. [2025-03-04 16:22:02,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2523 transitions. [2025-03-04 16:22:02,449 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,451 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.471137026239067) internal successors, (2523), 1714 states have internal predecessors, (2523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,456 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2523 transitions. [2025-03-04 16:22:02,456 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2523 transitions. [2025-03-04 16:22:02,456 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,457 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2523 transitions. [2025-03-04 16:22:02,457 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:22:02,457 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2523 transitions. [2025-03-04 16:22:02,461 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,462 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,462 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,463 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,463 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,463 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume !(1 == ~t9_i~0);~t9_st~0 := 2;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,463 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,464 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,464 INFO L85 PathProgramCache]: Analyzing trace with hash 714877384, now seen corresponding path program 1 times [2025-03-04 16:22:02,464 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,464 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [91165441] [2025-03-04 16:22:02,464 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,464 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,473 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,475 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,476 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,476 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,499 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,499 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,499 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [91165441] [2025-03-04 16:22:02,499 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [91165441] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,499 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,499 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,499 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1028534015] [2025-03-04 16:22:02,499 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,499 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,499 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,500 INFO L85 PathProgramCache]: Analyzing trace with hash -1900441624, now seen corresponding path program 1 times [2025-03-04 16:22:02,500 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,500 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [73359403] [2025-03-04 16:22:02,500 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,500 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,507 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:02,511 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,511 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,511 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [73359403] [2025-03-04 16:22:02,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [73359403] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1356826992] [2025-03-04 16:22:02,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,543 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,543 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,543 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,543 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,543 INFO L87 Difference]: Start difference. First operand 1715 states and 2523 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,579 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,579 INFO L93 Difference]: Finished difference Result 1715 states and 2522 transitions. [2025-03-04 16:22:02,579 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2522 transitions. [2025-03-04 16:22:02,584 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2522 transitions. [2025-03-04 16:22:02,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,590 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,590 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2522 transitions. [2025-03-04 16:22:02,592 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,592 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2522 transitions. [2025-03-04 16:22:02,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2522 transitions. [2025-03-04 16:22:02,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4705539358600583) internal successors, (2522), 1714 states have internal predecessors, (2522), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2522 transitions. [2025-03-04 16:22:02,615 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2522 transitions. [2025-03-04 16:22:02,615 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,615 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2522 transitions. [2025-03-04 16:22:02,616 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:22:02,616 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2522 transitions. [2025-03-04 16:22:02,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,621 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,621 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,622 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,622 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,622 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume !(1 == ~t10_i~0);~t10_st~0 := 2;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,623 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,623 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,623 INFO L85 PathProgramCache]: Analyzing trace with hash -2132083065, now seen corresponding path program 1 times [2025-03-04 16:22:02,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364993063] [2025-03-04 16:22:02,623 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,623 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,631 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,634 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,635 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,635 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,656 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,656 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,656 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364993063] [2025-03-04 16:22:02,656 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364993063] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,656 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,656 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,657 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [325080783] [2025-03-04 16:22:02,657 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,657 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,657 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,657 INFO L85 PathProgramCache]: Analyzing trace with hash -898254232, now seen corresponding path program 3 times [2025-03-04 16:22:02,657 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,657 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1095716518] [2025-03-04 16:22:02,657 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:22:02,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,667 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:02,672 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,672 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:22:02,672 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1095716518] [2025-03-04 16:22:02,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1095716518] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,704 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,704 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,704 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112484985] [2025-03-04 16:22:02,704 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,704 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,704 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,706 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,706 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,706 INFO L87 Difference]: Start difference. First operand 1715 states and 2522 transitions. cyclomatic complexity: 808 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,727 INFO L93 Difference]: Finished difference Result 1715 states and 2521 transitions. [2025-03-04 16:22:02,727 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2521 transitions. [2025-03-04 16:22:02,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2521 transitions. [2025-03-04 16:22:02,742 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,746 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,746 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2521 transitions. [2025-03-04 16:22:02,749 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,749 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2521 transitions. [2025-03-04 16:22:02,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2521 transitions. [2025-03-04 16:22:02,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4699708454810496) internal successors, (2521), 1714 states have internal predecessors, (2521), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2521 transitions. [2025-03-04 16:22:02,777 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2521 transitions. [2025-03-04 16:22:02,780 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,781 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2521 transitions. [2025-03-04 16:22:02,781 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:22:02,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2521 transitions. [2025-03-04 16:22:02,786 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,788 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume !(1 == ~t11_i~0);~t11_st~0 := 2;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,788 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,788 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,788 INFO L85 PathProgramCache]: Analyzing trace with hash 824120808, now seen corresponding path program 1 times [2025-03-04 16:22:02,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [584738637] [2025-03-04 16:22:02,788 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,796 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,799 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,799 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,799 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [584738637] [2025-03-04 16:22:02,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [584738637] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,825 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2116064560] [2025-03-04 16:22:02,825 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,825 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,825 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,825 INFO L85 PathProgramCache]: Analyzing trace with hash 1508629602, now seen corresponding path program 1 times [2025-03-04 16:22:02,825 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,825 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1625849967] [2025-03-04 16:22:02,825 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,834 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:02,838 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,839 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,839 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,868 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1625849967] [2025-03-04 16:22:02,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1625849967] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1716951460] [2025-03-04 16:22:02,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,869 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:02,870 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:02,870 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:02,870 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:02,870 INFO L87 Difference]: Start difference. First operand 1715 states and 2521 transitions. cyclomatic complexity: 807 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,891 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:02,891 INFO L93 Difference]: Finished difference Result 1715 states and 2520 transitions. [2025-03-04 16:22:02,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2520 transitions. [2025-03-04 16:22:02,897 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,901 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2520 transitions. [2025-03-04 16:22:02,901 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:02,902 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:02,902 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2520 transitions. [2025-03-04 16:22:02,904 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:02,904 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2520 transitions. [2025-03-04 16:22:02,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2520 transitions. [2025-03-04 16:22:02,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:02,922 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.469387755102041) internal successors, (2520), 1714 states have internal predecessors, (2520), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:02,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2520 transitions. [2025-03-04 16:22:02,925 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2520 transitions. [2025-03-04 16:22:02,926 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:02,926 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2520 transitions. [2025-03-04 16:22:02,926 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:22:02,926 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2520 transitions. [2025-03-04 16:22:02,931 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:02,931 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:02,931 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:02,933 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,933 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:02,933 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume !(1 == ~t12_i~0);~t12_st~0 := 2;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:02,933 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:02,933 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,933 INFO L85 PathProgramCache]: Analyzing trace with hash 642387559, now seen corresponding path program 1 times [2025-03-04 16:22:02,933 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,934 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [669041621] [2025-03-04 16:22:02,934 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:02,934 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,940 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:02,942 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:02,942 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:02,942 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:02,975 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:02,975 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:02,975 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [669041621] [2025-03-04 16:22:02,975 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [669041621] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:02,975 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:02,975 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:02,975 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1851176099] [2025-03-04 16:22:02,976 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:02,976 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:02,976 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:02,976 INFO L85 PathProgramCache]: Analyzing trace with hash -898254232, now seen corresponding path program 4 times [2025-03-04 16:22:02,976 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:02,976 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1333836169] [2025-03-04 16:22:02,976 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:22:02,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:02,984 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 152 statements into 2 equivalence classes. [2025-03-04 16:22:02,987 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:02,987 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 1 check-sat command(s) [2025-03-04 16:22:02,987 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,015 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,015 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,015 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1333836169] [2025-03-04 16:22:03,015 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1333836169] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,015 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,015 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,015 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1988011223] [2025-03-04 16:22:03,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,015 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:03,015 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:03,015 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:03,016 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:03,016 INFO L87 Difference]: Start difference. First operand 1715 states and 2520 transitions. cyclomatic complexity: 806 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,036 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:03,036 INFO L93 Difference]: Finished difference Result 1715 states and 2519 transitions. [2025-03-04 16:22:03,036 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1715 states and 2519 transitions. [2025-03-04 16:22:03,040 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:03,044 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1715 states to 1715 states and 2519 transitions. [2025-03-04 16:22:03,044 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1715 [2025-03-04 16:22:03,045 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1715 [2025-03-04 16:22:03,045 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1715 states and 2519 transitions. [2025-03-04 16:22:03,047 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:03,047 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2519 transitions. [2025-03-04 16:22:03,049 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1715 states and 2519 transitions. [2025-03-04 16:22:03,063 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1715 to 1715. [2025-03-04 16:22:03,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1715 states, 1715 states have (on average 1.4688046647230322) internal successors, (2519), 1714 states have internal predecessors, (2519), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1715 states to 1715 states and 2519 transitions. [2025-03-04 16:22:03,069 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1715 states and 2519 transitions. [2025-03-04 16:22:03,069 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:03,070 INFO L432 stractBuchiCegarLoop]: Abstraction has 1715 states and 2519 transitions. [2025-03-04 16:22:03,070 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:22:03,070 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1715 states and 2519 transitions. [2025-03-04 16:22:03,074 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1554 [2025-03-04 16:22:03,074 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:03,074 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:03,076 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,076 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,076 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:03,076 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume 0 == ~T1_E~0;~T1_E~0 := 1;" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:03,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,076 INFO L85 PathProgramCache]: Analyzing trace with hash 497977864, now seen corresponding path program 1 times [2025-03-04 16:22:03,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,076 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [407381583] [2025-03-04 16:22:03,077 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,083 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:03,087 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:03,087 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,087 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,141 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,141 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [407381583] [2025-03-04 16:22:03,141 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [407381583] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,141 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,141 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1384530274] [2025-03-04 16:22:03,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,142 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:03,142 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,142 INFO L85 PathProgramCache]: Analyzing trace with hash 1948120796, now seen corresponding path program 1 times [2025-03-04 16:22:03,143 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,143 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1202471996] [2025-03-04 16:22:03,143 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,143 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,150 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:03,153 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:03,154 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,154 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,183 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,184 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,184 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1202471996] [2025-03-04 16:22:03,184 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1202471996] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,184 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,184 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,184 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1299435804] [2025-03-04 16:22:03,184 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,184 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:03,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:03,185 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:22:03,185 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:22:03,185 INFO L87 Difference]: Start difference. First operand 1715 states and 2519 transitions. cyclomatic complexity: 805 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:03,330 INFO L93 Difference]: Finished difference Result 3176 states and 4649 transitions. [2025-03-04 16:22:03,330 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3176 states and 4649 transitions. [2025-03-04 16:22:03,340 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2990 [2025-03-04 16:22:03,348 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3176 states to 3176 states and 4649 transitions. [2025-03-04 16:22:03,348 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3176 [2025-03-04 16:22:03,350 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3176 [2025-03-04 16:22:03,350 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3176 states and 4649 transitions. [2025-03-04 16:22:03,353 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:03,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3176 states and 4649 transitions. [2025-03-04 16:22:03,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3176 states and 4649 transitions. [2025-03-04 16:22:03,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3176 to 3176. [2025-03-04 16:22:03,389 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3176 states, 3176 states have (on average 1.4637909319899245) internal successors, (4649), 3175 states have internal predecessors, (4649), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,395 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3176 states to 3176 states and 4649 transitions. [2025-03-04 16:22:03,395 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3176 states and 4649 transitions. [2025-03-04 16:22:03,396 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:22:03,396 INFO L432 stractBuchiCegarLoop]: Abstraction has 3176 states and 4649 transitions. [2025-03-04 16:22:03,396 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:22:03,396 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3176 states and 4649 transitions. [2025-03-04 16:22:03,404 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2990 [2025-03-04 16:22:03,404 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:03,404 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:03,406 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,406 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,406 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:03,406 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume 0 == ~T9_E~0;~T9_E~0 := 1;" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume !(1 == ~t12_pc~0);" "is_transmit12_triggered_~__retres1~12#1 := 0;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:03,407 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,407 INFO L85 PathProgramCache]: Analyzing trace with hash -7067926, now seen corresponding path program 1 times [2025-03-04 16:22:03,407 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,407 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [705533239] [2025-03-04 16:22:03,407 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,407 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,429 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:03,432 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:03,432 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,432 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,476 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,476 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [705533239] [2025-03-04 16:22:03,476 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [705533239] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,476 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,476 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,477 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1941806994] [2025-03-04 16:22:03,477 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,477 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:03,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,477 INFO L85 PathProgramCache]: Analyzing trace with hash -1677410426, now seen corresponding path program 1 times [2025-03-04 16:22:03,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,477 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1501309553] [2025-03-04 16:22:03,477 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,485 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:03,489 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:03,489 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,489 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,522 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,523 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1501309553] [2025-03-04 16:22:03,523 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1501309553] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,523 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,523 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,523 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1067458278] [2025-03-04 16:22:03,523 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,523 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:03,524 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:03,524 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:22:03,524 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:22:03,524 INFO L87 Difference]: Start difference. First operand 3176 states and 4649 transitions. cyclomatic complexity: 1475 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,647 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:03,647 INFO L93 Difference]: Finished difference Result 6088 states and 8890 transitions. [2025-03-04 16:22:03,647 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6088 states and 8890 transitions. [2025-03-04 16:22:03,669 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5862 [2025-03-04 16:22:03,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6088 states to 6088 states and 8890 transitions. [2025-03-04 16:22:03,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6088 [2025-03-04 16:22:03,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6088 [2025-03-04 16:22:03,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6088 states and 8890 transitions. [2025-03-04 16:22:03,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:03,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6088 states and 8890 transitions. [2025-03-04 16:22:03,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6088 states and 8890 transitions. [2025-03-04 16:22:03,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6088 to 6088. [2025-03-04 16:22:03,766 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6088 states, 6088 states have (on average 1.4602496714848883) internal successors, (8890), 6087 states have internal predecessors, (8890), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:03,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6088 states to 6088 states and 8890 transitions. [2025-03-04 16:22:03,780 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6088 states and 8890 transitions. [2025-03-04 16:22:03,781 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:22:03,781 INFO L432 stractBuchiCegarLoop]: Abstraction has 6088 states and 8890 transitions. [2025-03-04 16:22:03,781 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:22:03,781 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6088 states and 8890 transitions. [2025-03-04 16:22:03,801 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 5862 [2025-03-04 16:22:03,802 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:03,802 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:03,803 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,803 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:03,804 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:03,804 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume 0 == ~E_5~0;~E_5~0 := 1;" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:03,804 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,804 INFO L85 PathProgramCache]: Analyzing trace with hash -1910528021, now seen corresponding path program 1 times [2025-03-04 16:22:03,804 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [899531959] [2025-03-04 16:22:03,805 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,812 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:03,815 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:03,815 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,815 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,888 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,888 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,888 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [899531959] [2025-03-04 16:22:03,888 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [899531959] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,888 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,888 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,889 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686472977] [2025-03-04 16:22:03,889 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,889 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:03,889 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:03,889 INFO L85 PathProgramCache]: Analyzing trace with hash -135715351, now seen corresponding path program 1 times [2025-03-04 16:22:03,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:03,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1683508512] [2025-03-04 16:22:03,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:03,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:03,896 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:03,900 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:03,900 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:03,900 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:03,932 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:03,932 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:03,933 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1683508512] [2025-03-04 16:22:03,933 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1683508512] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:03,933 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:03,933 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:03,933 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1314603334] [2025-03-04 16:22:03,933 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:03,933 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:03,933 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:03,934 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:22:03,934 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:22:03,934 INFO L87 Difference]: Start difference. First operand 6088 states and 8890 transitions. cyclomatic complexity: 2806 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:04,152 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:04,152 INFO L93 Difference]: Finished difference Result 11504 states and 16765 transitions. [2025-03-04 16:22:04,152 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11504 states and 16765 transitions. [2025-03-04 16:22:04,204 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11234 [2025-03-04 16:22:04,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11504 states to 11504 states and 16765 transitions. [2025-03-04 16:22:04,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11504 [2025-03-04 16:22:04,247 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11504 [2025-03-04 16:22:04,247 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11504 states and 16765 transitions. [2025-03-04 16:22:04,261 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:04,261 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11504 states and 16765 transitions. [2025-03-04 16:22:04,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11504 states and 16765 transitions. [2025-03-04 16:22:04,377 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11504 to 11500. [2025-03-04 16:22:04,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11500 states, 11500 states have (on average 1.4574782608695651) internal successors, (16761), 11499 states have internal predecessors, (16761), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:04,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11500 states to 11500 states and 16761 transitions. [2025-03-04 16:22:04,420 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11500 states and 16761 transitions. [2025-03-04 16:22:04,420 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:22:04,420 INFO L432 stractBuchiCegarLoop]: Abstraction has 11500 states and 16761 transitions. [2025-03-04 16:22:04,420 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:22:04,420 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11500 states and 16761 transitions. [2025-03-04 16:22:04,450 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11234 [2025-03-04 16:22:04,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:04,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:04,452 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:04,452 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:04,453 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume 1 == ~m_pc~0;" "assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:04,453 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:04,454 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:04,454 INFO L85 PathProgramCache]: Analyzing trace with hash 1100528108, now seen corresponding path program 1 times [2025-03-04 16:22:04,454 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:04,454 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1313423443] [2025-03-04 16:22:04,454 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:04,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:04,461 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:04,463 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:04,463 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:04,463 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:04,542 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:04,542 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:04,542 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1313423443] [2025-03-04 16:22:04,542 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1313423443] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:04,542 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:04,542 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:04,542 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1992102716] [2025-03-04 16:22:04,542 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:04,542 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:04,543 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:04,543 INFO L85 PathProgramCache]: Analyzing trace with hash -224563745, now seen corresponding path program 1 times [2025-03-04 16:22:04,543 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:04,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1406696836] [2025-03-04 16:22:04,543 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:04,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:04,549 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:04,553 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:04,553 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:04,553 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:04,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:04,580 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:04,580 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1406696836] [2025-03-04 16:22:04,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1406696836] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:04,580 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:04,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:04,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [744158051] [2025-03-04 16:22:04,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:04,580 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:04,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:04,580 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:04,580 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:04,581 INFO L87 Difference]: Start difference. First operand 11500 states and 16761 transitions. cyclomatic complexity: 5269 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:04,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:04,708 INFO L93 Difference]: Finished difference Result 22616 states and 32742 transitions. [2025-03-04 16:22:04,708 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 22616 states and 32742 transitions. [2025-03-04 16:22:04,793 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 22335 [2025-03-04 16:22:04,860 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 22616 states to 22616 states and 32742 transitions. [2025-03-04 16:22:04,860 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 22616 [2025-03-04 16:22:04,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 22616 [2025-03-04 16:22:04,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 22616 states and 32742 transitions. [2025-03-04 16:22:04,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:04,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 22616 states and 32742 transitions. [2025-03-04 16:22:04,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22616 states and 32742 transitions. [2025-03-04 16:22:05,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22616 to 21880. [2025-03-04 16:22:05,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21880 states, 21880 states have (on average 1.4492687385740401) internal successors, (31710), 21879 states have internal predecessors, (31710), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:05,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21880 states to 21880 states and 31710 transitions. [2025-03-04 16:22:05,300 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21880 states and 31710 transitions. [2025-03-04 16:22:05,301 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:05,301 INFO L432 stractBuchiCegarLoop]: Abstraction has 21880 states and 31710 transitions. [2025-03-04 16:22:05,301 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:22:05,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21880 states and 31710 transitions. [2025-03-04 16:22:05,354 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 21599 [2025-03-04 16:22:05,355 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:05,355 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:05,356 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:05,356 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:05,357 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:05,357 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume 1 == ~t1_pc~0;" "assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:05,357 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:05,357 INFO L85 PathProgramCache]: Analyzing trace with hash -466398135, now seen corresponding path program 1 times [2025-03-04 16:22:05,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:05,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955537615] [2025-03-04 16:22:05,358 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:05,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:05,364 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:05,367 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:05,368 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:05,368 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:05,403 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:05,404 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:05,404 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955537615] [2025-03-04 16:22:05,404 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955537615] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:05,404 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:05,404 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:05,404 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [915408985] [2025-03-04 16:22:05,404 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:05,404 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:05,405 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:05,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1257473433, now seen corresponding path program 1 times [2025-03-04 16:22:05,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:05,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1306109066] [2025-03-04 16:22:05,405 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:05,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:05,412 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:05,415 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:05,416 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:05,416 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:05,442 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:05,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:05,443 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1306109066] [2025-03-04 16:22:05,443 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1306109066] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:05,443 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:05,443 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:05,443 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [872128220] [2025-03-04 16:22:05,443 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:05,443 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:05,443 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:05,443 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:05,443 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:05,444 INFO L87 Difference]: Start difference. First operand 21880 states and 31710 transitions. cyclomatic complexity: 9846 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:05,734 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:05,734 INFO L93 Difference]: Finished difference Result 41804 states and 60284 transitions. [2025-03-04 16:22:05,734 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41804 states and 60284 transitions. [2025-03-04 16:22:05,977 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41492 [2025-03-04 16:22:06,122 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41804 states to 41804 states and 60284 transitions. [2025-03-04 16:22:06,123 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41804 [2025-03-04 16:22:06,165 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41804 [2025-03-04 16:22:06,165 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41804 states and 60284 transitions. [2025-03-04 16:22:06,205 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:06,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41804 states and 60284 transitions. [2025-03-04 16:22:06,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41804 states and 60284 transitions. [2025-03-04 16:22:06,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41804 to 41756. [2025-03-04 16:22:06,708 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 41756 states, 41756 states have (on average 1.4425711275026343) internal successors, (60236), 41755 states have internal predecessors, (60236), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:06,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 41756 states to 41756 states and 60236 transitions. [2025-03-04 16:22:06,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 41756 states and 60236 transitions. [2025-03-04 16:22:06,801 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:06,802 INFO L432 stractBuchiCegarLoop]: Abstraction has 41756 states and 60236 transitions. [2025-03-04 16:22:06,802 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 16:22:06,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 41756 states and 60236 transitions. [2025-03-04 16:22:06,937 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41444 [2025-03-04 16:22:06,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:06,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:06,939 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:06,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:06,940 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:06,940 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume 1 == ~t2_pc~0;" "assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume !(1 == ~t12_pc~0);" "is_transmit12_triggered_~__retres1~12#1 := 0;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:06,941 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:06,941 INFO L85 PathProgramCache]: Analyzing trace with hash 1274296422, now seen corresponding path program 1 times [2025-03-04 16:22:06,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:06,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [121911433] [2025-03-04 16:22:06,941 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:06,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:06,950 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:07,093 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:07,094 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:07,094 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:07,133 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:07,134 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:07,134 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [121911433] [2025-03-04 16:22:07,134 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [121911433] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:07,134 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:07,134 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:07,134 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972224102] [2025-03-04 16:22:07,134 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:07,134 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:07,135 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:07,135 INFO L85 PathProgramCache]: Analyzing trace with hash 981067312, now seen corresponding path program 1 times [2025-03-04 16:22:07,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:07,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2048172738] [2025-03-04 16:22:07,135 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:07,136 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:07,143 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:07,147 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:07,148 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:07,148 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:07,179 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:07,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:07,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2048172738] [2025-03-04 16:22:07,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2048172738] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:07,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:07,180 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:07,180 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1609607817] [2025-03-04 16:22:07,180 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:07,180 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:07,180 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:07,181 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:07,181 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:07,181 INFO L87 Difference]: Start difference. First operand 41756 states and 60236 transitions. cyclomatic complexity: 18512 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:07,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:07,563 INFO L93 Difference]: Finished difference Result 79931 states and 114813 transitions. [2025-03-04 16:22:07,563 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 79931 states and 114813 transitions. [2025-03-04 16:22:07,831 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 79508 [2025-03-04 16:22:08,035 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 79931 states to 79931 states and 114813 transitions. [2025-03-04 16:22:08,035 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 79931 [2025-03-04 16:22:08,081 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 79931 [2025-03-04 16:22:08,081 INFO L73 IsDeterministic]: Start isDeterministic. Operand 79931 states and 114813 transitions. [2025-03-04 16:22:08,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:08,131 INFO L218 hiAutomatonCegarLoop]: Abstraction has 79931 states and 114813 transitions. [2025-03-04 16:22:08,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79931 states and 114813 transitions. [2025-03-04 16:22:09,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79931 to 79835. [2025-03-04 16:22:09,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 79835 states, 79835 states have (on average 1.4369261602054237) internal successors, (114717), 79834 states have internal predecessors, (114717), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:09,237 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79835 states to 79835 states and 114717 transitions. [2025-03-04 16:22:09,237 INFO L240 hiAutomatonCegarLoop]: Abstraction has 79835 states and 114717 transitions. [2025-03-04 16:22:09,238 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:09,238 INFO L432 stractBuchiCegarLoop]: Abstraction has 79835 states and 114717 transitions. [2025-03-04 16:22:09,238 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 16:22:09,238 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 79835 states and 114717 transitions. [2025-03-04 16:22:09,479 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 79412 [2025-03-04 16:22:09,479 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:09,479 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:09,482 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:09,482 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:09,482 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume 1 == ~t3_pc~0;" "assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:09,482 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:09,484 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:09,484 INFO L85 PathProgramCache]: Analyzing trace with hash -1094339005, now seen corresponding path program 1 times [2025-03-04 16:22:09,484 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:09,484 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1450748279] [2025-03-04 16:22:09,484 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:09,484 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:09,497 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:09,502 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:09,502 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:09,502 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:09,768 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:09,769 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:09,769 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1450748279] [2025-03-04 16:22:09,769 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1450748279] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:09,769 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:09,769 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:09,769 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1418020231] [2025-03-04 16:22:09,769 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:09,770 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:09,770 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:09,770 INFO L85 PathProgramCache]: Analyzing trace with hash 1132924877, now seen corresponding path program 1 times [2025-03-04 16:22:09,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:09,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2031158160] [2025-03-04 16:22:09,770 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:09,771 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:09,777 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:09,780 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:09,780 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:09,780 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:09,804 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:09,805 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:09,805 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2031158160] [2025-03-04 16:22:09,805 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2031158160] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:09,805 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:09,805 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:09,805 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238649688] [2025-03-04 16:22:09,805 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:09,805 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:09,805 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:09,806 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:09,806 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:09,806 INFO L87 Difference]: Start difference. First operand 79835 states and 114717 transitions. cyclomatic complexity: 34946 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:10,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:10,373 INFO L93 Difference]: Finished difference Result 152838 states and 218758 transitions. [2025-03-04 16:22:10,373 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 152838 states and 218758 transitions. [2025-03-04 16:22:11,024 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 152128 [2025-03-04 16:22:11,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 152838 states to 152838 states and 218758 transitions. [2025-03-04 16:22:11,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 152838 [2025-03-04 16:22:11,539 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 152838 [2025-03-04 16:22:11,539 INFO L73 IsDeterministic]: Start isDeterministic. Operand 152838 states and 218758 transitions. [2025-03-04 16:22:11,577 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:11,578 INFO L218 hiAutomatonCegarLoop]: Abstraction has 152838 states and 218758 transitions. [2025-03-04 16:22:11,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 152838 states and 218758 transitions. [2025-03-04 16:22:12,993 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 152838 to 152646. [2025-03-04 16:22:13,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 152646 states, 152646 states have (on average 1.4318488529014846) internal successors, (218566), 152645 states have internal predecessors, (218566), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:13,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 152646 states to 152646 states and 218566 transitions. [2025-03-04 16:22:13,802 INFO L240 hiAutomatonCegarLoop]: Abstraction has 152646 states and 218566 transitions. [2025-03-04 16:22:13,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:13,802 INFO L432 stractBuchiCegarLoop]: Abstraction has 152646 states and 218566 transitions. [2025-03-04 16:22:13,802 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 16:22:13,803 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 152646 states and 218566 transitions. [2025-03-04 16:22:14,148 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 151936 [2025-03-04 16:22:14,148 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:14,148 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:14,150 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:14,150 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:14,150 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume 1 == ~t4_pc~0;" "assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:14,150 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume !(1 == ~t6_pc~0);" "is_transmit6_triggered_~__retres1~6#1 := 0;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume !(1 == ~t9_pc~0);" "is_transmit9_triggered_~__retres1~9#1 := 0;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume !(1 == ~t10_pc~0);" "is_transmit10_triggered_~__retres1~10#1 := 0;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume !(1 == ~t11_pc~0);" "is_transmit11_triggered_~__retres1~11#1 := 0;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume !(1 == ~t12_pc~0);" "is_transmit12_triggered_~__retres1~12#1 := 0;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:14,151 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:14,151 INFO L85 PathProgramCache]: Analyzing trace with hash -1802625568, now seen corresponding path program 1 times [2025-03-04 16:22:14,151 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:14,151 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092523515] [2025-03-04 16:22:14,151 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:14,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:14,159 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:14,164 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:14,164 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:14,164 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:14,200 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:14,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:14,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092523515] [2025-03-04 16:22:14,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092523515] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:14,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:14,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:14,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1837129917] [2025-03-04 16:22:14,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:14,201 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:14,201 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:14,202 INFO L85 PathProgramCache]: Analyzing trace with hash -2055511382, now seen corresponding path program 1 times [2025-03-04 16:22:14,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:14,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [223406629] [2025-03-04 16:22:14,202 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:14,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:14,210 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:14,213 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:14,213 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:14,213 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:14,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:14,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:14,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [223406629] [2025-03-04 16:22:14,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [223406629] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:14,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:14,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:14,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1012516273] [2025-03-04 16:22:14,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:14,237 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:14,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:14,237 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:22:14,237 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:22:14,238 INFO L87 Difference]: Start difference. First operand 152646 states and 218566 transitions. cyclomatic complexity: 66048 Second operand has 4 states, 4 states have (on average 37.0) internal successors, (148), 3 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:15,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:15,776 INFO L93 Difference]: Finished difference Result 370889 states and 527815 transitions. [2025-03-04 16:22:15,777 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 370889 states and 527815 transitions. [2025-03-04 16:22:17,234 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 368964 [2025-03-04 16:22:18,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 370889 states to 370889 states and 527815 transitions. [2025-03-04 16:22:18,167 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 370889 [2025-03-04 16:22:18,363 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 370889 [2025-03-04 16:22:18,364 INFO L73 IsDeterministic]: Start isDeterministic. Operand 370889 states and 527815 transitions. [2025-03-04 16:22:18,587 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:18,587 INFO L218 hiAutomatonCegarLoop]: Abstraction has 370889 states and 527815 transitions. [2025-03-04 16:22:18,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 370889 states and 527815 transitions. [2025-03-04 16:22:21,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 370889 to 297397. [2025-03-04 16:22:21,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 297397 states, 297397 states have (on average 1.426036577369644) internal successors, (424099), 297396 states have internal predecessors, (424099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:22,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297397 states to 297397 states and 424099 transitions. [2025-03-04 16:22:22,370 INFO L240 hiAutomatonCegarLoop]: Abstraction has 297397 states and 424099 transitions. [2025-03-04 16:22:22,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:22:22,371 INFO L432 stractBuchiCegarLoop]: Abstraction has 297397 states and 424099 transitions. [2025-03-04 16:22:22,371 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-04 16:22:22,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 297397 states and 424099 transitions. [2025-03-04 16:22:23,499 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 296240 [2025-03-04 16:22:23,500 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:23,500 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:23,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:23,501 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:23,501 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume 1 == ~t5_pc~0;" "assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:23,502 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume !(1 == ~t7_pc~0);" "is_transmit7_triggered_~__retres1~7#1 := 0;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume !(1 == ~t8_pc~0);" "is_transmit8_triggered_~__retres1~8#1 := 0;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:23,502 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:23,502 INFO L85 PathProgramCache]: Analyzing trace with hash 1680850749, now seen corresponding path program 1 times [2025-03-04 16:22:23,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:23,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [780174599] [2025-03-04 16:22:23,502 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:23,503 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:23,509 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:23,513 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:23,513 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:23,513 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:23,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:23,578 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:23,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [780174599] [2025-03-04 16:22:23,579 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [780174599] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:23,579 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:23,579 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:23,579 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248454589] [2025-03-04 16:22:23,579 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:23,579 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:23,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:23,579 INFO L85 PathProgramCache]: Analyzing trace with hash -759081994, now seen corresponding path program 1 times [2025-03-04 16:22:23,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:23,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [290569339] [2025-03-04 16:22:23,579 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:23,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:23,597 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:23,604 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:23,604 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:23,604 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:23,627 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:23,627 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:23,627 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [290569339] [2025-03-04 16:22:23,627 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [290569339] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:23,627 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:23,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:23,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1702870813] [2025-03-04 16:22:23,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:23,628 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:23,628 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:23,628 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:23,628 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:23,631 INFO L87 Difference]: Start difference. First operand 297397 states and 424099 transitions. cyclomatic complexity: 126830 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:25,488 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:22:25,488 INFO L93 Difference]: Finished difference Result 568708 states and 808176 transitions. [2025-03-04 16:22:25,488 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 568708 states and 808176 transitions. [2025-03-04 16:22:28,238 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 566144 [2025-03-04 16:22:29,864 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 568708 states to 568708 states and 808176 transitions. [2025-03-04 16:22:29,864 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 568708 [2025-03-04 16:22:30,112 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 568708 [2025-03-04 16:22:30,113 INFO L73 IsDeterministic]: Start isDeterministic. Operand 568708 states and 808176 transitions. [2025-03-04 16:22:30,341 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:22:30,341 INFO L218 hiAutomatonCegarLoop]: Abstraction has 568708 states and 808176 transitions. [2025-03-04 16:22:30,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 568708 states and 808176 transitions. [2025-03-04 16:22:35,098 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 568708 to 567940. [2025-03-04 16:22:35,482 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 567940 states, 567940 states have (on average 1.4216431313166884) internal successors, (807408), 567939 states have internal predecessors, (807408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:22:37,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 567940 states to 567940 states and 807408 transitions. [2025-03-04 16:22:37,293 INFO L240 hiAutomatonCegarLoop]: Abstraction has 567940 states and 807408 transitions. [2025-03-04 16:22:37,293 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2025-03-04 16:22:37,293 INFO L432 stractBuchiCegarLoop]: Abstraction has 567940 states and 807408 transitions. [2025-03-04 16:22:37,293 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-04 16:22:37,293 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 567940 states and 807408 transitions. [2025-03-04 16:22:38,676 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 565376 [2025-03-04 16:22:38,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:22:38,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:22:38,678 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:38,678 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:22:38,678 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~14#1;havoc main_~__retres1~14#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;" "assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret32#1, start_simulation_#t~ret33#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true;" "assume 1 == ~m_i~0;~m_st~0 := 0;" "assume 1 == ~t1_i~0;~t1_st~0 := 0;" "assume 1 == ~t2_i~0;~t2_st~0 := 0;" "assume 1 == ~t3_i~0;~t3_st~0 := 0;" "assume 1 == ~t4_i~0;~t4_st~0 := 0;" "assume 1 == ~t5_i~0;~t5_st~0 := 0;" "assume 1 == ~t6_i~0;~t6_st~0 := 0;" "assume 1 == ~t7_i~0;~t7_st~0 := 0;" "assume 1 == ~t8_i~0;~t8_st~0 := 0;" "assume 1 == ~t9_i~0;~t9_st~0 := 0;" "assume 1 == ~t10_i~0;~t10_st~0 := 0;" "assume 1 == ~t11_i~0;~t11_st~0 := 0;" "assume 1 == ~t12_i~0;~t12_st~0 := 0;" "assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true;" "assume !(0 == ~M_E~0);" "assume !(0 == ~T1_E~0);" "assume !(0 == ~T2_E~0);" "assume !(0 == ~T3_E~0);" "assume !(0 == ~T4_E~0);" "assume !(0 == ~T5_E~0);" "assume !(0 == ~T6_E~0);" "assume !(0 == ~T7_E~0);" "assume !(0 == ~T8_E~0);" "assume !(0 == ~T9_E~0);" "assume !(0 == ~T10_E~0);" "assume !(0 == ~T11_E~0);" "assume !(0 == ~T12_E~0);" "assume !(0 == ~E_1~0);" "assume !(0 == ~E_2~0);" "assume !(0 == ~E_3~0);" "assume !(0 == ~E_4~0);" "assume !(0 == ~E_5~0);" "assume !(0 == ~E_6~0);" "assume !(0 == ~E_7~0);" "assume !(0 == ~E_8~0);" "assume !(0 == ~E_9~0);" "assume !(0 == ~E_10~0);" "assume !(0 == ~E_11~0);" "assume !(0 == ~E_12~0);" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume !(0 != activate_threads_~tmp~1#1);" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume !(0 != activate_threads_~tmp___0~0#1);" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume !(0 != activate_threads_~tmp___1~0#1);" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume !(0 != activate_threads_~tmp___3~0#1);" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume !(0 != activate_threads_~tmp___4~0#1);" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume !(0 != activate_threads_~tmp___5~0#1);" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume !(0 != activate_threads_~tmp___7~0#1);" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume !(0 != activate_threads_~tmp___8~0#1);" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume !(0 != activate_threads_~tmp___9~0#1);" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume !(0 != activate_threads_~tmp___11~0#1);" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume 1 == ~M_E~0;~M_E~0 := 2;" "assume !(1 == ~T1_E~0);" "assume !(1 == ~T2_E~0);" "assume !(1 == ~T3_E~0);" "assume !(1 == ~T4_E~0);" "assume !(1 == ~T5_E~0);" "assume !(1 == ~T6_E~0);" "assume !(1 == ~T7_E~0);" "assume !(1 == ~T8_E~0);" "assume !(1 == ~T9_E~0);" "assume !(1 == ~T10_E~0);" "assume !(1 == ~T11_E~0);" "assume !(1 == ~T12_E~0);" "assume !(1 == ~E_1~0);" "assume !(1 == ~E_2~0);" "assume !(1 == ~E_3~0);" "assume !(1 == ~E_4~0);" "assume !(1 == ~E_5~0);" "assume !(1 == ~E_6~0);" "assume !(1 == ~E_7~0);" "assume !(1 == ~E_8~0);" "assume !(1 == ~E_9~0);" "assume !(1 == ~E_10~0);" "assume !(1 == ~E_11~0);" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;" [2025-03-04 16:22:38,678 INFO L754 eck$LassoCheckResult]: Loop: "assume true;" "start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1;" "assume true;" "assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1;" "assume !(0 != eval_~tmp~0#1);" "havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_13~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true;" "assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true;" "assume 0 == ~M_E~0;~M_E~0 := 1;" "assume !(0 == ~T1_E~0);" "assume 0 == ~T2_E~0;~T2_E~0 := 1;" "assume 0 == ~T3_E~0;~T3_E~0 := 1;" "assume 0 == ~T4_E~0;~T4_E~0 := 1;" "assume 0 == ~T5_E~0;~T5_E~0 := 1;" "assume 0 == ~T6_E~0;~T6_E~0 := 1;" "assume 0 == ~T7_E~0;~T7_E~0 := 1;" "assume 0 == ~T8_E~0;~T8_E~0 := 1;" "assume !(0 == ~T9_E~0);" "assume 0 == ~T10_E~0;~T10_E~0 := 1;" "assume 0 == ~T11_E~0;~T11_E~0 := 1;" "assume 0 == ~T12_E~0;~T12_E~0 := 1;" "assume 0 == ~E_1~0;~E_1~0 := 1;" "assume 0 == ~E_2~0;~E_2~0 := 1;" "assume 0 == ~E_3~0;~E_3~0 := 1;" "assume 0 == ~E_4~0;~E_4~0 := 1;" "assume !(0 == ~E_5~0);" "assume 0 == ~E_6~0;~E_6~0 := 1;" "assume 0 == ~E_7~0;~E_7~0 := 1;" "assume 0 == ~E_8~0;~E_8~0 := 1;" "assume 0 == ~E_9~0;~E_9~0 := 1;" "assume 0 == ~E_10~0;~E_10~0 := 1;" "assume 0 == ~E_11~0;~E_11~0 := 1;" "assume 0 == ~E_12~0;~E_12~0 := 1;" "assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1;" "assume !(1 == ~m_pc~0);" "is_master_triggered_~__retres1~0#1 := 0;" "is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1;" "activate_threads_#t~ret18#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1;" "assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0;" "assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1;" "assume !(1 == ~t1_pc~0);" "is_transmit1_triggered_~__retres1~1#1 := 0;" "is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1;" "activate_threads_#t~ret19#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1;" "assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0;" "assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1;" "assume !(1 == ~t2_pc~0);" "is_transmit2_triggered_~__retres1~2#1 := 0;" "is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1;" "activate_threads_#t~ret20#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1;" "assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0;" "assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1;" "assume !(1 == ~t3_pc~0);" "is_transmit3_triggered_~__retres1~3#1 := 0;" "is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1;" "activate_threads_#t~ret21#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1;" "assume !(0 != activate_threads_~tmp___2~0#1);" "assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1;" "assume !(1 == ~t4_pc~0);" "is_transmit4_triggered_~__retres1~4#1 := 0;" "is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1;" "activate_threads_#t~ret22#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1;" "assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0;" "assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1;" "assume !(1 == ~t5_pc~0);" "is_transmit5_triggered_~__retres1~5#1 := 0;" "is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1;" "activate_threads_#t~ret23#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1;" "assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0;" "assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1;" "assume 1 == ~t6_pc~0;" "assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1;" "is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1;" "activate_threads_#t~ret24#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1;" "assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0;" "assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1;" "assume 1 == ~t7_pc~0;" "assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1;" "is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1;" "activate_threads_#t~ret25#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1;" "assume !(0 != activate_threads_~tmp___6~0#1);" "assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1;" "assume 1 == ~t8_pc~0;" "assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1;" "is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1;" "activate_threads_#t~ret26#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1;" "assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0;" "assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1;" "assume 1 == ~t9_pc~0;" "assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1;" "is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1;" "activate_threads_#t~ret27#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1;" "assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0;" "assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1;" "assume 1 == ~t10_pc~0;" "assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1;" "is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1;" "activate_threads_#t~ret28#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1;" "assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0;" "assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1;" "assume 1 == ~t11_pc~0;" "assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1;" "is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1;" "activate_threads_#t~ret29#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1;" "assume !(0 != activate_threads_~tmp___10~0#1);" "assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1;" "assume 1 == ~t12_pc~0;" "assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1;" "is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1;" "activate_threads_#t~ret30#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1;" "assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0;" "havoc activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true;" "assume !(1 == ~M_E~0);" "assume 1 == ~T1_E~0;~T1_E~0 := 2;" "assume 1 == ~T2_E~0;~T2_E~0 := 2;" "assume 1 == ~T3_E~0;~T3_E~0 := 2;" "assume 1 == ~T4_E~0;~T4_E~0 := 2;" "assume 1 == ~T5_E~0;~T5_E~0 := 2;" "assume 1 == ~T6_E~0;~T6_E~0 := 2;" "assume 1 == ~T7_E~0;~T7_E~0 := 2;" "assume !(1 == ~T8_E~0);" "assume 1 == ~T9_E~0;~T9_E~0 := 2;" "assume 1 == ~T10_E~0;~T10_E~0 := 2;" "assume 1 == ~T11_E~0;~T11_E~0 := 2;" "assume 1 == ~T12_E~0;~T12_E~0 := 2;" "assume 1 == ~E_1~0;~E_1~0 := 2;" "assume 1 == ~E_2~0;~E_2~0 := 2;" "assume 1 == ~E_3~0;~E_3~0 := 2;" "assume !(1 == ~E_4~0);" "assume 1 == ~E_5~0;~E_5~0 := 2;" "assume 1 == ~E_6~0;~E_6~0 := 2;" "assume 1 == ~E_7~0;~E_7~0 := 2;" "assume 1 == ~E_8~0;~E_8~0 := 2;" "assume 1 == ~E_9~0;~E_9~0 := 2;" "assume 1 == ~E_10~0;~E_10~0 := 2;" "assume 1 == ~E_11~0;~E_11~0 := 2;" "assume !(1 == ~E_12~0);" "assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "start_simulation_#t~ret32#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret32#1;havoc start_simulation_#t~ret32#1;" "assume !(0 == start_simulation_~tmp~3#1);" "assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;havoc exists_runnable_thread_~__retres1~13#1;" "assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~13#1 := 1;" "exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~13#1;" "stop_simulation_#t~ret31#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~13#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret31#1;havoc stop_simulation_#t~ret31#1;" "assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0;" "stop_simulation_#res#1 := stop_simulation_~__retres2~0#1;" "start_simulation_#t~ret33#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret31#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret33#1;havoc start_simulation_#t~ret33#1;" "assume !(0 != start_simulation_~tmp___0~1#1);" [2025-03-04 16:22:38,679 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:38,679 INFO L85 PathProgramCache]: Analyzing trace with hash -259462566, now seen corresponding path program 1 times [2025-03-04 16:22:38,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:38,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [646857743] [2025-03-04 16:22:38,679 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:38,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:38,684 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 148 statements into 1 equivalence classes. [2025-03-04 16:22:38,686 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 148 of 148 statements. [2025-03-04 16:22:38,686 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:38,686 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:38,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:38,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:38,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [646857743] [2025-03-04 16:22:38,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [646857743] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:38,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:38,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:22:38,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [952952056] [2025-03-04 16:22:38,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:38,711 INFO L757 eck$LassoCheckResult]: stem already infeasible [2025-03-04 16:22:38,712 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:22:38,712 INFO L85 PathProgramCache]: Analyzing trace with hash 1635591164, now seen corresponding path program 1 times [2025-03-04 16:22:38,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:22:38,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [305592411] [2025-03-04 16:22:38,712 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:22:38,712 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:22:38,717 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 152 statements into 1 equivalence classes. [2025-03-04 16:22:38,720 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 152 of 152 statements. [2025-03-04 16:22:38,720 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:22:38,720 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:22:38,735 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:22:38,735 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:22:38,735 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [305592411] [2025-03-04 16:22:38,735 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [305592411] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:22:38,735 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:22:38,735 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2025-03-04 16:22:38,735 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [432215871] [2025-03-04 16:22:38,735 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:22:38,736 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:22:38,736 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:22:38,736 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2025-03-04 16:22:38,736 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2025-03-04 16:22:38,736 INFO L87 Difference]: Start difference. First operand 567940 states and 807408 transitions. cyclomatic complexity: 239724 Second operand has 3 states, 3 states have (on average 49.333333333333336) internal successors, (148), 2 states have internal predecessors, (148), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)