./Ultimate.py --spec ../sv-benchmarks/c/properties/termination.prp --file ../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 798a7b37 Calling Ultimate with: /root/.sdkman/candidates/java/21.0.5-tem/bin/java -Dosgi.configuration.area=/storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/config -Xmx15G -Xms4m -jar /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/plugins/org.eclipse.equinox.launcher_1.6.800.v20240513-1750.jar -data @noDefault -ultimatedata /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data -tc /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/AutomizerTermination.xml -i ../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i -s /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 --- Real Ultimate output --- This is Ultimate 0.3.0-?-798a7b3-m [2025-03-04 16:37:43,839 INFO L188 SettingsManager]: Resetting all preferences to default values... [2025-03-04 16:37:43,884 INFO L114 SettingsManager]: Loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/config/svcomp-Termination-32bit-Automizer_Default.epf [2025-03-04 16:37:43,887 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2025-03-04 16:37:43,888 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2025-03-04 16:37:43,888 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder.Remove goto edges from RCFG [2025-03-04 16:37:43,909 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2025-03-04 16:37:43,910 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2025-03-04 16:37:43,910 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2025-03-04 16:37:43,910 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2025-03-04 16:37:43,911 INFO L153 SettingsManager]: * Use memory slicer=true [2025-03-04 16:37:43,911 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2025-03-04 16:37:43,911 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2025-03-04 16:37:43,911 INFO L153 SettingsManager]: * Use SBE=true [2025-03-04 16:37:43,912 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Use old map elimination=false [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2025-03-04 16:37:43,912 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * sizeof long=4 [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * sizeof POINTER=4 [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2025-03-04 16:37:43,912 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * sizeof long double=12 [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Behaviour of calls to undefined functions=OVERAPPROXIMATE_BEHAVIOUR [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Use constant arrays=true [2025-03-04 16:37:43,913 INFO L151 SettingsManager]: Preferences of IcfgBuilder differ from their defaults: [2025-03-04 16:37:43,913 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2025-03-04 16:37:43,914 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2025-03-04 16:37:43,914 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2025-03-04 16:37:43,914 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2025-03-04 16:37:43,914 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> e4ea247b245ebcaf5e735452e89c4110c7b9dc9b43836e98484a894783fc3462 [2025-03-04 16:37:44,097 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2025-03-04 16:37:44,106 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2025-03-04 16:37:44,107 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2025-03-04 16:37:44,109 INFO L270 PluginConnector]: Initializing CDTParser... [2025-03-04 16:37:44,109 INFO L274 PluginConnector]: CDTParser initialized [2025-03-04 16:37:44,110 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2025-03-04 16:37:45,259 INFO L533 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7ea81da2d/f310913bcaef4b12a859405799ff670b/FLAG594261f63 [2025-03-04 16:37:45,568 INFO L384 CDTParser]: Found 1 translation units. [2025-03-04 16:37:45,571 INFO L180 CDTParser]: Scanning /storage/repos/ultimate/releaseScripts/default/sv-benchmarks/c/uthash-2.0.2/uthash_FNV_test6-2.i [2025-03-04 16:37:45,590 INFO L427 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7ea81da2d/f310913bcaef4b12a859405799ff670b/FLAG594261f63 [2025-03-04 16:37:45,809 INFO L435 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/7ea81da2d/f310913bcaef4b12a859405799ff670b [2025-03-04 16:37:45,811 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2025-03-04 16:37:45,811 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2025-03-04 16:37:45,812 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2025-03-04 16:37:45,812 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2025-03-04 16:37:45,815 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2025-03-04 16:37:45,815 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:37:45" (1/1) ... [2025-03-04 16:37:45,816 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3cd1763d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:45, skipping insertion in model container [2025-03-04 16:37:45,816 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.03 04:37:45" (1/1) ... [2025-03-04 16:37:45,840 INFO L175 MainTranslator]: Built tables and reachable declarations [2025-03-04 16:37:46,189 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:37:46,199 INFO L200 MainTranslator]: Completed pre-run [2025-03-04 16:37:46,279 INFO L210 PostProcessor]: Analyzing one entry point: main [2025-03-04 16:37:46,318 INFO L204 MainTranslator]: Completed translation [2025-03-04 16:37:46,319 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46 WrapperNode [2025-03-04 16:37:46,319 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2025-03-04 16:37:46,320 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2025-03-04 16:37:46,320 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2025-03-04 16:37:46,320 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2025-03-04 16:37:46,325 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,341 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,387 INFO L138 Inliner]: procedures = 282, calls = 353, calls flagged for inlining = 25, calls inlined = 37, statements flattened = 1756 [2025-03-04 16:37:46,387 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2025-03-04 16:37:46,388 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2025-03-04 16:37:46,388 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2025-03-04 16:37:46,388 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2025-03-04 16:37:46,393 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,394 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,406 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,486 INFO L175 MemorySlicer]: Split 326 memory accesses to 4 slices as follows [271, 2, 19, 34]. 83 percent of accesses are in the largest equivalence class. The 12 initializations are split as follows [0, 2, 10, 0]. The 65 writes are split as follows [58, 0, 3, 4]. [2025-03-04 16:37:46,489 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,489 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,514 INFO L184 PluginConnector]: Executing the observer ReplaceArrayAssignments from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,517 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,519 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,522 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,533 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2025-03-04 16:37:46,534 INFO L112 PluginConnector]: ------------------------IcfgBuilder---------------------------- [2025-03-04 16:37:46,534 INFO L270 PluginConnector]: Initializing IcfgBuilder... [2025-03-04 16:37:46,534 INFO L274 PluginConnector]: IcfgBuilder initialized [2025-03-04 16:37:46,534 INFO L184 PluginConnector]: Executing the observer IcfgBuilderObserver from plugin IcfgBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (1/1) ... [2025-03-04 16:37:46,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2025-03-04 16:37:46,550 INFO L189 MonitoredProcess]: No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 [2025-03-04 16:37:46,563 INFO L229 MonitoredProcess]: Starting monitored process 1 with /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2025-03-04 16:37:46,565 INFO L327 MonitoredProcess]: [MP /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2025-03-04 16:37:46,604 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#0 [2025-03-04 16:37:46,604 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#1 [2025-03-04 16:37:46,604 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#2 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset#3 [2025-03-04 16:37:46,605 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#0 [2025-03-04 16:37:46,605 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#1 [2025-03-04 16:37:46,605 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#2 [2025-03-04 16:37:46,605 INFO L138 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset#3 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnStack [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#0 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#1 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#2 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~$Pointer$#3 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#0 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#1 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#2 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure read~int#3 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#0 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#1 [2025-03-04 16:37:46,605 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#2 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~int#3 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocOnHeap [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#0 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#1 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#2 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~$Pointer$#3 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#1 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#2 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#3 [2025-03-04 16:37:46,606 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2025-03-04 16:37:46,606 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2025-03-04 16:37:46,794 INFO L256 CfgBuilder]: Building ICFG [2025-03-04 16:37:46,796 INFO L286 CfgBuilder]: Building CFG for each procedure with an implementation [2025-03-04 16:37:47,928 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L969: havoc alt_memcmp_#t~nondet36#1; [2025-03-04 16:37:47,929 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L979: havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset; [2025-03-04 16:37:47,929 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L987: call ULTIMATE.dealloc(main_~#i~0#1.base, main_~#i~0#1.offset);havoc main_~#i~0#1.base, main_~#i~0#1.offset; [2025-03-04 16:37:47,929 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L955: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-04 16:37:47,929 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-3: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-04 16:37:47,929 INFO L1325 $ProcedureCfgBuilder]: dead code at ProgramPoint L955-6: havoc alt_malloc_#t~malloc32#1.base, alt_malloc_#t~malloc32#1.offset; [2025-03-04 16:37:48,028 INFO L? ?]: Removed 486 outVars from TransFormulas that were not future-live. [2025-03-04 16:37:48,028 INFO L307 CfgBuilder]: Performing block encoding [2025-03-04 16:37:48,066 INFO L331 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2025-03-04 16:37:48,068 INFO L336 CfgBuilder]: Removed 1 assume(true) statements. [2025-03-04 16:37:48,068 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:37:48 BoogieIcfgContainer [2025-03-04 16:37:48,068 INFO L131 PluginConnector]: ------------------------ END IcfgBuilder---------------------------- [2025-03-04 16:37:48,069 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2025-03-04 16:37:48,069 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2025-03-04 16:37:48,073 INFO L274 PluginConnector]: BuchiAutomizer initialized [2025-03-04 16:37:48,074 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:37:48,074 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 04.03 04:37:45" (1/3) ... [2025-03-04 16:37:48,074 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552038c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:37:48, skipping insertion in model container [2025-03-04 16:37:48,075 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:37:48,075 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.03 04:37:46" (2/3) ... [2025-03-04 16:37:48,075 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@552038c6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 04.03 04:37:48, skipping insertion in model container [2025-03-04 16:37:48,076 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2025-03-04 16:37:48,076 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.icfgbuilder CFG 04.03 04:37:48" (3/3) ... [2025-03-04 16:37:48,076 INFO L363 chiAutomizerObserver]: Analyzing ICFG uthash_FNV_test6-2.i [2025-03-04 16:37:48,118 INFO L306 stractBuchiCegarLoop]: Interprodecural is true [2025-03-04 16:37:48,119 INFO L307 stractBuchiCegarLoop]: Hoare is None [2025-03-04 16:37:48,119 INFO L308 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2025-03-04 16:37:48,119 INFO L309 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2025-03-04 16:37:48,119 INFO L310 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2025-03-04 16:37:48,119 INFO L311 stractBuchiCegarLoop]: Difference is false [2025-03-04 16:37:48,119 INFO L312 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2025-03-04 16:37:48,119 INFO L316 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2025-03-04 16:37:48,124 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 492 states, 487 states have (on average 1.5872689938398357) internal successors, (773), 487 states have internal predecessors, (773), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:48,150 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 467 [2025-03-04 16:37:48,151 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:48,151 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:48,157 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:48,157 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:48,157 INFO L338 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2025-03-04 16:37:48,159 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 492 states, 487 states have (on average 1.5872689938398357) internal successors, (773), 487 states have internal predecessors, (773), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:48,170 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 467 [2025-03-04 16:37:48,170 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:48,170 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:48,170 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:48,170 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:48,174 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:48,174 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume main_~user~0#1.base == 0 && main_~user~0#1.offset == 0;assume false;" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume !true;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:48,177 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:48,177 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 1 times [2025-03-04 16:37:48,182 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:48,182 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [197501238] [2025-03-04 16:37:48,182 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:48,182 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:48,235 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:48,249 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:48,249 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:48,249 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:48,249 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:48,259 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:48,272 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:48,272 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:48,272 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:48,295 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:48,296 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:48,296 INFO L85 PathProgramCache]: Analyzing trace with hash -743011733, now seen corresponding path program 1 times [2025-03-04 16:37:48,296 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:48,297 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [772279067] [2025-03-04 16:37:48,297 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:48,297 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:48,313 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 7 statements into 1 equivalence classes. [2025-03-04 16:37:48,319 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 7 of 7 statements. [2025-03-04 16:37:48,319 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:48,320 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:48,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:48,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:48,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [772279067] [2025-03-04 16:37:48,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [772279067] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:48,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:48,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2025-03-04 16:37:48,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1612460850] [2025-03-04 16:37:48,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:48,361 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:48,361 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:48,376 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2025-03-04 16:37:48,377 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2025-03-04 16:37:48,379 INFO L87 Difference]: Start difference. First operand has 492 states, 487 states have (on average 1.5872689938398357) internal successors, (773), 487 states have internal predecessors, (773), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) Second operand has 2 states, 2 states have (on average 3.5) internal successors, (7), 2 states have internal predecessors, (7), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:48,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:48,462 INFO L93 Difference]: Finished difference Result 474 states and 663 transitions. [2025-03-04 16:37:48,463 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 474 states and 663 transitions. [2025-03-04 16:37:48,470 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 441 [2025-03-04 16:37:48,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 474 states to 458 states and 647 transitions. [2025-03-04 16:37:48,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 458 [2025-03-04 16:37:48,481 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 458 [2025-03-04 16:37:48,481 INFO L73 IsDeterministic]: Start isDeterministic. Operand 458 states and 647 transitions. [2025-03-04 16:37:48,485 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:48,487 INFO L218 hiAutomatonCegarLoop]: Abstraction has 458 states and 647 transitions. [2025-03-04 16:37:48,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states and 647 transitions. [2025-03-04 16:37:48,518 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 458. [2025-03-04 16:37:48,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 458 states, 454 states have (on average 1.4118942731277533) internal successors, (641), 453 states have internal predecessors, (641), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:48,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 647 transitions. [2025-03-04 16:37:48,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 458 states and 647 transitions. [2025-03-04 16:37:48,522 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2025-03-04 16:37:48,524 INFO L432 stractBuchiCegarLoop]: Abstraction has 458 states and 647 transitions. [2025-03-04 16:37:48,524 INFO L338 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2025-03-04 16:37:48,524 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 458 states and 647 transitions. [2025-03-04 16:37:48,525 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 441 [2025-03-04 16:37:48,526 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:48,526 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:48,526 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:48,526 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:48,527 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:48,528 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem67#1 := read~int#0(main_~_hj_key~0#1.base, 10 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 16777216 * (main_#t~mem67#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem68#1 := read~int#0(main_~_hj_key~0#1.base, 9 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 65536 * (main_#t~mem68#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem69#1 := read~int#0(main_~_hj_key~0#1.base, 8 + main_~_hj_key~0#1.offset, 1);main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 + 256 * (main_#t~mem69#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem70#1 := read~int#0(main_~_hj_key~0#1.base, 7 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 16777216 * (main_#t~mem70#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem71#1 := read~int#0(main_~_hj_key~0#1.base, 6 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 65536 * (main_#t~mem71#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem72#1 := read~int#0(main_~_hj_key~0#1.base, 5 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + 256 * (main_#t~mem72#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem73#1 := read~int#0(main_~_hj_key~0#1.base, 4 + main_~_hj_key~0#1.offset, 1);main_~_hj_j~0#1 := main_~_hj_j~0#1 + (if main_#t~mem73#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem73#1 % 256 % 4294967296 else main_#t~mem73#1 % 256 % 4294967296 - 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:48,528 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:48,528 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 2 times [2025-03-04 16:37:48,528 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:48,528 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102380784] [2025-03-04 16:37:48,528 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:37:48,528 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:48,540 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:48,549 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:48,551 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:37:48,552 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:48,552 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:48,560 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:48,568 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:48,568 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:48,568 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:48,577 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:48,579 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:48,579 INFO L85 PathProgramCache]: Analyzing trace with hash -979910835, now seen corresponding path program 1 times [2025-03-04 16:37:48,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:48,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [268048721] [2025-03-04 16:37:48,579 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:48,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:48,641 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-04 16:37:48,657 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-04 16:37:48,660 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:48,660 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:48,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:48,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:48,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [268048721] [2025-03-04 16:37:48,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [268048721] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:48,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:48,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:37:48,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1432360342] [2025-03-04 16:37:48,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:48,948 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:48,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:48,948 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:37:48,949 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:37:48,950 INFO L87 Difference]: Start difference. First operand 458 states and 647 transitions. cyclomatic complexity: 193 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:49,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:49,122 INFO L93 Difference]: Finished difference Result 461 states and 643 transitions. [2025-03-04 16:37:49,122 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 461 states and 643 transitions. [2025-03-04 16:37:49,125 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 444 [2025-03-04 16:37:49,129 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 461 states to 461 states and 643 transitions. [2025-03-04 16:37:49,130 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 461 [2025-03-04 16:37:49,131 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461 [2025-03-04 16:37:49,131 INFO L73 IsDeterministic]: Start isDeterministic. Operand 461 states and 643 transitions. [2025-03-04 16:37:49,133 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:49,134 INFO L218 hiAutomatonCegarLoop]: Abstraction has 461 states and 643 transitions. [2025-03-04 16:37:49,135 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states and 643 transitions. [2025-03-04 16:37:49,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 458. [2025-03-04 16:37:49,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 458 states, 454 states have (on average 1.39647577092511) internal successors, (634), 453 states have internal predecessors, (634), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:49,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 640 transitions. [2025-03-04 16:37:49,150 INFO L240 hiAutomatonCegarLoop]: Abstraction has 458 states and 640 transitions. [2025-03-04 16:37:49,150 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:37:49,151 INFO L432 stractBuchiCegarLoop]: Abstraction has 458 states and 640 transitions. [2025-03-04 16:37:49,151 INFO L338 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2025-03-04 16:37:49,151 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 458 states and 640 transitions. [2025-03-04 16:37:49,152 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 441 [2025-03-04 16:37:49,152 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:49,152 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:49,153 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:49,153 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:49,153 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:49,154 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:49,154 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:49,154 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 3 times [2025-03-04 16:37:49,154 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:49,155 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1904696626] [2025-03-04 16:37:49,155 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:37:49,155 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:49,163 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:49,168 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:49,168 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:37:49,168 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:49,168 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:49,172 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:49,176 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:49,176 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:49,176 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:49,184 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:49,185 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:49,185 INFO L85 PathProgramCache]: Analyzing trace with hash -54787372, now seen corresponding path program 1 times [2025-03-04 16:37:49,185 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:49,185 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534324076] [2025-03-04 16:37:49,185 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:49,185 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:49,223 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-04 16:37:49,234 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-04 16:37:49,235 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:49,235 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:49,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:49,401 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:49,401 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [534324076] [2025-03-04 16:37:49,401 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [534324076] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:49,401 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:49,401 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:37:49,401 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1951453592] [2025-03-04 16:37:49,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:49,401 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:49,402 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:49,402 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:37:49,402 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:37:49,403 INFO L87 Difference]: Start difference. First operand 458 states and 640 transitions. cyclomatic complexity: 186 Second operand has 4 states, 4 states have (on average 18.75) internal successors, (75), 4 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:49,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:49,538 INFO L93 Difference]: Finished difference Result 410 states and 560 transitions. [2025-03-04 16:37:49,538 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 410 states and 560 transitions. [2025-03-04 16:37:49,541 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 393 [2025-03-04 16:37:49,543 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 410 states to 410 states and 560 transitions. [2025-03-04 16:37:49,543 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 410 [2025-03-04 16:37:49,544 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 410 [2025-03-04 16:37:49,544 INFO L73 IsDeterministic]: Start isDeterministic. Operand 410 states and 560 transitions. [2025-03-04 16:37:49,544 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:49,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 410 states and 560 transitions. [2025-03-04 16:37:49,546 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 410 states and 560 transitions. [2025-03-04 16:37:49,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 410 to 410. [2025-03-04 16:37:49,552 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 410 states, 406 states have (on average 1.3645320197044335) internal successors, (554), 405 states have internal predecessors, (554), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:49,553 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 410 states to 410 states and 560 transitions. [2025-03-04 16:37:49,554 INFO L240 hiAutomatonCegarLoop]: Abstraction has 410 states and 560 transitions. [2025-03-04 16:37:49,555 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2025-03-04 16:37:49,555 INFO L432 stractBuchiCegarLoop]: Abstraction has 410 states and 560 transitions. [2025-03-04 16:37:49,556 INFO L338 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2025-03-04 16:37:49,556 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 410 states and 560 transitions. [2025-03-04 16:37:49,557 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 393 [2025-03-04 16:37:49,558 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:49,558 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:49,559 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:49,559 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:49,559 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:49,561 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:49,562 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:49,562 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 4 times [2025-03-04 16:37:49,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:49,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1412523688] [2025-03-04 16:37:49,562 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:37:49,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:49,573 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:37:49,577 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:49,578 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:37:49,578 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:49,578 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:49,585 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:49,591 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:49,591 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:49,591 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:49,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:49,601 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:49,602 INFO L85 PathProgramCache]: Analyzing trace with hash 1870745939, now seen corresponding path program 1 times [2025-03-04 16:37:49,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:49,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1930673417] [2025-03-04 16:37:49,602 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:49,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:49,640 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 75 statements into 1 equivalence classes. [2025-03-04 16:37:49,786 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 75 of 75 statements. [2025-03-04 16:37:49,790 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:49,790 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:50,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:50,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:50,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1930673417] [2025-03-04 16:37:50,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1930673417] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:50,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:50,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-04 16:37:50,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1278798558] [2025-03-04 16:37:50,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:50,110 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:50,110 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:50,111 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-04 16:37:50,111 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2025-03-04 16:37:50,111 INFO L87 Difference]: Start difference. First operand 410 states and 560 transitions. cyclomatic complexity: 154 Second operand has 6 states, 6 states have (on average 12.5) internal successors, (75), 6 states have internal predecessors, (75), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:50,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:50,492 INFO L93 Difference]: Finished difference Result 415 states and 567 transitions. [2025-03-04 16:37:50,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 415 states and 567 transitions. [2025-03-04 16:37:50,494 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 398 [2025-03-04 16:37:50,496 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 415 states to 415 states and 567 transitions. [2025-03-04 16:37:50,496 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 415 [2025-03-04 16:37:50,496 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 415 [2025-03-04 16:37:50,496 INFO L73 IsDeterministic]: Start isDeterministic. Operand 415 states and 567 transitions. [2025-03-04 16:37:50,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:50,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 415 states and 567 transitions. [2025-03-04 16:37:50,497 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 415 states and 567 transitions. [2025-03-04 16:37:50,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 415 to 412. [2025-03-04 16:37:50,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 412 states, 408 states have (on average 1.3627450980392157) internal successors, (556), 407 states have internal predecessors, (556), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:50,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 412 states to 412 states and 562 transitions. [2025-03-04 16:37:50,502 INFO L240 hiAutomatonCegarLoop]: Abstraction has 412 states and 562 transitions. [2025-03-04 16:37:50,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 16:37:50,503 INFO L432 stractBuchiCegarLoop]: Abstraction has 412 states and 562 transitions. [2025-03-04 16:37:50,503 INFO L338 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2025-03-04 16:37:50,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 412 states and 562 transitions. [2025-03-04 16:37:50,504 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 395 [2025-03-04 16:37:50,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:50,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:50,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:50,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:50,505 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:50,505 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:50,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:50,505 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 5 times [2025-03-04 16:37:50,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:50,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1672673812] [2025-03-04 16:37:50,506 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:37:50,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:50,512 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:50,514 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:50,515 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:37:50,515 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:50,515 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:50,517 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:50,519 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:50,519 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:50,519 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:50,523 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:50,523 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:50,523 INFO L85 PathProgramCache]: Analyzing trace with hash -1093157932, now seen corresponding path program 1 times [2025-03-04 16:37:50,523 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:50,523 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818002932] [2025-03-04 16:37:50,523 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:50,524 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:50,549 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-04 16:37:50,654 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 16:37:50,654 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:50,654 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:50,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:50,909 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:50,909 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818002932] [2025-03-04 16:37:50,909 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818002932] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:50,909 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:50,909 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2025-03-04 16:37:50,910 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [834209527] [2025-03-04 16:37:50,910 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:50,910 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:50,910 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:50,910 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2025-03-04 16:37:50,910 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2025-03-04 16:37:50,910 INFO L87 Difference]: Start difference. First operand 412 states and 562 transitions. cyclomatic complexity: 154 Second operand has 4 states, 4 states have (on average 19.0) internal successors, (76), 4 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:51,062 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:51,063 INFO L93 Difference]: Finished difference Result 412 states and 561 transitions. [2025-03-04 16:37:51,063 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 412 states and 561 transitions. [2025-03-04 16:37:51,065 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 395 [2025-03-04 16:37:51,067 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 412 states to 412 states and 561 transitions. [2025-03-04 16:37:51,067 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 412 [2025-03-04 16:37:51,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 412 [2025-03-04 16:37:51,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 412 states and 561 transitions. [2025-03-04 16:37:51,068 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:51,068 INFO L218 hiAutomatonCegarLoop]: Abstraction has 412 states and 561 transitions. [2025-03-04 16:37:51,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 412 states and 561 transitions. [2025-03-04 16:37:51,071 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 412 to 412. [2025-03-04 16:37:51,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 412 states, 408 states have (on average 1.3602941176470589) internal successors, (555), 407 states have internal predecessors, (555), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:51,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 412 states to 412 states and 561 transitions. [2025-03-04 16:37:51,073 INFO L240 hiAutomatonCegarLoop]: Abstraction has 412 states and 561 transitions. [2025-03-04 16:37:51,073 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2025-03-04 16:37:51,074 INFO L432 stractBuchiCegarLoop]: Abstraction has 412 states and 561 transitions. [2025-03-04 16:37:51,074 INFO L338 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2025-03-04 16:37:51,074 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 412 states and 561 transitions. [2025-03-04 16:37:51,075 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 395 [2025-03-04 16:37:51,075 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:51,075 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:51,075 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:51,075 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:51,075 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:51,076 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:51,076 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:51,076 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 6 times [2025-03-04 16:37:51,076 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:51,077 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1424904036] [2025-03-04 16:37:51,077 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:37:51,077 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:51,083 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:51,086 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:51,086 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:37:51,086 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:51,086 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:51,089 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:51,090 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:51,091 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:51,091 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:51,095 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:51,096 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:51,096 INFO L85 PathProgramCache]: Analyzing trace with hash 549281261, now seen corresponding path program 1 times [2025-03-04 16:37:51,096 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:51,096 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2029825033] [2025-03-04 16:37:51,096 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:51,096 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:51,126 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 76 statements into 1 equivalence classes. [2025-03-04 16:37:51,148 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 76 of 76 statements. [2025-03-04 16:37:51,148 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:51,148 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:51,336 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:51,336 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:51,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2029825033] [2025-03-04 16:37:51,337 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2029825033] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:51,337 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:51,337 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:37:51,337 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [917726278] [2025-03-04 16:37:51,337 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:51,337 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:51,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:51,338 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:37:51,338 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:37:51,338 INFO L87 Difference]: Start difference. First operand 412 states and 561 transitions. cyclomatic complexity: 153 Second operand has 7 states, 7 states have (on average 10.857142857142858) internal successors, (76), 7 states have internal predecessors, (76), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:51,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:51,685 INFO L93 Difference]: Finished difference Result 417 states and 567 transitions. [2025-03-04 16:37:51,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417 states and 567 transitions. [2025-03-04 16:37:51,687 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 400 [2025-03-04 16:37:51,689 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417 states to 417 states and 567 transitions. [2025-03-04 16:37:51,689 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 417 [2025-03-04 16:37:51,690 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 417 [2025-03-04 16:37:51,690 INFO L73 IsDeterministic]: Start isDeterministic. Operand 417 states and 567 transitions. [2025-03-04 16:37:51,690 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:51,690 INFO L218 hiAutomatonCegarLoop]: Abstraction has 417 states and 567 transitions. [2025-03-04 16:37:51,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417 states and 567 transitions. [2025-03-04 16:37:51,694 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417 to 416. [2025-03-04 16:37:51,694 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 416 states, 412 states have (on average 1.3592233009708738) internal successors, (560), 411 states have internal predecessors, (560), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:51,695 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 416 states to 416 states and 566 transitions. [2025-03-04 16:37:51,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 416 states and 566 transitions. [2025-03-04 16:37:51,696 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:37:51,696 INFO L432 stractBuchiCegarLoop]: Abstraction has 416 states and 566 transitions. [2025-03-04 16:37:51,696 INFO L338 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2025-03-04 16:37:51,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 416 states and 566 transitions. [2025-03-04 16:37:51,697 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 399 [2025-03-04 16:37:51,697 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:51,697 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:51,698 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:51,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:51,698 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:51,698 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:51,698 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:51,698 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 7 times [2025-03-04 16:37:51,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:51,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1713924891] [2025-03-04 16:37:51,698 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:37:51,698 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:51,704 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:51,706 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:51,706 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:51,706 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:51,706 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:51,709 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:51,710 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:51,710 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:51,710 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:51,715 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:51,715 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:51,715 INFO L85 PathProgramCache]: Analyzing trace with hash -403077680, now seen corresponding path program 1 times [2025-03-04 16:37:51,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:51,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1797954085] [2025-03-04 16:37:51,715 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:51,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:51,738 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-04 16:37:51,752 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 16:37:51,752 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:51,752 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:51,943 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:51,943 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:51,943 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1797954085] [2025-03-04 16:37:51,943 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1797954085] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:51,943 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:51,943 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-04 16:37:51,943 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [649805786] [2025-03-04 16:37:51,943 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:51,943 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:51,943 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:51,943 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-04 16:37:51,943 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-04 16:37:51,943 INFO L87 Difference]: Start difference. First operand 416 states and 566 transitions. cyclomatic complexity: 154 Second operand has 6 states, 6 states have (on average 12.833333333333334) internal successors, (77), 6 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:52,184 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:52,184 INFO L93 Difference]: Finished difference Result 419 states and 569 transitions. [2025-03-04 16:37:52,184 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 419 states and 569 transitions. [2025-03-04 16:37:52,186 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 402 [2025-03-04 16:37:52,188 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 419 states to 419 states and 569 transitions. [2025-03-04 16:37:52,188 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 419 [2025-03-04 16:37:52,188 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 419 [2025-03-04 16:37:52,188 INFO L73 IsDeterministic]: Start isDeterministic. Operand 419 states and 569 transitions. [2025-03-04 16:37:52,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:52,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 419 states and 569 transitions. [2025-03-04 16:37:52,189 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 419 states and 569 transitions. [2025-03-04 16:37:52,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 419 to 419. [2025-03-04 16:37:52,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 419 states, 415 states have (on average 1.3566265060240963) internal successors, (563), 414 states have internal predecessors, (563), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:52,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 419 states to 419 states and 569 transitions. [2025-03-04 16:37:52,194 INFO L240 hiAutomatonCegarLoop]: Abstraction has 419 states and 569 transitions. [2025-03-04 16:37:52,194 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 16:37:52,195 INFO L432 stractBuchiCegarLoop]: Abstraction has 419 states and 569 transitions. [2025-03-04 16:37:52,195 INFO L338 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2025-03-04 16:37:52,195 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 419 states and 569 transitions. [2025-03-04 16:37:52,196 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 402 [2025-03-04 16:37:52,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:52,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:52,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:52,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:52,197 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:52,197 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:52,197 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:52,197 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 8 times [2025-03-04 16:37:52,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:52,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1120174990] [2025-03-04 16:37:52,197 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:37:52,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:52,204 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:52,206 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:52,206 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:37:52,206 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:52,206 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:52,208 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:52,210 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:52,210 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:52,210 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:52,214 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:52,215 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:52,215 INFO L85 PathProgramCache]: Analyzing trace with hash -739951568, now seen corresponding path program 1 times [2025-03-04 16:37:52,215 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:52,215 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1481766447] [2025-03-04 16:37:52,215 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:52,215 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:52,239 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 77 statements into 1 equivalence classes. [2025-03-04 16:37:52,325 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 77 of 77 statements. [2025-03-04 16:37:52,325 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:52,326 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:52,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:52,711 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:52,711 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1481766447] [2025-03-04 16:37:52,711 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1481766447] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:52,711 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:52,711 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2025-03-04 16:37:52,711 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1861709026] [2025-03-04 16:37:52,711 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:52,711 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:52,711 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:52,711 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2025-03-04 16:37:52,711 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2025-03-04 16:37:52,711 INFO L87 Difference]: Start difference. First operand 419 states and 569 transitions. cyclomatic complexity: 154 Second operand has 8 states, 8 states have (on average 9.625) internal successors, (77), 8 states have internal predecessors, (77), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:53,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:53,115 INFO L93 Difference]: Finished difference Result 426 states and 577 transitions. [2025-03-04 16:37:53,115 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 426 states and 577 transitions. [2025-03-04 16:37:53,117 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 409 [2025-03-04 16:37:53,119 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 426 states to 426 states and 577 transitions. [2025-03-04 16:37:53,119 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 426 [2025-03-04 16:37:53,120 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 426 [2025-03-04 16:37:53,120 INFO L73 IsDeterministic]: Start isDeterministic. Operand 426 states and 577 transitions. [2025-03-04 16:37:53,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:53,120 INFO L218 hiAutomatonCegarLoop]: Abstraction has 426 states and 577 transitions. [2025-03-04 16:37:53,121 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 426 states and 577 transitions. [2025-03-04 16:37:53,123 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 426 to 424. [2025-03-04 16:37:53,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 424 states, 420 states have (on average 1.3547619047619048) internal successors, (569), 419 states have internal predecessors, (569), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:53,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 424 states to 424 states and 575 transitions. [2025-03-04 16:37:53,125 INFO L240 hiAutomatonCegarLoop]: Abstraction has 424 states and 575 transitions. [2025-03-04 16:37:53,126 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2025-03-04 16:37:53,126 INFO L432 stractBuchiCegarLoop]: Abstraction has 424 states and 575 transitions. [2025-03-04 16:37:53,126 INFO L338 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2025-03-04 16:37:53,126 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 424 states and 575 transitions. [2025-03-04 16:37:53,127 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 407 [2025-03-04 16:37:53,127 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:53,127 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:53,128 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:53,128 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:53,128 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:53,128 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:53,128 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:53,128 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 9 times [2025-03-04 16:37:53,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:53,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [671034988] [2025-03-04 16:37:53,129 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:37:53,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:53,135 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:53,137 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:53,137 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:37:53,137 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:53,137 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:53,139 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:53,141 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:53,141 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:53,141 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:53,145 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:53,146 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:53,146 INFO L85 PathProgramCache]: Analyzing trace with hash -1728799574, now seen corresponding path program 1 times [2025-03-04 16:37:53,146 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:53,146 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1701888381] [2025-03-04 16:37:53,146 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:53,146 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:53,171 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:37:53,208 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:37:53,208 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:53,208 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:53,381 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:53,382 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:53,382 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1701888381] [2025-03-04 16:37:53,382 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1701888381] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:53,382 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:53,382 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:37:53,383 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1520793471] [2025-03-04 16:37:53,383 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:53,383 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:53,383 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:53,383 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:37:53,383 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:37:53,383 INFO L87 Difference]: Start difference. First operand 424 states and 575 transitions. cyclomatic complexity: 155 Second operand has 7 states, 7 states have (on average 11.142857142857142) internal successors, (78), 7 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:53,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:53,798 INFO L93 Difference]: Finished difference Result 429 states and 581 transitions. [2025-03-04 16:37:53,799 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 429 states and 581 transitions. [2025-03-04 16:37:53,800 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 412 [2025-03-04 16:37:53,802 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 429 states to 429 states and 581 transitions. [2025-03-04 16:37:53,802 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 429 [2025-03-04 16:37:53,802 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 429 [2025-03-04 16:37:53,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 429 states and 581 transitions. [2025-03-04 16:37:53,803 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:53,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 429 states and 581 transitions. [2025-03-04 16:37:53,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states and 581 transitions. [2025-03-04 16:37:53,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 424. [2025-03-04 16:37:53,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 424 states, 420 states have (on average 1.3547619047619048) internal successors, (569), 419 states have internal predecessors, (569), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:53,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 424 states to 424 states and 575 transitions. [2025-03-04 16:37:53,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 424 states and 575 transitions. [2025-03-04 16:37:53,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:37:53,809 INFO L432 stractBuchiCegarLoop]: Abstraction has 424 states and 575 transitions. [2025-03-04 16:37:53,809 INFO L338 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2025-03-04 16:37:53,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 424 states and 575 transitions. [2025-03-04 16:37:53,811 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 407 [2025-03-04 16:37:53,811 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:53,811 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:53,811 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:53,811 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:53,811 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:53,811 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:53,812 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:53,812 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 10 times [2025-03-04 16:37:53,812 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:53,812 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [292835902] [2025-03-04 16:37:53,812 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:37:53,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:53,819 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:37:53,825 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:53,825 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:37:53,825 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:53,825 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:53,831 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:53,833 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:53,833 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:53,833 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:53,837 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:53,838 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:53,838 INFO L85 PathProgramCache]: Analyzing trace with hash -1077927159, now seen corresponding path program 1 times [2025-03-04 16:37:53,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:53,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815335647] [2025-03-04 16:37:53,838 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:53,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:53,868 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:37:53,883 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:37:53,883 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:53,883 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:54,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:54,124 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:54,124 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815335647] [2025-03-04 16:37:54,124 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815335647] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:54,124 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:54,124 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:37:54,124 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [101883649] [2025-03-04 16:37:54,125 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:54,125 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:54,125 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:54,125 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:37:54,125 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:37:54,125 INFO L87 Difference]: Start difference. First operand 424 states and 575 transitions. cyclomatic complexity: 155 Second operand has 9 states, 9 states have (on average 8.666666666666666) internal successors, (78), 9 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:54,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:54,636 INFO L93 Difference]: Finished difference Result 435 states and 590 transitions. [2025-03-04 16:37:54,636 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 590 transitions. [2025-03-04 16:37:54,638 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 418 [2025-03-04 16:37:54,640 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 590 transitions. [2025-03-04 16:37:54,640 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2025-03-04 16:37:54,640 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2025-03-04 16:37:54,640 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 590 transitions. [2025-03-04 16:37:54,641 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:54,641 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 590 transitions. [2025-03-04 16:37:54,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 590 transitions. [2025-03-04 16:37:54,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 432. [2025-03-04 16:37:54,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.355140186915888) internal successors, (580), 427 states have internal predecessors, (580), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:54,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 586 transitions. [2025-03-04 16:37:54,646 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 586 transitions. [2025-03-04 16:37:54,647 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-04 16:37:54,647 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 586 transitions. [2025-03-04 16:37:54,647 INFO L338 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2025-03-04 16:37:54,647 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 586 transitions. [2025-03-04 16:37:54,648 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 415 [2025-03-04 16:37:54,648 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:54,649 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:54,649 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:54,649 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:54,649 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:54,649 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:54,650 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:54,650 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 11 times [2025-03-04 16:37:54,650 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:54,650 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1382705542] [2025-03-04 16:37:54,650 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:37:54,650 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:54,657 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:54,659 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:54,659 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:37:54,659 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:54,659 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:54,661 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:54,663 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:54,663 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:54,663 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:54,668 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:54,668 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:54,668 INFO L85 PathProgramCache]: Analyzing trace with hash -916088580, now seen corresponding path program 1 times [2025-03-04 16:37:54,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:54,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [808754487] [2025-03-04 16:37:54,668 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:54,668 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:54,692 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 78 statements into 1 equivalence classes. [2025-03-04 16:37:54,813 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 78 of 78 statements. [2025-03-04 16:37:54,813 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:54,813 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:55,263 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:55,263 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:55,263 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [808754487] [2025-03-04 16:37:55,263 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [808754487] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:55,263 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:55,264 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:37:55,264 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [954542] [2025-03-04 16:37:55,264 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:55,264 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:55,264 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:55,264 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:37:55,264 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:37:55,264 INFO L87 Difference]: Start difference. First operand 432 states and 586 transitions. cyclomatic complexity: 158 Second operand has 13 states, 13 states have (on average 6.0) internal successors, (78), 13 states have internal predecessors, (78), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:56,489 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:56,490 INFO L93 Difference]: Finished difference Result 512 states and 696 transitions. [2025-03-04 16:37:56,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 512 states and 696 transitions. [2025-03-04 16:37:56,492 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 495 [2025-03-04 16:37:56,494 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 512 states to 512 states and 696 transitions. [2025-03-04 16:37:56,494 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 512 [2025-03-04 16:37:56,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 512 [2025-03-04 16:37:56,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 512 states and 696 transitions. [2025-03-04 16:37:56,495 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:56,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 512 states and 696 transitions. [2025-03-04 16:37:56,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 512 states and 696 transitions. [2025-03-04 16:37:56,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 512 to 438. [2025-03-04 16:37:56,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 438 states, 434 states have (on average 1.3548387096774193) internal successors, (588), 433 states have internal predecessors, (588), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:56,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 594 transitions. [2025-03-04 16:37:56,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 438 states and 594 transitions. [2025-03-04 16:37:56,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-04 16:37:56,503 INFO L432 stractBuchiCegarLoop]: Abstraction has 438 states and 594 transitions. [2025-03-04 16:37:56,503 INFO L338 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2025-03-04 16:37:56,503 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states and 594 transitions. [2025-03-04 16:37:56,504 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 421 [2025-03-04 16:37:56,504 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:56,504 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:56,505 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:56,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:56,505 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:56,505 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise78#1 := 0;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:56,505 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:56,505 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 12 times [2025-03-04 16:37:56,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:56,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1334622749] [2025-03-04 16:37:56,506 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:37:56,506 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:56,513 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:56,515 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:56,515 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:37:56,515 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:56,515 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:56,518 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:56,520 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:56,521 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:56,521 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:56,526 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:56,526 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:56,527 INFO L85 PathProgramCache]: Analyzing trace with hash 1227440681, now seen corresponding path program 1 times [2025-03-04 16:37:56,527 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:56,527 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1590182692] [2025-03-04 16:37:56,527 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:56,527 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:56,553 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:37:56,571 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:37:56,571 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:56,571 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:56,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:56,755 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:56,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1590182692] [2025-03-04 16:37:56,756 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1590182692] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:56,756 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:56,756 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:37:56,756 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1890687824] [2025-03-04 16:37:56,756 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:56,756 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:56,756 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:56,756 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:37:56,756 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:37:56,756 INFO L87 Difference]: Start difference. First operand 438 states and 594 transitions. cyclomatic complexity: 160 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:57,222 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:57,222 INFO L93 Difference]: Finished difference Result 448 states and 606 transitions. [2025-03-04 16:37:57,222 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 448 states and 606 transitions. [2025-03-04 16:37:57,223 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 431 [2025-03-04 16:37:57,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 448 states to 448 states and 606 transitions. [2025-03-04 16:37:57,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 448 [2025-03-04 16:37:57,226 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 448 [2025-03-04 16:37:57,226 INFO L73 IsDeterministic]: Start isDeterministic. Operand 448 states and 606 transitions. [2025-03-04 16:37:57,226 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:57,226 INFO L218 hiAutomatonCegarLoop]: Abstraction has 448 states and 606 transitions. [2025-03-04 16:37:57,227 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 448 states and 606 transitions. [2025-03-04 16:37:57,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 448 to 441. [2025-03-04 16:37:57,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 437 states have (on average 1.3546910755148742) internal successors, (592), 436 states have internal predecessors, (592), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:57,232 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 598 transitions. [2025-03-04 16:37:57,232 INFO L240 hiAutomatonCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:57,232 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-04 16:37:57,233 INFO L432 stractBuchiCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:57,233 INFO L338 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2025-03-04 16:37:57,233 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 598 transitions. [2025-03-04 16:37:57,234 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 424 [2025-03-04 16:37:57,234 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:57,234 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:57,234 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:57,234 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:57,234 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:57,237 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:57,237 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:57,237 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 13 times [2025-03-04 16:37:57,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:57,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [368373146] [2025-03-04 16:37:57,238 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:37:57,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:57,245 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:57,247 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:57,247 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:57,247 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:57,247 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:57,250 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:57,251 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:57,251 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:57,251 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:57,258 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:57,259 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:57,259 INFO L85 PathProgramCache]: Analyzing trace with hash -1667444273, now seen corresponding path program 1 times [2025-03-04 16:37:57,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:57,260 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [124730394] [2025-03-04 16:37:57,260 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:57,260 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:57,286 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:37:57,368 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:37:57,369 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:57,369 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:57,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:57,604 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:57,604 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [124730394] [2025-03-04 16:37:57,604 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [124730394] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:57,604 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:57,605 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:37:57,605 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1258126775] [2025-03-04 16:37:57,605 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:57,605 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:57,605 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:57,606 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:37:57,606 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:37:57,606 INFO L87 Difference]: Start difference. First operand 441 states and 598 transitions. cyclomatic complexity: 161 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:58,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:58,132 INFO L93 Difference]: Finished difference Result 451 states and 610 transitions. [2025-03-04 16:37:58,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 610 transitions. [2025-03-04 16:37:58,134 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 434 [2025-03-04 16:37:58,136 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 610 transitions. [2025-03-04 16:37:58,136 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-04 16:37:58,137 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-04 16:37:58,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 610 transitions. [2025-03-04 16:37:58,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:58,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 610 transitions. [2025-03-04 16:37:58,138 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 610 transitions. [2025-03-04 16:37:58,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 441. [2025-03-04 16:37:58,142 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 437 states have (on average 1.3546910755148742) internal successors, (592), 436 states have internal predecessors, (592), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:58,143 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 598 transitions. [2025-03-04 16:37:58,143 INFO L240 hiAutomatonCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:58,143 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:37:58,145 INFO L432 stractBuchiCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:58,145 INFO L338 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2025-03-04 16:37:58,145 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 598 transitions. [2025-03-04 16:37:58,146 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 424 [2025-03-04 16:37:58,146 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:58,146 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:58,147 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:58,147 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:58,147 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:58,147 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:58,148 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:58,148 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 14 times [2025-03-04 16:37:58,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:58,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372305737] [2025-03-04 16:37:58,148 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:37:58,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:58,155 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:58,157 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:58,157 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:37:58,157 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:58,157 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:58,162 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:58,163 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:58,163 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:58,163 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:58,168 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:58,169 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:58,169 INFO L85 PathProgramCache]: Analyzing trace with hash 1626779113, now seen corresponding path program 1 times [2025-03-04 16:37:58,169 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:58,169 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [612646627] [2025-03-04 16:37:58,169 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:58,170 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:58,195 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:37:58,296 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:37:58,296 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:58,296 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:58,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:58,518 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:58,518 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [612646627] [2025-03-04 16:37:58,518 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [612646627] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:58,518 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:58,518 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2025-03-04 16:37:58,518 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021568541] [2025-03-04 16:37:58,518 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:58,519 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:58,519 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:58,519 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2025-03-04 16:37:58,519 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2025-03-04 16:37:58,519 INFO L87 Difference]: Start difference. First operand 441 states and 598 transitions. cyclomatic complexity: 161 Second operand has 6 states, 6 states have (on average 13.166666666666666) internal successors, (79), 6 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:58,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:58,790 INFO L93 Difference]: Finished difference Result 438 states and 594 transitions. [2025-03-04 16:37:58,790 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 438 states and 594 transitions. [2025-03-04 16:37:58,792 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 421 [2025-03-04 16:37:58,794 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 438 states to 438 states and 594 transitions. [2025-03-04 16:37:58,794 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 438 [2025-03-04 16:37:58,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 438 [2025-03-04 16:37:58,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 438 states and 594 transitions. [2025-03-04 16:37:58,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:58,795 INFO L218 hiAutomatonCegarLoop]: Abstraction has 438 states and 594 transitions. [2025-03-04 16:37:58,795 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 438 states and 594 transitions. [2025-03-04 16:37:58,799 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 438 to 438. [2025-03-04 16:37:58,800 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 438 states, 434 states have (on average 1.3548387096774193) internal successors, (588), 433 states have internal predecessors, (588), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:58,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 594 transitions. [2025-03-04 16:37:58,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 438 states and 594 transitions. [2025-03-04 16:37:58,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2025-03-04 16:37:58,802 INFO L432 stractBuchiCegarLoop]: Abstraction has 438 states and 594 transitions. [2025-03-04 16:37:58,802 INFO L338 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2025-03-04 16:37:58,802 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 438 states and 594 transitions. [2025-03-04 16:37:58,803 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 421 [2025-03-04 16:37:58,803 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:58,803 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:58,804 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:58,804 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:58,804 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:58,804 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:58,805 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:58,805 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 15 times [2025-03-04 16:37:58,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:58,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2016768807] [2025-03-04 16:37:58,805 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:37:58,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:58,812 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:58,814 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:58,814 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:37:58,814 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:58,814 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:58,819 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:58,821 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:58,821 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:58,821 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:58,826 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:58,826 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:58,826 INFO L85 PathProgramCache]: Analyzing trace with hash -1946159530, now seen corresponding path program 1 times [2025-03-04 16:37:58,826 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:58,826 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1955648009] [2025-03-04 16:37:58,826 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:58,826 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:58,849 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:37:58,909 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:37:58,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:58,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:37:59,228 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:37:59,228 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:37:59,228 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1955648009] [2025-03-04 16:37:59,228 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1955648009] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:37:59,229 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:37:59,229 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-04 16:37:59,229 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1113762064] [2025-03-04 16:37:59,229 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:37:59,229 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:37:59,229 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:37:59,229 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-04 16:37:59,229 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2025-03-04 16:37:59,229 INFO L87 Difference]: Start difference. First operand 438 states and 594 transitions. cyclomatic complexity: 160 Second operand has 11 states, 11 states have (on average 7.181818181818182) internal successors, (79), 11 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:37:59,881 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:37:59,881 INFO L93 Difference]: Finished difference Result 463 states and 630 transitions. [2025-03-04 16:37:59,882 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463 states and 630 transitions. [2025-03-04 16:37:59,883 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 446 [2025-03-04 16:37:59,885 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463 states to 463 states and 630 transitions. [2025-03-04 16:37:59,885 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463 [2025-03-04 16:37:59,886 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463 [2025-03-04 16:37:59,886 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463 states and 630 transitions. [2025-03-04 16:37:59,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:37:59,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 463 states and 630 transitions. [2025-03-04 16:37:59,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states and 630 transitions. [2025-03-04 16:37:59,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 441. [2025-03-04 16:37:59,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 441 states, 437 states have (on average 1.3546910755148742) internal successors, (592), 436 states have internal predecessors, (592), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:37:59,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 598 transitions. [2025-03-04 16:37:59,892 INFO L240 hiAutomatonCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:59,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 16:37:59,893 INFO L432 stractBuchiCegarLoop]: Abstraction has 441 states and 598 transitions. [2025-03-04 16:37:59,893 INFO L338 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2025-03-04 16:37:59,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 441 states and 598 transitions. [2025-03-04 16:37:59,894 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 424 [2025-03-04 16:37:59,894 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:37:59,894 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:37:59,894 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:37:59,894 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:37:59,895 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:37:59,895 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:37:59,896 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:59,896 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 16 times [2025-03-04 16:37:59,896 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:59,896 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1137860251] [2025-03-04 16:37:59,896 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:37:59,896 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:59,904 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:37:59,905 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:59,905 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:37:59,905 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:59,906 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:37:59,908 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:37:59,909 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:37:59,909 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:37:59,909 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:37:59,915 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:37:59,916 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:37:59,916 INFO L85 PathProgramCache]: Analyzing trace with hash -1427415249, now seen corresponding path program 1 times [2025-03-04 16:37:59,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:37:59,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [12706047] [2025-03-04 16:37:59,917 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:37:59,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:37:59,941 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:38:00,040 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:38:00,041 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:00,041 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:00,460 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:00,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:00,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [12706047] [2025-03-04 16:38:00,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [12706047] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:00,461 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:00,461 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:38:00,461 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1139549300] [2025-03-04 16:38:00,461 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:00,461 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:00,462 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:00,462 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:38:00,462 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:38:00,462 INFO L87 Difference]: Start difference. First operand 441 states and 598 transitions. cyclomatic complexity: 161 Second operand has 13 states, 13 states have (on average 6.076923076923077) internal successors, (79), 13 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:01,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:01,242 INFO L93 Difference]: Finished difference Result 516 states and 700 transitions. [2025-03-04 16:38:01,242 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 516 states and 700 transitions. [2025-03-04 16:38:01,244 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 499 [2025-03-04 16:38:01,246 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 516 states to 516 states and 700 transitions. [2025-03-04 16:38:01,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 516 [2025-03-04 16:38:01,246 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 516 [2025-03-04 16:38:01,246 INFO L73 IsDeterministic]: Start isDeterministic. Operand 516 states and 700 transitions. [2025-03-04 16:38:01,247 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:01,247 INFO L218 hiAutomatonCegarLoop]: Abstraction has 516 states and 700 transitions. [2025-03-04 16:38:01,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 516 states and 700 transitions. [2025-03-04 16:38:01,251 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 516 to 442. [2025-03-04 16:38:01,252 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 442 states, 438 states have (on average 1.356164383561644) internal successors, (594), 437 states have internal predecessors, (594), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:01,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 600 transitions. [2025-03-04 16:38:01,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 442 states and 600 transitions. [2025-03-04 16:38:01,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2025-03-04 16:38:01,254 INFO L432 stractBuchiCegarLoop]: Abstraction has 442 states and 600 transitions. [2025-03-04 16:38:01,254 INFO L338 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2025-03-04 16:38:01,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 442 states and 600 transitions. [2025-03-04 16:38:01,256 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 425 [2025-03-04 16:38:01,256 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:01,256 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:01,256 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:01,256 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:01,256 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:01,257 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 32 % 4294967296;main_#t~bitwise83#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:01,257 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:01,257 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 17 times [2025-03-04 16:38:01,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:01,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328830900] [2025-03-04 16:38:01,257 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:38:01,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:01,264 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:01,265 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:01,266 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:38:01,266 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:01,266 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:01,268 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:01,269 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:01,269 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:01,269 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:01,275 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:01,276 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:01,276 INFO L85 PathProgramCache]: Analyzing trace with hash 253569608, now seen corresponding path program 1 times [2025-03-04 16:38:01,276 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:01,276 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [467403337] [2025-03-04 16:38:01,276 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:01,276 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:01,300 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 79 statements into 1 equivalence classes. [2025-03-04 16:38:01,364 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 79 of 79 statements. [2025-03-04 16:38:01,364 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:01,364 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:01,984 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:01,984 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:01,984 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [467403337] [2025-03-04 16:38:01,984 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [467403337] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:01,984 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:01,985 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:38:01,985 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [333580600] [2025-03-04 16:38:01,985 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:01,985 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:01,985 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:01,985 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:38:01,985 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:38:01,985 INFO L87 Difference]: Start difference. First operand 442 states and 600 transitions. cyclomatic complexity: 162 Second operand has 9 states, 9 states have (on average 8.777777777777779) internal successors, (79), 9 states have internal predecessors, (79), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:02,548 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:02,549 INFO L93 Difference]: Finished difference Result 434 states and 588 transitions. [2025-03-04 16:38:02,549 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 434 states and 588 transitions. [2025-03-04 16:38:02,550 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 417 [2025-03-04 16:38:02,553 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 434 states to 434 states and 588 transitions. [2025-03-04 16:38:02,553 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 434 [2025-03-04 16:38:02,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 434 [2025-03-04 16:38:02,554 INFO L73 IsDeterministic]: Start isDeterministic. Operand 434 states and 588 transitions. [2025-03-04 16:38:02,554 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:02,554 INFO L218 hiAutomatonCegarLoop]: Abstraction has 434 states and 588 transitions. [2025-03-04 16:38:02,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 434 states and 588 transitions. [2025-03-04 16:38:02,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 434 to 432. [2025-03-04 16:38:02,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 432 states, 428 states have (on average 1.352803738317757) internal successors, (579), 427 states have internal predecessors, (579), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:02,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 585 transitions. [2025-03-04 16:38:02,561 INFO L240 hiAutomatonCegarLoop]: Abstraction has 432 states and 585 transitions. [2025-03-04 16:38:02,562 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2025-03-04 16:38:02,562 INFO L432 stractBuchiCegarLoop]: Abstraction has 432 states and 585 transitions. [2025-03-04 16:38:02,562 INFO L338 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2025-03-04 16:38:02,562 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 432 states and 585 transitions. [2025-03-04 16:38:02,563 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 415 [2025-03-04 16:38:02,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:02,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:02,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:02,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:02,565 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:02,565 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:02,565 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:02,566 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 18 times [2025-03-04 16:38:02,566 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:02,566 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1515289154] [2025-03-04 16:38:02,566 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:38:02,566 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:02,575 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:02,578 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:02,579 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:38:02,579 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:02,579 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:02,582 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:02,585 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:02,585 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:02,585 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:02,591 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:02,592 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:02,592 INFO L85 PathProgramCache]: Analyzing trace with hash 1840451015, now seen corresponding path program 1 times [2025-03-04 16:38:02,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:02,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763822741] [2025-03-04 16:38:02,592 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:02,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:02,627 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:38:02,676 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:38:02,677 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:02,677 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:02,834 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:02,834 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:02,834 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763822741] [2025-03-04 16:38:02,834 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763822741] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:02,834 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:02,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:38:02,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [136692575] [2025-03-04 16:38:02,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:02,834 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:02,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:02,835 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:38:02,835 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:38:02,835 INFO L87 Difference]: Start difference. First operand 432 states and 585 transitions. cyclomatic complexity: 157 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:03,202 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:03,202 INFO L93 Difference]: Finished difference Result 435 states and 588 transitions. [2025-03-04 16:38:03,202 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 435 states and 588 transitions. [2025-03-04 16:38:03,203 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 418 [2025-03-04 16:38:03,205 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 435 states to 435 states and 588 transitions. [2025-03-04 16:38:03,205 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 435 [2025-03-04 16:38:03,205 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 435 [2025-03-04 16:38:03,205 INFO L73 IsDeterministic]: Start isDeterministic. Operand 435 states and 588 transitions. [2025-03-04 16:38:03,206 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:03,206 INFO L218 hiAutomatonCegarLoop]: Abstraction has 435 states and 588 transitions. [2025-03-04 16:38:03,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states and 588 transitions. [2025-03-04 16:38:03,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2025-03-04 16:38:03,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 431 states have (on average 1.3503480278422273) internal successors, (582), 430 states have internal predecessors, (582), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:03,210 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 588 transitions. [2025-03-04 16:38:03,210 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 588 transitions. [2025-03-04 16:38:03,210 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:38:03,211 INFO L432 stractBuchiCegarLoop]: Abstraction has 435 states and 588 transitions. [2025-03-04 16:38:03,211 INFO L338 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2025-03-04 16:38:03,211 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 588 transitions. [2025-03-04 16:38:03,212 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 418 [2025-03-04 16:38:03,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:03,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:03,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:03,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:03,212 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:03,213 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:03,213 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:03,213 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 19 times [2025-03-04 16:38:03,213 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:03,213 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1192839489] [2025-03-04 16:38:03,213 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:38:03,213 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:03,219 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:03,221 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:03,221 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:03,221 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:03,221 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:03,223 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:03,224 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:03,224 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:03,224 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:03,228 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:03,229 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:03,229 INFO L85 PathProgramCache]: Analyzing trace with hash -1480979837, now seen corresponding path program 1 times [2025-03-04 16:38:03,229 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:03,229 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1873302868] [2025-03-04 16:38:03,229 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:03,229 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:03,253 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:38:03,298 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:38:03,298 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:03,298 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:03,511 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:03,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:03,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1873302868] [2025-03-04 16:38:03,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1873302868] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:03,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:03,512 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2025-03-04 16:38:03,512 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626115795] [2025-03-04 16:38:03,512 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:03,513 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:03,513 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:03,513 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2025-03-04 16:38:03,513 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2025-03-04 16:38:03,513 INFO L87 Difference]: Start difference. First operand 435 states and 588 transitions. cyclomatic complexity: 157 Second operand has 7 states, 7 states have (on average 11.428571428571429) internal successors, (80), 7 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:03,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:03,855 INFO L93 Difference]: Finished difference Result 441 states and 593 transitions. [2025-03-04 16:38:03,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 441 states and 593 transitions. [2025-03-04 16:38:03,856 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 424 [2025-03-04 16:38:03,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 441 states to 441 states and 593 transitions. [2025-03-04 16:38:03,858 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 441 [2025-03-04 16:38:03,858 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 441 [2025-03-04 16:38:03,858 INFO L73 IsDeterministic]: Start isDeterministic. Operand 441 states and 593 transitions. [2025-03-04 16:38:03,858 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:03,859 INFO L218 hiAutomatonCegarLoop]: Abstraction has 441 states and 593 transitions. [2025-03-04 16:38:03,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states and 593 transitions. [2025-03-04 16:38:03,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 435. [2025-03-04 16:38:03,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 435 states, 431 states have (on average 1.3480278422273781) internal successors, (581), 430 states have internal predecessors, (581), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:03,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 587 transitions. [2025-03-04 16:38:03,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 435 states and 587 transitions. [2025-03-04 16:38:03,867 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2025-03-04 16:38:03,867 INFO L432 stractBuchiCegarLoop]: Abstraction has 435 states and 587 transitions. [2025-03-04 16:38:03,867 INFO L338 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2025-03-04 16:38:03,867 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 435 states and 587 transitions. [2025-03-04 16:38:03,868 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 418 [2025-03-04 16:38:03,868 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:03,868 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:03,869 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:03,869 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:03,869 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:03,870 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:03,870 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:03,870 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 20 times [2025-03-04 16:38:03,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:03,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [850824883] [2025-03-04 16:38:03,870 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:38:03,870 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:03,877 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:03,878 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:03,879 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:38:03,879 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:03,879 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:03,881 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:03,882 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:03,882 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:03,882 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:03,890 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:03,890 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:03,890 INFO L85 PathProgramCache]: Analyzing trace with hash 531617763, now seen corresponding path program 1 times [2025-03-04 16:38:03,890 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:03,890 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1184687277] [2025-03-04 16:38:03,890 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:03,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:03,915 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:38:03,986 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:38:03,986 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:03,986 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:04,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:04,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:04,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1184687277] [2025-03-04 16:38:04,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1184687277] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:04,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:04,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2025-03-04 16:38:04,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [542898967] [2025-03-04 16:38:04,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:04,171 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:04,171 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:04,171 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2025-03-04 16:38:04,171 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2025-03-04 16:38:04,171 INFO L87 Difference]: Start difference. First operand 435 states and 587 transitions. cyclomatic complexity: 156 Second operand has 10 states, 10 states have (on average 8.0) internal successors, (80), 10 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:04,693 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:04,693 INFO L93 Difference]: Finished difference Result 451 states and 609 transitions. [2025-03-04 16:38:04,693 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 451 states and 609 transitions. [2025-03-04 16:38:04,694 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 434 [2025-03-04 16:38:04,696 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 451 states to 451 states and 609 transitions. [2025-03-04 16:38:04,696 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 451 [2025-03-04 16:38:04,696 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 451 [2025-03-04 16:38:04,696 INFO L73 IsDeterministic]: Start isDeterministic. Operand 451 states and 609 transitions. [2025-03-04 16:38:04,697 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:04,697 INFO L218 hiAutomatonCegarLoop]: Abstraction has 451 states and 609 transitions. [2025-03-04 16:38:04,697 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states and 609 transitions. [2025-03-04 16:38:04,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 445. [2025-03-04 16:38:04,701 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 445 states, 441 states have (on average 1.346938775510204) internal successors, (594), 440 states have internal predecessors, (594), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:04,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 600 transitions. [2025-03-04 16:38:04,702 INFO L240 hiAutomatonCegarLoop]: Abstraction has 445 states and 600 transitions. [2025-03-04 16:38:04,703 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:38:04,703 INFO L432 stractBuchiCegarLoop]: Abstraction has 445 states and 600 transitions. [2025-03-04 16:38:04,703 INFO L338 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2025-03-04 16:38:04,703 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states and 600 transitions. [2025-03-04 16:38:04,704 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 428 [2025-03-04 16:38:04,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:04,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:04,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:04,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:04,706 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:04,706 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:04,706 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:04,706 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 21 times [2025-03-04 16:38:04,706 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:04,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734243864] [2025-03-04 16:38:04,707 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST2 [2025-03-04 16:38:04,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:04,714 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:04,716 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:04,716 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST2 issued 1 check-sat command(s) [2025-03-04 16:38:04,716 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:04,716 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:04,719 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:04,722 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:04,723 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:04,723 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:04,727 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:04,728 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:04,728 INFO L85 PathProgramCache]: Analyzing trace with hash -137164875, now seen corresponding path program 1 times [2025-03-04 16:38:04,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:04,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [601437333] [2025-03-04 16:38:04,728 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:04,728 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:04,800 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:38:04,872 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:38:04,872 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:04,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:05,197 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:05,197 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:05,197 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [601437333] [2025-03-04 16:38:05,198 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [601437333] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:05,198 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:05,198 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:38:05,198 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [90832746] [2025-03-04 16:38:05,198 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:05,198 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:05,198 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:05,198 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:38:05,198 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:38:05,199 INFO L87 Difference]: Start difference. First operand 445 states and 600 transitions. cyclomatic complexity: 159 Second operand has 9 states, 9 states have (on average 8.88888888888889) internal successors, (80), 9 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:05,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:05,747 INFO L93 Difference]: Finished difference Result 450 states and 605 transitions. [2025-03-04 16:38:05,747 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 450 states and 605 transitions. [2025-03-04 16:38:05,748 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 433 [2025-03-04 16:38:05,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 450 states to 450 states and 605 transitions. [2025-03-04 16:38:05,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 450 [2025-03-04 16:38:05,750 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 450 [2025-03-04 16:38:05,750 INFO L73 IsDeterministic]: Start isDeterministic. Operand 450 states and 605 transitions. [2025-03-04 16:38:05,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:05,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 450 states and 605 transitions. [2025-03-04 16:38:05,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states and 605 transitions. [2025-03-04 16:38:05,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 445. [2025-03-04 16:38:05,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 445 states, 441 states have (on average 1.344671201814059) internal successors, (593), 440 states have internal predecessors, (593), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:05,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 599 transitions. [2025-03-04 16:38:05,755 INFO L240 hiAutomatonCegarLoop]: Abstraction has 445 states and 599 transitions. [2025-03-04 16:38:05,756 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:38:05,756 INFO L432 stractBuchiCegarLoop]: Abstraction has 445 states and 599 transitions. [2025-03-04 16:38:05,756 INFO L338 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2025-03-04 16:38:05,756 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 445 states and 599 transitions. [2025-03-04 16:38:05,757 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 428 [2025-03-04 16:38:05,757 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:05,757 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:05,757 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:05,758 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:05,758 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:05,758 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:05,758 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:05,758 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 22 times [2025-03-04 16:38:05,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:05,758 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2003548456] [2025-03-04 16:38:05,758 INFO L95 rtionOrderModulation]: Changing assertion order to TERMS_WITH_SMALL_CONSTANTS_FIRST [2025-03-04 16:38:05,758 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:05,765 INFO L108 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST partitioned 2 statements into 2 equivalence classes. [2025-03-04 16:38:05,767 INFO L111 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:05,767 INFO L114 AnnotateAndAsserter]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 2 check-sat command(s) [2025-03-04 16:38:05,767 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:05,767 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:05,769 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:05,770 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:05,770 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:05,770 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:05,774 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:05,775 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:05,775 INFO L85 PathProgramCache]: Analyzing trace with hash 603720697, now seen corresponding path program 1 times [2025-03-04 16:38:05,775 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:05,775 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1309149646] [2025-03-04 16:38:05,775 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:05,775 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:05,800 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 80 statements into 1 equivalence classes. [2025-03-04 16:38:05,850 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 80 of 80 statements. [2025-03-04 16:38:05,850 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:05,850 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:06,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:06,206 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:06,206 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1309149646] [2025-03-04 16:38:06,206 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1309149646] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:06,206 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:06,206 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:38:06,207 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1205731941] [2025-03-04 16:38:06,207 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:06,207 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:06,207 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:06,207 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:38:06,207 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:38:06,207 INFO L87 Difference]: Start difference. First operand 445 states and 599 transitions. cyclomatic complexity: 158 Second operand has 13 states, 13 states have (on average 6.153846153846154) internal successors, (80), 13 states have internal predecessors, (80), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:06,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:06,748 INFO L93 Difference]: Finished difference Result 473 states and 640 transitions. [2025-03-04 16:38:06,748 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 473 states and 640 transitions. [2025-03-04 16:38:06,749 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 456 [2025-03-04 16:38:06,750 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 473 states to 473 states and 640 transitions. [2025-03-04 16:38:06,750 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 473 [2025-03-04 16:38:06,751 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 473 [2025-03-04 16:38:06,751 INFO L73 IsDeterministic]: Start isDeterministic. Operand 473 states and 640 transitions. [2025-03-04 16:38:06,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:06,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 473 states and 640 transitions. [2025-03-04 16:38:06,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 473 states and 640 transitions. [2025-03-04 16:38:06,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 473 to 453. [2025-03-04 16:38:06,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 453 states, 449 states have (on average 1.3452115812917596) internal successors, (604), 448 states have internal predecessors, (604), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:06,756 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 610 transitions. [2025-03-04 16:38:06,756 INFO L240 hiAutomatonCegarLoop]: Abstraction has 453 states and 610 transitions. [2025-03-04 16:38:06,757 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 16:38:06,757 INFO L432 stractBuchiCegarLoop]: Abstraction has 453 states and 610 transitions. [2025-03-04 16:38:06,757 INFO L338 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2025-03-04 16:38:06,757 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 453 states and 610 transitions. [2025-03-04 16:38:06,758 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 436 [2025-03-04 16:38:06,758 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:06,758 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:06,759 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:06,759 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:06,759 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:06,759 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise78#1 := main_~_ha_hashv~0#1 % 4294967296 / 8192;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume !(0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296);" "assume main_~_ha_hashv~0#1 % 4294967296 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := 0;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:06,759 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:06,759 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 23 times [2025-03-04 16:38:06,760 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:06,760 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351211326] [2025-03-04 16:38:06,760 INFO L95 rtionOrderModulation]: Changing assertion order to INSIDE_LOOP_FIRST1 [2025-03-04 16:38:06,760 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:06,766 INFO L108 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:06,767 INFO L111 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:06,768 INFO L114 AnnotateAndAsserter]: Assert order INSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:38:06,768 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:06,768 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:06,770 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:06,772 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:06,772 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:06,772 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:06,777 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:06,777 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:06,777 INFO L85 PathProgramCache]: Analyzing trace with hash -1557967918, now seen corresponding path program 1 times [2025-03-04 16:38:06,777 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:06,777 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [291207472] [2025-03-04 16:38:06,777 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:06,777 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:06,803 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-04 16:38:06,872 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 16:38:06,872 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:06,872 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:07,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:07,294 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:07,294 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [291207472] [2025-03-04 16:38:07,294 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [291207472] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:07,294 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:07,294 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2025-03-04 16:38:07,294 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1484309937] [2025-03-04 16:38:07,294 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:07,295 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:07,295 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:07,295 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2025-03-04 16:38:07,295 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2025-03-04 16:38:07,295 INFO L87 Difference]: Start difference. First operand 453 states and 610 transitions. cyclomatic complexity: 161 Second operand has 13 states, 13 states have (on average 6.230769230769231) internal successors, (81), 13 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:07,930 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:07,931 INFO L93 Difference]: Finished difference Result 463 states and 623 transitions. [2025-03-04 16:38:07,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463 states and 623 transitions. [2025-03-04 16:38:07,932 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 446 [2025-03-04 16:38:07,933 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463 states to 463 states and 623 transitions. [2025-03-04 16:38:07,933 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463 [2025-03-04 16:38:07,933 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463 [2025-03-04 16:38:07,933 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463 states and 623 transitions. [2025-03-04 16:38:07,934 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:07,934 INFO L218 hiAutomatonCegarLoop]: Abstraction has 463 states and 623 transitions. [2025-03-04 16:38:07,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states and 623 transitions. [2025-03-04 16:38:07,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 458. [2025-03-04 16:38:07,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 458 states, 454 states have (on average 1.3458149779735682) internal successors, (611), 453 states have internal predecessors, (611), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:07,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 458 states to 458 states and 617 transitions. [2025-03-04 16:38:07,939 INFO L240 hiAutomatonCegarLoop]: Abstraction has 458 states and 617 transitions. [2025-03-04 16:38:07,939 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2025-03-04 16:38:07,939 INFO L432 stractBuchiCegarLoop]: Abstraction has 458 states and 617 transitions. [2025-03-04 16:38:07,939 INFO L338 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2025-03-04 16:38:07,940 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 458 states and 617 transitions. [2025-03-04 16:38:07,941 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 441 [2025-03-04 16:38:07,941 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:07,941 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:07,941 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:07,941 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:07,941 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:07,942 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise79#1 := 0;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:07,942 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:07,942 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 24 times [2025-03-04 16:38:07,942 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:07,942 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753209110] [2025-03-04 16:38:07,942 INFO L95 rtionOrderModulation]: Changing assertion order to MIX_INSIDE_OUTSIDE [2025-03-04 16:38:07,942 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:07,949 INFO L108 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:07,951 INFO L111 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:07,951 INFO L114 AnnotateAndAsserter]: Assert order MIX_INSIDE_OUTSIDE issued 1 check-sat command(s) [2025-03-04 16:38:07,951 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:07,951 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:07,953 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:07,954 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:07,954 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:07,954 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:07,959 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:07,959 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:07,959 INFO L85 PathProgramCache]: Analyzing trace with hash 1605141586, now seen corresponding path program 1 times [2025-03-04 16:38:07,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:07,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2006107175] [2025-03-04 16:38:07,959 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:07,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:07,982 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-04 16:38:08,011 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 16:38:08,011 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:08,011 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:08,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:08,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:08,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2006107175] [2025-03-04 16:38:08,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2006107175] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:08,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:08,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2025-03-04 16:38:08,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599436170] [2025-03-04 16:38:08,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:08,156 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:08,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:08,156 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2025-03-04 16:38:08,156 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2025-03-04 16:38:08,156 INFO L87 Difference]: Start difference. First operand 458 states and 617 transitions. cyclomatic complexity: 163 Second operand has 9 states, 9 states have (on average 9.0) internal successors, (81), 9 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:08,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:08,624 INFO L93 Difference]: Finished difference Result 463 states and 623 transitions. [2025-03-04 16:38:08,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 463 states and 623 transitions. [2025-03-04 16:38:08,625 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 446 [2025-03-04 16:38:08,626 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 463 states to 463 states and 623 transitions. [2025-03-04 16:38:08,626 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 463 [2025-03-04 16:38:08,627 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 463 [2025-03-04 16:38:08,627 INFO L73 IsDeterministic]: Start isDeterministic. Operand 463 states and 623 transitions. [2025-03-04 16:38:08,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:08,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 463 states and 623 transitions. [2025-03-04 16:38:08,630 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states and 623 transitions. [2025-03-04 16:38:08,632 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 461. [2025-03-04 16:38:08,633 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 461 states, 457 states have (on average 1.3457330415754925) internal successors, (615), 456 states have internal predecessors, (615), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:08,634 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 621 transitions. [2025-03-04 16:38:08,634 INFO L240 hiAutomatonCegarLoop]: Abstraction has 461 states and 621 transitions. [2025-03-04 16:38:08,634 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:38:08,634 INFO L432 stractBuchiCegarLoop]: Abstraction has 461 states and 621 transitions. [2025-03-04 16:38:08,635 INFO L338 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2025-03-04 16:38:08,635 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 461 states and 621 transitions. [2025-03-04 16:38:08,635 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 444 [2025-03-04 16:38:08,635 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:08,636 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:08,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:08,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:08,636 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:08,637 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise79#1 := 256 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296);" "assume 0 == main_~_hj_j~0#1 % 4294967296 / 8192 % 4294967296;main_#t~bitwise80#1 := main_~_ha_hashv~0#1;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 / 4096 % 4294967296;main_#t~bitwise81#1 := main_~_hj_i~0#1;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume 0 == 65536 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;main_#t~bitwise82#1 := main_~_hj_j~0#1;" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:08,637 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:08,637 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 25 times [2025-03-04 16:38:08,637 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:08,637 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115042183] [2025-03-04 16:38:08,637 INFO L95 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2025-03-04 16:38:08,637 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:08,644 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:08,645 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:08,645 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:08,645 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:08,645 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:08,647 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:08,648 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:08,648 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:08,648 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:08,652 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:08,652 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:08,653 INFO L85 PathProgramCache]: Analyzing trace with hash 501808424, now seen corresponding path program 1 times [2025-03-04 16:38:08,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:08,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1147569750] [2025-03-04 16:38:08,653 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:08,653 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:08,675 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-04 16:38:08,699 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 16:38:08,699 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:08,699 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:08,910 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2025-03-04 16:38:08,911 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2025-03-04 16:38:08,911 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1147569750] [2025-03-04 16:38:08,911 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1147569750] provided 1 perfect and 0 imperfect interpolant sequences [2025-03-04 16:38:08,911 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2025-03-04 16:38:08,911 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [11] imperfect sequences [] total 11 [2025-03-04 16:38:08,911 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [328638577] [2025-03-04 16:38:08,911 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2025-03-04 16:38:08,911 INFO L769 eck$LassoCheckResult]: loop already infeasible [2025-03-04 16:38:08,911 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2025-03-04 16:38:08,912 INFO L144 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2025-03-04 16:38:08,912 INFO L146 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2025-03-04 16:38:08,912 INFO L87 Difference]: Start difference. First operand 461 states and 621 transitions. cyclomatic complexity: 164 Second operand has 11 states, 11 states have (on average 7.363636363636363) internal successors, (81), 11 states have internal predecessors, (81), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2025-03-04 16:38:09,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2025-03-04 16:38:09,464 INFO L93 Difference]: Finished difference Result 474 states and 638 transitions. [2025-03-04 16:38:09,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 474 states and 638 transitions. [2025-03-04 16:38:09,466 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 457 [2025-03-04 16:38:09,467 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 474 states to 474 states and 638 transitions. [2025-03-04 16:38:09,467 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 474 [2025-03-04 16:38:09,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 474 [2025-03-04 16:38:09,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 474 states and 638 transitions. [2025-03-04 16:38:09,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2025-03-04 16:38:09,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 474 states and 638 transitions. [2025-03-04 16:38:09,468 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states and 638 transitions. [2025-03-04 16:38:09,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 464. [2025-03-04 16:38:09,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 464 states, 460 states have (on average 1.3434782608695652) internal successors, (618), 459 states have internal predecessors, (618), 3 states have call successors, (3), 1 states have call predecessors, (3), 1 states have return successors, (3), 3 states have call predecessors, (3), 3 states have call successors, (3) [2025-03-04 16:38:09,473 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 624 transitions. [2025-03-04 16:38:09,473 INFO L240 hiAutomatonCegarLoop]: Abstraction has 464 states and 624 transitions. [2025-03-04 16:38:09,474 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2025-03-04 16:38:09,474 INFO L432 stractBuchiCegarLoop]: Abstraction has 464 states and 624 transitions. [2025-03-04 16:38:09,474 INFO L338 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2025-03-04 16:38:09,475 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 464 states and 624 transitions. [2025-03-04 16:38:09,475 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 447 [2025-03-04 16:38:09,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2025-03-04 16:38:09,476 INFO L119 BuchiIsEmpty]: Starting construction of run [2025-03-04 16:38:09,476 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1] [2025-03-04 16:38:09,476 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2025-03-04 16:38:09,477 INFO L752 eck$LassoCheckResult]: Stem: "assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#1(48, 1, 0, 1);call write~init~int#1(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(40, 3);~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset := 3, 0;call write~init~int#2(0, ~#alt_malloc_sizes~0.base, ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 4 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 8 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 12 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 16 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 20 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 24 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 28 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 32 + ~#alt_malloc_sizes~0.offset, 4);call write~init~int#2(0, ~#alt_malloc_sizes~0.base, 36 + ~#alt_malloc_sizes~0.offset, 4);~alt_malloc_balance~0 := 0;~alt_memcmp_count~0 := 0;~alt_bzero_count~0 := 0;" "assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_#t~mem40#1, main_#t~ret41#1.base, main_#t~ret41#1.offset, main_#t~mem42#1, main_#t~mem43#1, main_#t~mem44#1, main_#t~mem46#1, main_#t~mem45#1, main_#t~mem47#1, main_#t~mem48#1, main_#t~mem50#1, main_#t~mem49#1, main_#t~mem51#1, main_#t~mem52#1, main_#t~mem54#1, main_#t~mem53#1, main_#t~mem55#1, main_#t~mem56#1, main_#t~bitwise57#1, main_#t~bitwise58#1, main_#t~bitwise59#1, main_#t~bitwise60#1, main_#t~bitwise61#1, main_#t~bitwise62#1, main_#t~bitwise63#1, main_#t~bitwise64#1, main_#t~bitwise65#1, main_#t~switch66#1, main_#t~mem67#1, main_#t~mem68#1, main_#t~mem69#1, main_#t~mem70#1, main_#t~mem71#1, main_#t~mem72#1, main_#t~mem73#1, main_#t~mem74#1, main_#t~mem75#1, main_#t~mem76#1, main_#t~mem77#1, main_#t~bitwise78#1, main_#t~bitwise79#1, main_#t~bitwise80#1, main_#t~bitwise81#1, main_#t~bitwise82#1, main_#t~bitwise83#1, main_#t~bitwise84#1, main_#t~bitwise85#1, main_#t~bitwise86#1, main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, main_#t~ret87#1.base, main_#t~ret87#1.offset, main_#t~mem88#1.base, main_#t~mem88#1.offset, main_#t~mem89#1.base, main_#t~mem89#1.offset, main_#t~mem90#1.base, main_#t~mem90#1.offset, main_#t~mem91#1.base, main_#t~mem91#1.offset, main_#t~mem92#1.base, main_#t~mem92#1.offset, main_#t~mem93#1.base, main_#t~mem93#1.offset, main_#t~mem94#1.base, main_#t~mem94#1.offset, main_#t~ret95#1.base, main_#t~ret95#1.offset, main_#t~mem96#1.base, main_#t~mem96#1.offset, main_#t~mem97#1.base, main_#t~mem97#1.offset, main_#t~mem98#1.base, main_#t~mem98#1.offset, main_#t~mem99#1.base, main_#t~mem99#1.offset, main_#t~mem100#1.base, main_#t~mem100#1.offset, main_#t~mem101#1.base, main_#t~mem101#1.offset, main_#t~mem102#1.base, main_#t~mem102#1.offset, main_#t~mem103#1.base, main_#t~mem103#1.offset, main_#t~mem104#1.base, main_#t~mem104#1.offset, main_#t~mem105#1.base, main_#t~mem105#1.offset, main_#t~mem106#1, main_#t~mem107#1.base, main_#t~mem107#1.offset, main_#t~mem108#1.base, main_#t~mem108#1.offset, main_#t~mem109#1.base, main_#t~mem109#1.offset, main_#t~mem110#1.base, main_#t~mem110#1.offset, main_#t~mem111#1, main_#t~post112#1, main_#t~mem113#1.base, main_#t~mem113#1.offset, main_#t~mem114#1, main_#t~bitwise115#1, main_#t~mem116#1.base, main_#t~mem116#1.offset, main_#t~mem117#1.base, main_#t~mem117#1.offset, main_#t~mem118#1, main_#t~post119#1, main_#t~mem120#1.base, main_#t~mem120#1.offset, main_#t~mem121#1.base, main_#t~mem121#1.offset, main_#t~mem122#1.base, main_#t~mem122#1.offset, main_#t~mem124#1, main_#t~mem123#1, main_#t~mem125#1.base, main_#t~mem125#1.offset, main_#t~mem126#1, main_#t~short127#1, main_#t~mem128#1.base, main_#t~mem128#1.offset, main_#t~mem129#1, main_#t~ret130#1.base, main_#t~ret130#1.offset, main_#t~mem131#1.base, main_#t~mem131#1.offset, main_#t~mem132#1, main_#t~mem133#1.base, main_#t~mem133#1.offset, main_#t~mem134#1.base, main_#t~mem134#1.offset, main_#t~mem137#1, main_#t~mem135#1.base, main_#t~mem135#1.offset, main_#t~mem136#1, main_#t~bitwise138#1, main_#t~mem139#1.base, main_#t~mem139#1.offset, main_#t~mem142#1, main_#t~mem140#1.base, main_#t~mem140#1.offset, main_#t~mem141#1, main_#t~bitwise143#1, main_#t~mem144#1.base, main_#t~mem144#1.offset, main_#t~mem145#1.base, main_#t~mem145#1.offset, main_#t~mem146#1, main_#t~mem147#1.base, main_#t~mem147#1.offset, main_#t~mem148#1.base, main_#t~mem148#1.offset, main_#t~mem149#1.base, main_#t~mem149#1.offset, main_#t~mem150#1.base, main_#t~mem150#1.offset, main_#t~mem153#1, main_#t~mem151#1.base, main_#t~mem151#1.offset, main_#t~mem152#1, main_#t~bitwise154#1, main_#t~mem155#1, main_#t~pre156#1, main_#t~mem157#1.base, main_#t~mem157#1.offset, main_#t~mem158#1, main_#t~mem159#1.base, main_#t~mem159#1.offset, main_#t~mem160#1, main_#t~post161#1, main_#t~mem165#1, main_#t~mem163#1, main_#t~mem162#1.base, main_#t~mem162#1.offset, main_#t~mem164#1, main_#t~mem166#1, main_#t~post167#1, main_#t~mem168#1.base, main_#t~mem168#1.offset, main_#t~mem169#1.base, main_#t~mem169#1.offset, main_#t~mem170#1.base, main_#t~mem170#1.offset, main_#t~post171#1, main_#t~mem172#1.base, main_#t~mem172#1.offset, main_#t~mem173#1.base, main_#t~mem173#1.offset, main_#t~mem174#1.base, main_#t~mem174#1.offset, main_#t~mem175#1, main_#t~mem176#1.base, main_#t~mem176#1.offset, main_#t~mem177#1, main_#t~mem178#1.base, main_#t~mem178#1.offset, main_#t~mem179#1, main_#t~post180#1, main_#t~mem181#1.base, main_#t~mem181#1.offset, main_#t~mem182#1.base, main_#t~mem182#1.offset, main_#t~mem183#1.base, main_#t~mem183#1.offset, main_#t~mem186#1, main_#t~mem184#1.base, main_#t~mem184#1.offset, main_#t~mem185#1, main_#t~ite189#1, main_#t~mem187#1.base, main_#t~mem187#1.offset, main_#t~mem188#1, main_#t~mem190#1.base, main_#t~mem190#1.offset, main_#t~mem191#1, main_#t~mem192#1.base, main_#t~mem192#1.offset, main_~_he_bkt~0#1, main_~_he_bkt_i~0#1, main_~_he_thh~0#1.base, main_~_he_thh~0#1.offset, main_~_he_hh_nxt~0#1.base, main_~_he_hh_nxt~0#1.offset, main_~_he_new_buckets~0#1.base, main_~_he_new_buckets~0#1.offset, main_~_he_newbkt~0#1.base, main_~_he_newbkt~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, main_~_ha_bkt~0#1, main_~_ha_hashv~0#1, main_#t~mem193#1, main_#t~post194#1, main_#t~mem195#1, main_#t~mem197#1, main_#t~mem196#1, main_#t~mem198#1, main_#t~mem199#1, main_#t~mem201#1, main_#t~mem200#1, main_#t~mem202#1, main_#t~mem203#1, main_#t~mem205#1, main_#t~mem204#1, main_#t~mem206#1, main_#t~mem207#1, main_#t~bitwise208#1, main_#t~bitwise209#1, main_#t~bitwise210#1, main_#t~bitwise211#1, main_#t~bitwise212#1, main_#t~bitwise213#1, main_#t~bitwise214#1, main_#t~bitwise215#1, main_#t~bitwise216#1, main_#t~switch217#1, main_#t~mem218#1, main_#t~mem219#1, main_#t~mem220#1, main_#t~mem221#1, main_#t~mem222#1, main_#t~mem223#1, main_#t~mem224#1, main_#t~mem225#1, main_#t~mem226#1, main_#t~mem227#1, main_#t~mem228#1, main_#t~bitwise229#1, main_#t~bitwise230#1, main_#t~bitwise231#1, main_#t~bitwise232#1, main_#t~bitwise233#1, main_#t~bitwise234#1, main_#t~bitwise235#1, main_#t~bitwise236#1, main_#t~bitwise237#1, main_~_hj_i~1#1, main_~_hj_j~1#1, main_~_hj_k~1#1, main_~_hj_key~1#1.base, main_~_hj_key~1#1.offset, main_#t~mem238#1.base, main_#t~mem238#1.offset, main_#t~mem239#1, main_#t~bitwise240#1, main_#t~mem241#1.base, main_#t~mem241#1.offset, main_#t~mem242#1.base, main_#t~mem242#1.offset, main_#t~mem243#1.base, main_#t~mem243#1.offset, main_#t~mem244#1.base, main_#t~mem244#1.offset, main_#t~mem245#1.base, main_#t~mem245#1.offset, main_#t~mem246#1.base, main_#t~mem246#1.offset, main_#t~mem247#1.base, main_#t~mem247#1.offset, main_#t~mem248#1, main_#t~mem249#1, main_#t~mem250#1, main_#t~short251#1, main_#t~mem252#1.base, main_#t~mem252#1.offset, main_#t~ret253#1, main_#t~mem254#1.base, main_#t~mem254#1.offset, main_#t~mem255#1.base, main_#t~mem255#1.offset, main_#t~mem256#1.base, main_#t~mem256#1.offset, main_#t~mem257#1, main_~_hf_bkt~0#1, main_~_hf_hashv~0#1, main_#t~mem258#1.base, main_#t~mem258#1.offset, main_#t~mem259#1.base, main_#t~mem259#1.offset, main_#t~short260#1, main_#t~mem261#1.base, main_#t~mem261#1.offset, main_#t~mem262#1.base, main_#t~mem262#1.offset, main_#t~mem263#1.base, main_#t~mem263#1.offset, main_#t~mem264#1, main_#t~mem265#1.base, main_#t~mem265#1.offset, main_#t~mem266#1.base, main_#t~mem266#1.offset, main_#t~mem267#1.base, main_#t~mem267#1.offset, main_#t~mem268#1.base, main_#t~mem268#1.offset, main_#t~mem269#1.base, main_#t~mem269#1.offset, main_#t~mem270#1.base, main_#t~mem270#1.offset, main_#t~mem271#1, main_#t~mem272#1.base, main_#t~mem272#1.offset, main_#t~mem273#1.base, main_#t~mem273#1.offset, main_#t~mem274#1.base, main_#t~mem274#1.offset, main_#t~mem275#1, main_#t~mem276#1.base, main_#t~mem276#1.offset, main_#t~mem277#1.base, main_#t~mem277#1.offset, main_#t~mem278#1.base, main_#t~mem278#1.offset, main_#t~mem279#1.base, main_#t~mem279#1.offset, main_#t~mem280#1.base, main_#t~mem280#1.offset, main_#t~mem281#1, main_#t~mem282#1.base, main_#t~mem282#1.offset, main_#t~mem285#1, main_#t~mem283#1.base, main_#t~mem283#1.offset, main_#t~mem284#1, main_#t~bitwise286#1, main_#t~mem287#1.base, main_#t~mem287#1.offset, main_#t~mem288#1.base, main_#t~mem288#1.offset, main_#t~mem289#1, main_#t~post290#1, main_#t~mem291#1.base, main_#t~mem291#1.offset, main_#t~mem292#1.base, main_#t~mem292#1.offset, main_#t~mem293#1.base, main_#t~mem293#1.offset, main_#t~mem294#1.base, main_#t~mem294#1.offset, main_#t~mem295#1.base, main_#t~mem295#1.offset, main_#t~mem296#1.base, main_#t~mem296#1.offset, main_#t~mem297#1.base, main_#t~mem297#1.offset, main_#t~mem298#1.base, main_#t~mem298#1.offset, main_~_hd_head~0#1.base, main_~_hd_head~0#1.offset, main_#t~mem299#1.base, main_#t~mem299#1.offset, main_#t~mem300#1, main_#t~post301#1, main_~_hd_bkt~0#1, main_~_hd_hh_del~0#1.base, main_~_hd_hh_del~0#1.offset, main_#t~mem302#1, main_#t~post303#1, main_#t~mem304#1.base, main_#t~mem304#1.offset, main_#t~ite306#1.base, main_#t~ite306#1.offset, main_#t~mem305#1.base, main_#t~mem305#1.offset, main_#t~mem307#1.base, main_#t~mem307#1.offset, main_#t~mem308#1.base, main_#t~mem308#1.offset, main_#t~short309#1, main_#t~mem310#1.base, main_#t~mem310#1.offset, main_#t~mem311#1.base, main_#t~mem311#1.offset, main_#t~mem312#1.base, main_#t~mem312#1.offset, main_#t~mem313#1, main_#t~mem314#1.base, main_#t~mem314#1.offset, main_#t~mem315#1.base, main_#t~mem315#1.offset, main_#t~mem316#1.base, main_#t~mem316#1.offset, main_#t~mem317#1.base, main_#t~mem317#1.offset, main_#t~mem318#1.base, main_#t~mem318#1.offset, main_#t~mem319#1.base, main_#t~mem319#1.offset, main_#t~mem320#1, main_#t~mem321#1.base, main_#t~mem321#1.offset, main_#t~mem322#1.base, main_#t~mem322#1.offset, main_#t~mem323#1.base, main_#t~mem323#1.offset, main_#t~mem324#1, main_#t~mem325#1.base, main_#t~mem325#1.offset, main_#t~mem326#1.base, main_#t~mem326#1.offset, main_#t~mem327#1.base, main_#t~mem327#1.offset, main_#t~mem328#1.base, main_#t~mem328#1.offset, main_#t~mem329#1.base, main_#t~mem329#1.offset, main_#t~mem330#1, main_#t~mem331#1.base, main_#t~mem331#1.offset, main_#t~mem334#1, main_#t~mem332#1.base, main_#t~mem332#1.offset, main_#t~mem333#1, main_#t~bitwise335#1, main_#t~mem336#1.base, main_#t~mem336#1.offset, main_#t~mem337#1.base, main_#t~mem337#1.offset, main_#t~mem338#1, main_#t~post339#1, main_#t~mem340#1.base, main_#t~mem340#1.offset, main_#t~mem341#1.base, main_#t~mem341#1.offset, main_#t~mem342#1.base, main_#t~mem342#1.offset, main_#t~mem343#1.base, main_#t~mem343#1.offset, main_#t~mem344#1.base, main_#t~mem344#1.offset, main_#t~mem345#1.base, main_#t~mem345#1.offset, main_#t~mem346#1.base, main_#t~mem346#1.offset, main_#t~mem347#1.base, main_#t~mem347#1.offset, main_~_hd_head~1#1.base, main_~_hd_head~1#1.offset, main_#t~mem348#1.base, main_#t~mem348#1.offset, main_#t~mem349#1, main_#t~post350#1, main_~_hd_bkt~1#1, main_~_hd_hh_del~1#1.base, main_~_hd_hh_del~1#1.offset, main_#t~ite352#1.base, main_#t~ite352#1.offset, main_#t~mem351#1.base, main_#t~mem351#1.offset, main_~#i~0#1.base, main_~#i~0#1.offset, main_~user~0#1.base, main_~user~0#1.offset, main_~tmp~0#1.base, main_~tmp~0#1.offset, main_~users~0#1.base, main_~users~0#1.offset, main_~temp~0#1.base, main_~temp~0#1.offset;call main_~#i~0#1.base, main_~#i~0#1.offset := #Ultimate.allocOnStack(4);havoc main_~user~0#1.base, main_~user~0#1.offset;havoc main_~tmp~0#1.base, main_~tmp~0#1.offset;main_~users~0#1.base, main_~users~0#1.offset := 0, 0;call write~int#3(0, main_~#i~0#1.base, main_~#i~0#1.offset, 4);" [2025-03-04 16:38:09,477 INFO L754 eck$LassoCheckResult]: Loop: "assume true;call main_#t~mem40#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);" "assume main_#t~mem40#1 < 10;havoc main_#t~mem40#1;assume { :begin_inline_real_malloc } true;real_malloc_#in~n#1 := 40;havoc real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;real_malloc_~n#1 := real_malloc_#in~n#1;call real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset := #Ultimate.allocOnHeap(real_malloc_~n#1 % 4294967296);real_malloc_#res#1.base, real_malloc_#res#1.offset := real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset;" "main_#t~ret41#1.base, main_#t~ret41#1.offset := real_malloc_#res#1.base, real_malloc_#res#1.offset;havoc real_malloc_#t~malloc39#1.base, real_malloc_#t~malloc39#1.offset, real_malloc_~n#1;havoc real_malloc_#in~n#1;assume { :end_inline_real_malloc } true;main_~user~0#1.base, main_~user~0#1.offset := main_#t~ret41#1.base, main_#t~ret41#1.offset;havoc main_#t~ret41#1.base, main_#t~ret41#1.offset;" "assume !(main_~user~0#1.base == 0 && main_~user~0#1.offset == 0);" "call main_#t~mem42#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem42#1, main_~user~0#1.base, main_~user~0#1.offset, 4);havoc main_#t~mem42#1;call main_#t~mem43#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call main_#t~mem44#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);call write~int#0(main_#t~mem43#1 * main_#t~mem44#1, main_~user~0#1.base, 4 + main_~user~0#1.offset, 4);havoc main_#t~mem43#1;havoc main_#t~mem44#1;" "assume true;havoc main_~_ha_hashv~0#1;" "assume true;havoc main_~_hj_i~0#1;havoc main_~_hj_j~0#1;havoc main_~_hj_k~0#1;main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset := main_~user~0#1.base, main_~user~0#1.offset;main_~_ha_hashv~0#1 := 4276993775;main_~_hj_j~0#1 := 2654435769;main_~_hj_i~0#1 := main_~_hj_j~0#1;main_~_hj_k~0#1 := 4;" "assume !(main_~_hj_k~0#1 % 4294967296 >= 12);main_~_ha_hashv~0#1 := 4 + main_~_ha_hashv~0#1;main_#t~switch66#1 := 11 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 10 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 9 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 8 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 7 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 6 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 5 == main_~_hj_k~0#1;" "assume !main_#t~switch66#1;" "main_#t~switch66#1 := main_#t~switch66#1 || 4 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem74#1 := read~int#0(main_~_hj_key~0#1.base, 3 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 16777216 * (main_#t~mem74#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 3 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem75#1 := read~int#0(main_~_hj_key~0#1.base, 2 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 65536 * (main_#t~mem75#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 2 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem76#1 := read~int#0(main_~_hj_key~0#1.base, 1 + main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + 256 * (main_#t~mem76#1 % 256 % 4294967296);" "main_#t~switch66#1 := main_#t~switch66#1 || 1 == main_~_hj_k~0#1;" "assume main_#t~switch66#1;call main_#t~mem77#1 := read~int#0(main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset, 1);main_~_hj_i~0#1 := main_~_hj_i~0#1 + (if main_#t~mem77#1 % 256 % 4294967296 <= 2147483647 then main_#t~mem77#1 % 256 % 4294967296 else main_#t~mem77#1 % 256 % 4294967296 - 4294967296);" "havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;havoc main_#t~switch66#1;havoc main_#t~mem67#1;havoc main_#t~mem68#1;havoc main_#t~mem69#1;havoc main_#t~mem70#1;havoc main_#t~mem71#1;havoc main_#t~mem72#1;havoc main_#t~mem73#1;havoc main_#t~mem74#1;havoc main_#t~mem75#1;havoc main_#t~mem76#1;havoc main_#t~mem77#1;" "assume true;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume !(0 == main_~_hj_i~0#1 % 4294967296);" "assume !(0 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "assume !(main_~_hj_i~0#1 % 4294967296 == main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296);" "havoc main_#t~bitwise78#1;assume main_#t~bitwise78#1 % 4294967296 <= main_~_hj_i~0#1 % 4294967296 + main_~_ha_hashv~0#1 % 4294967296 / 8192 % 4294967296;" "main_~_hj_i~0#1 := main_#t~bitwise78#1;havoc main_#t~bitwise78#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume !(0 == main_~_hj_j~0#1 % 4294967296);" "assume !(0 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "assume !(main_~_hj_j~0#1 % 4294967296 == 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296);" "havoc main_#t~bitwise79#1;assume main_#t~bitwise79#1 % 4294967296 <= main_~_hj_j~0#1 % 4294967296 + 256 * (main_~_hj_i~0#1 % 4294967296) % 4294967296;" "main_~_hj_j~0#1 := main_#t~bitwise79#1;havoc main_#t~bitwise79#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise80#1 := main_~_hj_j~0#1 % 4294967296 / 8192;" "main_~_ha_hashv~0#1 := main_#t~bitwise80#1;havoc main_#t~bitwise80#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise81#1 := main_~_ha_hashv~0#1 % 4294967296 / 4096;" "main_~_hj_i~0#1 := main_#t~bitwise81#1;havoc main_#t~bitwise81#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise82#1 := 65536 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise82#1;havoc main_#t~bitwise82#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise83#1 := main_~_hj_j~0#1 % 4294967296 / 32;" "main_~_ha_hashv~0#1 := main_#t~bitwise83#1;havoc main_#t~bitwise83#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_hj_j~0#1;main_~_hj_i~0#1 := main_~_hj_i~0#1 - main_~_ha_hashv~0#1;" "assume 0 == main_~_hj_i~0#1 % 4294967296;main_#t~bitwise84#1 := main_~_ha_hashv~0#1 % 4294967296 / 8;" "main_~_hj_i~0#1 := main_#t~bitwise84#1;havoc main_#t~bitwise84#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_ha_hashv~0#1;main_~_hj_j~0#1 := main_~_hj_j~0#1 - main_~_hj_i~0#1;" "assume 0 == main_~_hj_j~0#1 % 4294967296;main_#t~bitwise85#1 := 1024 * (main_~_hj_i~0#1 % 4294967296);" "main_~_hj_j~0#1 := main_#t~bitwise85#1;havoc main_#t~bitwise85#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_i~0#1;main_~_ha_hashv~0#1 := main_~_ha_hashv~0#1 - main_~_hj_j~0#1;" "assume 0 == main_~_ha_hashv~0#1 % 4294967296;main_#t~bitwise86#1 := main_~_hj_j~0#1 % 4294967296 / 32768;" "main_~_ha_hashv~0#1 := main_#t~bitwise86#1;havoc main_#t~bitwise86#1;" "assume !false;" "havoc main_~_hj_i~0#1, main_~_hj_j~0#1, main_~_hj_k~0#1, main_~_hj_key~0#1.base, main_~_hj_key~0#1.offset;" "assume !false;" "assume !false;" "assume true;call write~int#0(main_~_ha_hashv~0#1, main_~user~0#1.base, 36 + main_~user~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_~user~0#1.base, 28 + main_~user~0#1.offset, 4);call write~int#0(4, main_~user~0#1.base, 32 + main_~user~0#1.offset, 4);" "assume !(main_~users~0#1.base == 0 && main_~users~0#1.offset == 0);call main_#t~mem102#1.base, main_#t~mem102#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem102#1.base, main_#t~mem102#1.offset, main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);havoc main_#t~mem102#1.base, main_#t~mem102#1.offset;" "assume true;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 16 + main_~user~0#1.offset, 4);call main_#t~mem103#1.base, main_#t~mem103#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem104#1.base, main_#t~mem104#1.offset := read~$Pointer$#0(main_#t~mem103#1.base, 16 + main_#t~mem103#1.offset, 4);call main_#t~mem105#1.base, main_#t~mem105#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem106#1 := read~int#0(main_#t~mem105#1.base, 20 + main_#t~mem105#1.offset, 4);call write~$Pointer$#0(main_#t~mem104#1.base, main_#t~mem104#1.offset - main_#t~mem106#1, main_~user~0#1.base, 12 + main_~user~0#1.offset, 4);havoc main_#t~mem103#1.base, main_#t~mem103#1.offset;havoc main_#t~mem104#1.base, main_#t~mem104#1.offset;havoc main_#t~mem105#1.base, main_#t~mem105#1.offset;havoc main_#t~mem106#1;call main_#t~mem107#1.base, main_#t~mem107#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem108#1.base, main_#t~mem108#1.offset := read~$Pointer$#0(main_#t~mem107#1.base, 16 + main_#t~mem107#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, main_~user~0#1.offset, main_#t~mem108#1.base, 8 + main_#t~mem108#1.offset, 4);havoc main_#t~mem107#1.base, main_#t~mem107#1.offset;havoc main_#t~mem108#1.base, main_#t~mem108#1.offset;call main_#t~mem109#1.base, main_#t~mem109#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem109#1.base, 16 + main_#t~mem109#1.offset, 4);havoc main_#t~mem109#1.base, main_#t~mem109#1.offset;" "assume !false;" "assume true;havoc main_~_ha_bkt~0#1;call main_#t~mem110#1.base, main_#t~mem110#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem111#1 := read~int#0(main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);main_#t~post112#1 := main_#t~mem111#1;call write~int#0(1 + main_#t~post112#1, main_#t~mem110#1.base, 12 + main_#t~mem110#1.offset, 4);havoc main_#t~mem110#1.base, main_#t~mem110#1.offset;havoc main_#t~mem111#1;havoc main_#t~post112#1;" "assume true;call main_#t~mem113#1.base, main_#t~mem113#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem114#1 := read~int#0(main_#t~mem113#1.base, 4 + main_#t~mem113#1.offset, 4);" "assume 0 == main_~_ha_hashv~0#1 % 4294967296 || 0 == (main_#t~mem114#1 - 1) % 4294967296;main_#t~bitwise115#1 := 0;" "main_~_ha_bkt~0#1 := main_#t~bitwise115#1;havoc main_#t~mem113#1.base, main_#t~mem113#1.offset;havoc main_#t~mem114#1;havoc main_#t~bitwise115#1;" "assume !false;" "assume true;call main_#t~mem116#1.base, main_#t~mem116#1.offset := read~$Pointer$#0(main_~users~0#1.base, 8 + main_~users~0#1.offset, 4);call main_#t~mem117#1.base, main_#t~mem117#1.offset := read~$Pointer$#0(main_#t~mem116#1.base, main_#t~mem116#1.offset, 4);main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset := main_#t~mem117#1.base, main_#t~mem117#1.offset + 12 * (if main_~_ha_bkt~0#1 % 4294967296 % 4294967296 <= 2147483647 then main_~_ha_bkt~0#1 % 4294967296 % 4294967296 else main_~_ha_bkt~0#1 % 4294967296 % 4294967296 - 4294967296);havoc main_#t~mem116#1.base, main_#t~mem116#1.offset;havoc main_#t~mem117#1.base, main_#t~mem117#1.offset;call main_#t~mem118#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);main_#t~post119#1 := main_#t~mem118#1;call write~int#0(1 + main_#t~post119#1, main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);havoc main_#t~mem118#1;havoc main_#t~post119#1;call main_#t~mem120#1.base, main_#t~mem120#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_#t~mem120#1.base, main_#t~mem120#1.offset, main_~user~0#1.base, 24 + main_~user~0#1.offset, 4);havoc main_#t~mem120#1.base, main_#t~mem120#1.offset;call write~$Pointer$#0(0, 0, main_~user~0#1.base, 20 + main_~user~0#1.offset, 4);call main_#t~mem121#1.base, main_#t~mem121#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);" "assume main_#t~mem121#1.base != 0 || main_#t~mem121#1.offset != 0;havoc main_#t~mem121#1.base, main_#t~mem121#1.offset;call main_#t~mem122#1.base, main_#t~mem122#1.offset := read~$Pointer$#0(main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_#t~mem122#1.base, 12 + main_#t~mem122#1.offset, 4);havoc main_#t~mem122#1.base, main_#t~mem122#1.offset;" "call write~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset, 4);call main_#t~mem124#1 := read~int#0(main_~_ha_head~0#1.base, 4 + main_~_ha_head~0#1.offset, 4);call main_#t~mem123#1 := read~int#0(main_~_ha_head~0#1.base, 8 + main_~_ha_head~0#1.offset, 4);main_#t~short127#1 := main_#t~mem124#1 % 4294967296 >= 10 * (1 + main_#t~mem123#1) % 4294967296;" "assume main_#t~short127#1;call main_#t~mem125#1.base, main_#t~mem125#1.offset := read~$Pointer$#0(main_~user~0#1.base, 8 + main_~user~0#1.offset, 4);call main_#t~mem126#1 := read~int#0(main_#t~mem125#1.base, 36 + main_#t~mem125#1.offset, 4);main_#t~short127#1 := 0 == main_#t~mem126#1 % 4294967296;" "assume !main_#t~short127#1;havoc main_#t~mem124#1;havoc main_#t~mem123#1;havoc main_#t~mem125#1.base, main_#t~mem125#1.offset;havoc main_#t~mem126#1;havoc main_#t~short127#1;" "havoc main_~_ha_head~0#1.base, main_~_ha_head~0#1.offset;" "assume !false;" "havoc main_~_ha_bkt~0#1;" "assume !false;" "assume !false;" "havoc main_~_ha_hashv~0#1;" "assume !false;" "call main_#t~mem193#1 := read~int#3(main_~#i~0#1.base, main_~#i~0#1.offset, 4);main_#t~post194#1 := main_#t~mem193#1;call write~int#3(1 + main_#t~post194#1, main_~#i~0#1.base, main_~#i~0#1.offset, 4);havoc main_#t~mem193#1;havoc main_#t~post194#1;" [2025-03-04 16:38:09,477 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:09,477 INFO L85 PathProgramCache]: Analyzing trace with hash 28096, now seen corresponding path program 26 times [2025-03-04 16:38:09,477 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:09,478 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [608359314] [2025-03-04 16:38:09,478 INFO L95 rtionOrderModulation]: Changing assertion order to OUTSIDE_LOOP_FIRST1 [2025-03-04 16:38:09,478 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:09,485 INFO L108 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:09,487 INFO L111 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:09,487 INFO L114 AnnotateAndAsserter]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2025-03-04 16:38:09,487 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:09,487 INFO L348 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2025-03-04 16:38:09,489 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 2 statements into 1 equivalence classes. [2025-03-04 16:38:09,490 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 2 of 2 statements. [2025-03-04 16:38:09,490 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:09,490 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is sat [2025-03-04 16:38:09,494 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2025-03-04 16:38:09,495 INFO L157 PredicateUnifier]: Initialized classic predicate unifier [2025-03-04 16:38:09,496 INFO L85 PathProgramCache]: Analyzing trace with hash 1766980165, now seen corresponding path program 1 times [2025-03-04 16:38:09,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2025-03-04 16:38:09,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176430161] [2025-03-04 16:38:09,496 INFO L97 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2025-03-04 16:38:09,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2025-03-04 16:38:09,521 INFO L108 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY partitioned 81 statements into 1 equivalence classes. [2025-03-04 16:38:09,611 INFO L111 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) and asserted 81 of 81 statements. [2025-03-04 16:38:09,611 INFO L114 AnnotateAndAsserter]: Assert order NOT_INCREMENTALLY issued 1 check-sat command(s) [2025-03-04 16:38:09,611 INFO L115 AnnotateAndAsserter]: Conjunction of SSA is unsat [2025-03-04 16:38:21,889 WARN L286 SmtUtils]: Spent 12.01s on a formula simplification that was a NOOP. DAG size: 32 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-04 16:38:29,366 WARN L286 SmtUtils]: Spent 7.47s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify) [2025-03-04 16:38:55,880 WARN L286 SmtUtils]: Spent 24.01s on a formula simplification that was a NOOP. DAG size: 10 (called from [L 728] de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher.simplify)